Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x5C byte (0x0)
mem_usage : registers
protection : not protected
SSI Transmit Data Register n
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STXn : SSI Transmit Data
bits : 0 - 31 (32 bit)
access : read-write
SSI Receive Data Register n
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SRXn : SSI Receive Data
bits : 0 - 31 (32 bit)
access : read-only
SSI Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSIEN : SSIEN - SSI Enable This bit is used to enable/disable the SSI
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
SSI is disabled.
0x1 : ENABLED
SSI is enabled.
End of enumeration elements list.
TE : Transmit Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Transmit section disabled.
0x1 : ENABLED
Transmit section enabled.
End of enumeration elements list.
RE : Receive Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Receive section disabled.
0x1 : ENABLED
Receive section enabled.
End of enumeration elements list.
NET : Network Mode. This bit controls whether SSI is in network mode or not.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Network mode not selected.
0x1 : ENABLED
Network mode selected.
End of enumeration elements list.
SYN : Synchronous Mode
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ASYNC_MODE
Asynchronous mode selected.
0x1 : SYNC_MODE
Synchronous mode selected.
End of enumeration elements list.
I2S_MODE : I2S Mode Select
bits : 5 - 6 (2 bit)
access : read-write
SYS_CLK_EN : Network Clock (Oversampling Clock) Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_OUTPUT
network clock not output on SRCK port.
0x1 : OUTPUT
network clock output on SRCK port.
End of enumeration elements list.
TCH_EN : Two-Channel Operation Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Two-channel mode disabled.
0x1 : ENABLED
Two-channel mode enabled.
End of enumeration elements list.
CLK_IST : Clock Idle State
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : IDLE_0
Clock idle state is '0'.
0x1 : IDLE_1
Clock idle state is '1'.
End of enumeration elements list.
TFR_CLK_DIS : Transmit Frame Clock Disable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : CONTINUE
Continue Frame-sync/Clock generation after current frame during which TE is cleared. This may be required when Frame-sync and Clocks are required from SSI, even when no data is to be received.
0x1 : STOP
Stop Frame-sync/Clock generation at next frame boundary. This will be effective also in case where transmitter is already disabled in current or previous frames.
End of enumeration elements list.
RFR_CLK_DIS : Receive Frame Clock Disable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : CONTINUE
Continue Frame-sync/Clock generation after current frame during which RE is cleared. This may be required when Frame-sync and Clocks are required from SSI, even when no data is to be received.
0x1 : STOP
Stop Frame-sync/Clock generation at next frame boundary. This will be effective also in case where receiver is already disabled in current or previous frames.
End of enumeration elements list.
SYNC_TX_FS : SYNC_FS_TX bit provides a safe window for TE to be visible to the internal circuit which is just after FS occurrence
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : TE_NOT_LATCHED
TE not latched with FS occurrence & used directly for transmitter enable/disable.
0x1 : TE_LATCHED
TE latched with FS occurrence & latched-TE used for transmitter enable/disable.
End of enumeration elements list.
SSI Interrupt Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFE0 : Transmit FIFO Empty 0
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : HAS_DATA
Transmit FIFO0 has data for transmission.
0x1 : EMPTY
Transmit FIFO0 is empty.
End of enumeration elements list.
TFE1 : Transmit FIFO Empty 1
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : HAS_DATA
Transmit FIFO1 has data for transmission.
0x1 : EMPTY
Transmit FIFO1 is empty.
End of enumeration elements list.
RFF0 : Receive FIFO Full 0
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : NOT_FULL
Space available in Receive FIFO0.
0x1 : FULL
Receive FIFO0 is full.
End of enumeration elements list.
RFF1 : Receive FIFO Full 1
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : NOT_FULL
Space available in Receive FIFO1.
0x1 : FULL
Receive FIFO1 is full.
End of enumeration elements list.
RLS : Receive Last Time Slot
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : RLS_0
Current time slot is not last time slot of frame.
0x1 : RLS_1
Current time slot is the last receive time slot of frame.
End of enumeration elements list.
TLS : Transmit Last Time Slot
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : TLS_0
Current time slot is not last time slot of frame.
0x1 : TLS_1
Current time slot is the last transmit time slot of frame.
End of enumeration elements list.
RFS : Receive Frame Sync
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : RFS_0
No Occurrence of Receive frame sync.
0x1 : RFS_1
Receive frame sync occurred during reception of next word in SRX registers.
End of enumeration elements list.
TFS : Transmit Frame Sync
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : TFS_0
No Occurrence of Transmit frame sync.
0x1 : TFS_1
Transmit frame sync occurred during transmission of last word written to STX registers.
End of enumeration elements list.
TUE0 : Transmitter Underrun Error 0
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : TUE0_0
Default interrupt issued to the Core.
0x1 : TUE0_1
Exception interrupt issued to the Core.
End of enumeration elements list.
TUE1 : Transmitter Underrun Error 1
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : TUE1_0
Default interrupt issued to the Core.
0x1 : TUE1_1
Exception interrupt issued to the Core.
End of enumeration elements list.
ROE0 : Receiver Overrun Error 0
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : ROE0_0
Default interrupt issued to the Core.
0x1 : ROE0_1
Exception interrupt issued to the Core.
End of enumeration elements list.
ROE1 : Receiver Overrun Error 1
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ROE1_0
Default interrupt issued to the Core.
0x1 : ROE1_1
Exception interrupt issued to the Core.
End of enumeration elements list.
TDE0 : Transmit Data Register Empty 0
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : TDE0_0
Data available for transmission.
0x1 : TDE0_1
Data needs to be written by the Core for transmission.
End of enumeration elements list.
TDE1 : Transmit Data Register Empty 1
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : TDE1_0
Data available for transmission.
0x1 : TDE1_1
Data needs to be written by the Core for transmission.
End of enumeration elements list.
RDR0 : Receive Data Ready 0
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : RDR0_0
No new data for Core to read.
0x1 : RDR0_1
New data for Core to read.
End of enumeration elements list.
RDR1 : Receive Data Ready 1
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : RDR1_0
No new data for Core to read.
0x1 : RDR1_1
New data for Core to read.
End of enumeration elements list.
RXT : Receive Tag Updated
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : RXT_0
No change in SATAG register.
0x1 : RXT_1
SATAG register updated with different value.
End of enumeration elements list.
CMDDU : Command Data Register Updated
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : CMDDU_0
No change in SACDAT register.
0x1 : CMDDU_1
SACDAT register updated with different value.
End of enumeration elements list.
CMDAU : Command Address Register Updated
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : CMDAU_0
No change in SACADD register.
0x1 : CMDAU_1
SACADD register updated with different value.
End of enumeration elements list.
TFRC : Transmit Frame Complete
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : TFRC_0
End of Frame not reached
0x1 : TFRC_1
End of frame reached after disabling TE or disabling TFR_CLK_DIS, when transmitter is already disabled.
End of enumeration elements list.
RFRC : Receive Frame Complete
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : RFRC_0
End of Frame not reached
0x1 : RFRC_1
End of frame reached after disabling RE or disabling RFR_CLK_DIS, when receiver is already disabled.
End of enumeration elements list.
SSI Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFE0IE : Transmit FIFO Empty 0 Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TFE0IE_0
Corresponding status bit cannot issue interrupt.
0x1 : TFE0IE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TFE1IE : Transmit FIFO Empty 1 Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TFE1IE_0
Corresponding status bit cannot issue interrupt.
0x1 : TFE1IE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RFF0IE : Receive FIFO Full 0 Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : RFF0IE_0
Corresponding status bit cannot issue interrupt.
0x1 : RFF0IE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RFF1IE : Receive FIFO Full 1 Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RFF1IE_0
Corresponding status bit cannot issue interrupt.
0x1 : RFF1IE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RLSIE : Receive Last Time Slot Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : RLSIE_0
Corresponding status bit cannot issue interrupt.
0x1 : RLSIE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TLSIE : Transmit Last Time Slot Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : TLSIE_0
Corresponding status bit cannot issue interrupt.
0x1 : TLSIE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RFSIE : Receive Frame Sync Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : RFSIE_0
Corresponding status bit cannot issue interrupt.
0x1 : RFSIE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TFSIE : Transmit Frame Sync Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : TFSIE_0
Corresponding status bit cannot issue interrupt.
0x1 : TFSIE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TUE0IE : Transmitter Underrun Error 0 Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : TUE0IE_0
Corresponding status bit cannot issue interrupt.
0x1 : TUE0IE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TUE1IE : Transmitter Underrun Error 1 Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : TUE1IE_0
Corresponding status bit cannot issue interrupt.
0x1 : TUE1IE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
ROE0IE : Receiver Overrun Error 0 Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : ROE0IE_0
Corresponding status bit cannot issue interrupt.
0x1 : ROE0IE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
ROE1IE : Receiver Overrun Error 1 Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ROE1IE_0
Corresponding status bit cannot issue interrupt.
0x1 : ROE1IE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TDE0IE : Transmit Data Register Empty 0 Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : TDE0IE_0
Corresponding status bit cannot issue interrupt.
0x1 : TDE0IE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TDE1IE : Transmit Data Register Empty 1 Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : TDE1IE_0
Corresponding status bit cannot issue interrupt.
0x1 : TDE1IE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RDR0IE : Receive Data Ready 0 Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : RDR0IE_0
Corresponding status bit cannot issue interrupt.
0x1 : RDR0IE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RDR1IE : Receive Data Ready 1 Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : RDR1IE_0
Corresponding status bit cannot issue interrupt.
0x1 : RDR1IE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RXTIE : Receive Tag Updated Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : RXTIE_0
Corresponding status bit cannot issue interrupt.
0x1 : RXTIE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
CMDDUIE : Command Data Register Updated Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : CMDDUIE_0
Corresponding status bit cannot issue interrupt.
0x1 : CMDDUIE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
CMDAUIE : Command Address Register Updated Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : CMDAUIE_0
Corresponding status bit cannot issue interrupt.
0x1 : CMDAUIE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TIE : Transmit Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : TIE_0
SSI Transmitter Interrupt requests disabled.
0x1 : TIE_1
SSI Transmitter Interrupt requests enabled.
End of enumeration elements list.
TDMAE : Transmit DMA Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : TDMAE_0
SSI Transmitter DMA requests disabled.
0x1 : TDMAE_1
SSI Transmitter DMA requests enabled.
End of enumeration elements list.
RIE : Receive Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : RIE_0
SSI Receiver Interrupt requests disabled.
0x1 : RIE_1
SSI Receiver Interrupt requests enabled.
End of enumeration elements list.
RDMAE : Receive DMA Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : RDMAE_0
SSI Receiver DMA requests disabled.
0x1 : RDMAE_1
SSI Receiver DMA requests enabled.
End of enumeration elements list.
TFRCIE : Transmit Frame Complete Interrupt Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TFRCIE_0
Corresponding status bit cannot issue interrupt.
0x1 : TFRCIE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RFRCIE : Receive Frame Complete Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : RFRCIE_0
Corresponding status bit cannot issue interrupt.
0x1 : RFRCIE_1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
SSI Receive Data Register n
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SRXn : SSI Receive Data
bits : 0 - 31 (32 bit)
access : read-only
SSI Transmit Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEFS : Transmit Early Frame Sync
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FIRST_BIT
Transmit frame sync initiated as the first bit of data is transmitted.
0x1 : ONE_BIT_BEFORE
Transmit frame sync is initiated one bit before the data is transmitted.
End of enumeration elements list.
TFSL : Transmit Frame Sync Length
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ONE_WORD
Transmit frame sync is one-word long.
0x1 : ONE_CLOCK_BIT
Transmit frame sync is one-clock-bit long.
End of enumeration elements list.
TFSI : Transmit Frame Sync Invert
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ACTIVE_HIGH
Transmit frame sync is active high.
0x1 : ACTIVE_LOW
Transmit frame sync is active low.
End of enumeration elements list.
TSCKP : Transmit Clock Polarity
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Data clocked out on rising edge of bit clock.
0x1 : FALLING_EDGE
Data clocked out on falling edge of bit clock.
End of enumeration elements list.
TSHFD : Transmit Shift Direction
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : MSB_FIRST
Data transmitted MSB first.
0x1 : LSB_FIRST
Data transmitted LSB first.
End of enumeration elements list.
TXDIR : Transmit Clock Direction
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : EXTERNAL
Transmit Clock is external.
0x1 : INTERNAL
Transmit Clock generated internally.
End of enumeration elements list.
TFDIR : Transmit Frame Direction
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : EXTERNAL
Frame Sync is external.
0x1 : INTERNAL
Frame Sync generated internally.
End of enumeration elements list.
TFEN0 : Transmit FIFO Enable 0
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : TFEN0_0
Transmit FIFO 0 disabled.
0x1 : TFEN0_1
Transmit FIFO 0 enabled.
End of enumeration elements list.
TFEN1 : Transmit FIFO Enable 1
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : TFEN1_0
Transmit FIFO 1 disabled.
0x1 : TFEN1_1
Transmit FIFO 1 enabled.
End of enumeration elements list.
TXBIT0 : Transmit Bit 0
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : MSB_ALIGNED
Shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or 12) of transmit shift register (MSB aligned).
0x1 : LSB_ALIGNED
Shifting with respect to bit 0 of transmit shift register (LSB aligned).
End of enumeration elements list.
SSI Receive Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFS : Receive Early Frame Sync
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FIRST_BIT
Receive frame sync initiated as the first bit of data is received.
0x1 : ONE_BIT_BEFORE
Receive frame sync is initiated one bit before the data is received.
End of enumeration elements list.
RFSL : Receive Frame Sync Length
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ONE_WORD
Receive frame sync is one-word long.
0x1 : ONE_CLOCK_BIT
Receive frame sync is one-clock-bit long.
End of enumeration elements list.
RFSI : Receive Frame Sync Invert
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ACTIVE_HIGH
Receive frame sync is active high.
0x1 : ACTIVE_LOW
Receive frame sync is active low.
End of enumeration elements list.
RSCKP : Receive Clock Polarity
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FALLING_EDGE
Data latched on falling edge of bit clock.
0x1 : RISING_EDGE
Data latched on rising edge of bit clock.
End of enumeration elements list.
RSHFD : Receive Shift Direction
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : MSB_FIRST
Data received MSB first.
0x1 : LSB_FIRST
Data received LSB first.
End of enumeration elements list.
RXDIR : Receive Clock Direction
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : EXTERNAL
Receive Clock is external.
0x1 : INTERNAL
Receive Clock generated internally.
End of enumeration elements list.
RFDIR : Receive Frame Direction
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : EXTERNAL
Frame Sync is external.
0x1 : INTERNAL
Frame Sync generated internally.
End of enumeration elements list.
RFEN0 : Receive FIFO Enable 0
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : RFEN0_0
Receive FIFO 0 disabled.
0x1 : RFEN0_1
Receive FIFO 0 enabled.
End of enumeration elements list.
RFEN1 : Receive FIFO Enable 1
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : RFEN1_0
Receive FIFO 1 disabled.
0x1 : RFEN1_1
Receive FIFO 1 enabled.
End of enumeration elements list.
RXBIT0 : Receive Bit 0
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : MSB_ALIGNED
Shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or 12) of receive shift register (MSB aligned).
0x1 : LSB_ALIGNED
Shifting with respect to bit 0 of receive shift register (LSB aligned).
End of enumeration elements list.
RXEXT : Receive Data Extension
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : OFF
Sign extension turned off.
0x1 : ON
Sign extension turned on.
End of enumeration elements list.
SSI Transmit Clock Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PM7_PM0 : Prescaler Modulus Select
bits : 0 - 7 (8 bit)
access : read-write
DC4_DC0 : Frame Rate Divider Control
bits : 8 - 12 (5 bit)
access : read-write
WL3_WL0 : Word Length Control
bits : 13 - 16 (4 bit)
access : read-write
PSR : Prescaler Range
bits : 17 - 17 (1 bit)
access : read-write
DIV2 : Divide By 2
bits : 18 - 18 (1 bit)
access : read-write
SSI Receive Clock Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PM7_PM0 : Prescaler Modulus Select
bits : 0 - 7 (8 bit)
access : read-write
DC4_DC0 : Frame Rate Divider Control
bits : 8 - 12 (5 bit)
access : read-write
WL3_WL0 : Word Length Control
bits : 13 - 16 (4 bit)
access : read-write
PSR : Prescaler Range
bits : 17 - 17 (1 bit)
access : read-write
DIV2 : Divide By 2
bits : 18 - 18 (1 bit)
access : read-write
SSI FIFO Control/Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFWM0 : Transmit FIFO Empty WaterMark 0
bits : 0 - 3 (4 bit)
access : read-write
RFWM0 : Receive FIFO Full WaterMark 0
bits : 4 - 7 (4 bit)
access : read-write
TFCNT0 : Transmit FIFO Counter 0
bits : 8 - 11 (4 bit)
access : read-write
RFCNT0 : Receive FIFO Counter 0
bits : 12 - 15 (4 bit)
access : read-write
TFWM1 : Transmit FIFO Empty WaterMark 1
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x1 : TFWM1_1
TFE set when there are more than or equal to 1 empty slots in Transmit FIFO (default). Transmit FIFO empty is set when TxFIFO <= 14 data.
0x2 : TFWM1_2
TFE set when there are more than or equal to 2 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=13 data.
0x3 : TFWM1_3
TFE set when there are more than or equal to 3 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=12 data.
0x4 : TFWM1_4
TFE set when there are more than or equal to 4 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=11 data.
0x5 : TFWM1_5
TFE set when there are more than or equal to 5 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=10 data.
0x6 : TFWM1_6
TFE set when there are more than or equal to 6 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=9 data.
0x7 : TFWM1_7
TFE set when there are more than or equal to 7 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=8 data.
0x8 : TFWM1_8
TFE set when there are more than or equal to 8 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=7 data.
0x9 : TFWM1_9
TFE set when there are more than or equal to 9 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 6 data.
0xA : TFWM1_10
TFE set when there are more than or equal to 10 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 5 data.
0xB : TFWM1_11
TFE set when there are more than or equal to 11 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 4 data.
0xC : TFWM1_12
TFE set when there are more than or equal to 12 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 3 data.
0xD : TFWM1_13
TFE set when there are more than or equal to 13 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 2 data.
0xE : TFWM1_14
TFE set when there are more than or equal to 14 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 1 data.
0xF : TFWM1_15
TFE set when there are 15 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO = 0 data.
End of enumeration elements list.
RFWM1 : Receive FIFO Full WaterMark 1
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0x1 : RFWM1_1
RFF set when at least one data word has been written to the Receive FIFO. Set when RxFIFO = 1,2.....15 data words
0x2 : RFWM1_2
RFF set when 2 or more data words have been written to the Receive FIFO. Set when RxFIFO = 2,3.....15 data words
0x3 : RFWM1_3
RFF set when 3 or more data words have been written to the Receive FIFO. Set when RxFIFO = 3,4.....15 data words
0x4 : RFWM1_4
RFF set when 4 or more data words have been written to the Receive FIFO. Set when RxFIFO = 4,5.....15 data words
0x5 : RFWM1_5
RFF set when 5 or more data words have been written to the Receive FIFO. Set when RxFIFO = 5,6.....15 data words
0x6 : RFWM1_6
RFF set when 6 or more data words have been written to the Receive.. Set when RxFIFO = 6,7......15 data words
0x7 : RFWM1_7
RFF set when 7 or more data words have been written to the Receive FIFO. Set when RxFIFO = 7,8......15 data words
0x8 : RFWM1_8
RFF set when 8 or more data words have been written to the Receive FIFO. Set when RxFIFO =8,9..... 15 data words
0x9 : RFWM1_9
RFF set when 9 or more data words have been written to the Receive FIFO. Set when RxFIFO = 9,10.....15 data words
0xA : RFWM1_10
RFF set when 10 or more data words have been written to the Receive FIFO. Set when RxFIFO = 10,11.....15 data words
0xB : RFWM1_11
RFF set when 11 or more data words have been written to the Receive FIFO. Set when RxFIFO = 11,12.....15 data words
0xC : RFWM1_12
RFF set when 12 or more data words have been written to the Receive FIFO. Set when RxFIFO = 12,13.....15 data words
0xD : RFWM1_13
RFF set when 13 or more data words have been written to the Receive FIFO. Set when RxFIFO = 13,14,15data words
0xE : RFWM1_14
RFF set when 14 or more data words have been written to the Receive FIFO. Set when RxFIFO = 14,15 data words
0xF : RFWM1_15
RFF set when 15 data words have been written to the Receive FIFO (default). Set when RxFIFO = 15 data words
End of enumeration elements list.
TFCNT1 : Transmit FIFO Counter1. These bits indicate the number of data words in Transmit FIFO.
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TFCNT1_0
0 data word in transmit FIFO
0x1 : TFCNT1_1
1 data word in transmit FIFO
0x2 : TFCNT1_2
2 data word in transmit FIFO
0x3 : TFCNT1_3
3 data word in transmit FIFO
0x4 : TFCNT1_4
4 data word in transmit FIFO
0x5 : TFCNT1_5
5 data word in transmit FIFO
0x6 : TFCNT1_6
6 data word in transmit FIFO
0x7 : TFCNT1_7
7 data word in transmit FIFO
0x8 : TFCNT1_8
8 data word in transmit FIFO
0x9 : TFCNT1_9
9 data word in transmit FIFO
0xA : TFCNT1_10
10 data word in transmit FIFO
0xB : TFCNT1_11
11 data word in transmit FIFO
0xC : TFCNT1_12
12 data word in transmit FIFO
0xD : TFCNT1_13
13 data word in transmit FIFO
0xE : TFCNT1_14
14 data word in transmit FIFO
0xF : TFCNT1_15
15 data word in transmit FIFO
End of enumeration elements list.
RFCNT1 : Receive FIFO Counter1. These bits indicate the number of data words in Receive FIFO 1.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : RFCNT1_0
0 data word in receive FIFO
0x1 : RFCNT1_1
1 data word in receive FIFO
0x2 : RFCNT1_2
2 data word in receive FIFO
0x3 : RFCNT1_3
3 data word in receive FIFO
0x4 : RFCNT1_4
4 data word in receive FIFO
0x5 : RFCNT1_5
5 data word in receive FIFO
0x6 : RFCNT1_6
6 data word in receive FIFO
0x7 : RFCNT1_7
7 data word in receive FIFO
0x8 : RFCNT1_8
8 data word in receive FIFO
0x9 : RFCNT1_9
9 data word in receive FIFO
0xA : RFCNT1_10
10 data word in receive FIFO
0xB : RFCNT1_11
11 data word in receive FIFO
0xC : RFCNT1_12
12 data word in receive FIFO
0xD : RFCNT1_13
13 data word in receive FIFO
0xE : RFCNT1_14
14 data word in receive FIFO
0xF : RFCNT1_15
15 data word in receive FIFO
End of enumeration elements list.
SSI AC97 Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AC97EN : AC97 Mode Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : AC97EN_0
AC97 mode disabled.
0x1 : AC97EN_1
SSI in AC97 mode.
End of enumeration elements list.
FV : Fixed/Variable Operation
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIXED
AC97 Fixed Mode.
0x1 : VARIABLE
AC97 Variable Mode.
End of enumeration elements list.
TIF : Tag in FIFO
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SATAG_REGISTER
Tag info stored in SATAG register.
0x1 : RX_FIFO0
Tag info stored in Rx FIFO 0.
End of enumeration elements list.
RD : Read Command
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RD_0
Next frame will not have a Read Command.
0x1 : RD_1
Next frame will have a Read Command.
End of enumeration elements list.
WR : Write Command
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : WR_0
Next frame will not have a Write Command.
0x1 : WR_1
Next frame will have a Write Command.
End of enumeration elements list.
FRDIV : Frame Rate Divider
bits : 5 - 10 (6 bit)
access : read-write
SSI AC97 Command Address Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SACADD : AC97 Command Address
bits : 0 - 18 (19 bit)
access : read-write
SSI Transmit Data Register n
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STXn : SSI Transmit Data
bits : 0 - 31 (32 bit)
access : read-write
SSI AC97 Command Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SACDAT : AC97 Command Data
bits : 0 - 19 (20 bit)
access : read-write
SSI AC97 Tag Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SATAG : AC97 Tag Value
bits : 0 - 15 (16 bit)
access : read-write
SSI Transmit Time Slot Mask Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STMSK : Transmit Mask
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : STMSK_0
Valid Time Slot.
0x1 : STMSK_1
Time Slot masked (no data transmitted in this time slot).
End of enumeration elements list.
SSI Receive Time Slot Mask Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRMSK : Receive Mask
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : SRMSK_0
Valid Time Slot.
0x1 : SRMSK_1
Time Slot masked (no data received in this time slot).
End of enumeration elements list.
SSI AC97 Channel Status Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SACCST : AC97 Channel Status
bits : 0 - 9 (10 bit)
access : read-only
Enumeration:
0 : SACCST_0
Data channel disabled.
0x1 : SACCST_1
Data channel enabled.
End of enumeration elements list.
SSI AC97 Channel Enable Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SACCEN : AC97 Channel Enable
bits : 0 - 9 (10 bit)
access : write-only
Enumeration:
0 : SACCEN_0
Write Has no effect.
0x1 : SACCEN_1
Write Enables the corresponding data channel.
End of enumeration elements list.
SSI AC97 Channel Disable Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SACCDIS : AC97 Channel Disable
bits : 0 - 9 (10 bit)
access : write-only
Enumeration:
0 : SACCDIS_0
Write Has no effect.
0x1 : SACCDIS_1
Write Disables the corresponding data channel.
End of enumeration elements list.
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