Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
PWM Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : PWM Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : EN_0
PWM disabled
0x1 : EN_1
PWM enabled
End of enumeration elements list.
REPEAT : Sample Repeat
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : REPEAT_0
Use each sample once
0x1 : REPEAT_1
Use each sample twice
0x2 : REPEAT_2
Use each sample four times
0x3 : REPEAT_3
Use each sample eight times
End of enumeration elements list.
SWR : Software Reset
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SWR_0
PWM is out of reset
0x1 : SWR_1
PWM is undergoing reset
End of enumeration elements list.
PRESCALER : Counter Clock Prescaler Value
bits : 4 - 15 (12 bit)
access : read-write
Enumeration:
0 : PRESCALER_0
Divide by 1
0x1 : PRESCALER_1
Divide by 2
0xFFF : PRESCALER_4095
Divide by 4096
End of enumeration elements list.
CLKSRC : Select Clock Source
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : CLKSRC_0
Clock is off
0x1 : CLKSRC_1
ipg_clk
0x2 : CLKSRC_2
ipg_clk_highfreq
0x3 : CLKSRC_3
ipg_clk_32k
End of enumeration elements list.
POUTC : PWM Output Configuration. This bit field determines the mode of PWM output on the output pin.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : POUTC_0
Output pin is set at rollover and cleared at comparison
0x1 : POUTC_1
Output pin is cleared at rollover and set at comparison
0x2 : POUTC_2
PWM output is disconnected
0x3 : POUTC_3
PWM output is disconnected
End of enumeration elements list.
HCTR : Half-word Data Swap Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : HCTR_0
Half word swapping does not take place
0x1 : HCTR_1
Half words from write data bus are swapped
End of enumeration elements list.
BCTR : Byte Data Swap Control
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : BCTR_0
byte ordering remains the same
0x1 : BCTR_1
byte ordering is reversed
End of enumeration elements list.
DBGEN : Debug Mode Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DBGEN_0
Inactive in debug mode
0x1 : DBGEN_1
Active in debug mode
End of enumeration elements list.
WAITEN : Wait Mode Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : WAITEN_0
Inactive in wait mode
0x1 : WAITEN_1
Active in wait mode
End of enumeration elements list.
DOZEN : Doze Mode Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DOZEN_0
Inactive in doze mode
0x1 : DOZEN_1
Active in doze mode
End of enumeration elements list.
STOPEN : Stop Mode Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : STOPEN_0
Inactive in stop mode
0x1 : STOPEN_1
Active in stop mode
End of enumeration elements list.
FWM : FIFO Water Mark
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : FWM_0
FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO
0x1 : FWM_1
FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO
0x2 : FWM_2
FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO
0x3 : FWM_3
FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO
End of enumeration elements list.
PWM Period Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period Value
bits : 0 - 15 (16 bit)
access : read-write
PWM Counter Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Counter Value
bits : 0 - 15 (16 bit)
access : read-only
PWM Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOAV : FIFO Available
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0 : FIFOAV_0
No data available
0x1 : FIFOAV_1
1 word of data in FIFO
0x2 : FIFOAV_2
2 words of data in FIFO
0x3 : FIFOAV_3
3 words of data in FIFO
0x4 : FIFOAV_4
4 words of data in FIFO
0x5 : FIFOAV_5
unused
0x6 : FIFOAV_6
unused
0x7 : FIFOAV_7
unused
End of enumeration elements list.
FE : FIFO Empty Status Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FE_0
Data level is above water mark
0x1 : FE_1
When the data level falls below the mark set by FWM field
End of enumeration elements list.
ROV : Roll-over Status. This bit shows that a roll-over event has occurred.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ROV_0
Roll-over event not occurred
0x1 : ROV_1
Roll-over event occurred
End of enumeration elements list.
CMP : Compare Status. This bit shows that a compare event has occurred.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : CMP_0
Compare event not occurred
0x1 : CMP_1
Compare event occurred
End of enumeration elements list.
FWE : FIFO Write Error Status
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : FWE_0
FIFO write error not occurred
0x1 : FWE_1
FIFO write error occurred
End of enumeration elements list.
PWM Interrupt Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIE : FIFO Empty Interrupt Enable. This bit controls the generation of the FIFO Empty interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FIE_0
FIFO Empty interrupt disabled
0x1 : FIE_1
FIFO Empty interrupt enabled
End of enumeration elements list.
RIE : Roll-over Interrupt Enable. This bit controls the generation of the Rollover interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RIE_0
Roll-over interrupt not enabled
0x1 : RIE_1
Roll-over Interrupt enabled
End of enumeration elements list.
CIE : Compare Interrupt Enable. This bit controls the generation of the Compare interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : CIE_0
Compare Interrupt not enabled
0x1 : CIE_1
Compare Interrupt enabled
End of enumeration elements list.
PWM Sample Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAMPLE : Sample Value
bits : 0 - 15 (16 bit)
access : read-write
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