Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xA byte (0x0)
mem_usage : registers
protection : not protected
Watchdog Control Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDZST : Watchdog Low Power
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : WDZST_0
Continue timer operation (Default).
0x1 : WDZST_1
Suspend the watchdog timer.
End of enumeration elements list.
WDBG : Watchdog DEBUG Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : WDBG_0
Continue WDOG timer operation (Default).
0x1 : WDBG_1
Suspend the watchdog timer.
End of enumeration elements list.
WDE : Watchdog Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WDE_0
Disable the Watchdog (Default).
0x1 : WDE_1
Enable the Watchdog.
End of enumeration elements list.
WDT : WDOG_B Time-out assertion
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : WDT_0
No effect on WDOG_B (Default).
0x1 : WDT_1
Assert WDOG_B upon a Watchdog Time-out event.
End of enumeration elements list.
SRS : Software Reset Signal
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SRS_0
Assert system reset signal.
0x1 : SRS_1
No effect on the system (Default).
End of enumeration elements list.
WDA : WDOG_B assertion. Controls the software assertion of the WDOG_B signal.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : WDA_0
Assert WDOG_B output.
0x1 : WDA_1
No effect on system (Default).
End of enumeration elements list.
SRE : software reset extension, an option way to generate software reset
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SRE_0
using original way to generate software reset (default)
0x1 : SRE_1
using new way to generate software reset.
End of enumeration elements list.
WDW : Watchdog Disable for Wait
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : WDW_0
Continue WDOG timer operation (Default).
0x1 : WDW_1
Suspend WDOG timer operation.
End of enumeration elements list.
WT : Watchdog Time-out Field
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
0 : WT_0
- 0.5 Seconds (Default).
0x1 : WT_1
- 1.0 Seconds.
0x2 : WT_2
- 1.5 Seconds.
0x3 : WT_3
- 2.0 Seconds.
0xFF : WT_255
- 128 Seconds.
End of enumeration elements list.
Watchdog Service Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WSR : Watchdog Service Register
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0x5555 : WSR_21845
Write to the Watchdog Service Register (WDOG_WSR).
0xAAAA : WSR_43690
Write to the Watchdog Service Register (WDOG_WSR).
End of enumeration elements list.
Watchdog Reset Status Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SFTW : Software Reset
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : SFTW_0
Reset is not the result of a software reset.
0x1 : SFTW_1
Reset is the result of a software reset.
End of enumeration elements list.
TOUT : Timeout. Indicates whether the reset is the result of a WDOG timeout.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : TOUT_0
Reset is not the result of a WDOG timeout.
0x1 : TOUT_1
Reset is the result of a WDOG timeout.
End of enumeration elements list.
POR : Power On Reset. Indicates whether the reset is the result of a power on reset.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : POR_0
Reset is not the result of a power on reset.
0x1 : POR_1
Reset is the result of a power on reset.
End of enumeration elements list.
Watchdog Interrupt Control Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WICT : Watchdog Interrupt Count Time-out (WICT) field determines, how long before the counter time-out must the interrupt occur
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : WICT_0
WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.
0x1 : WICT_1
WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
0x4 : WICT_4
WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
0xFF : WICT_255
WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
End of enumeration elements list.
WTIS : Watchdog TImer Interrupt Status bit will reflect the timer interrupt status, whether interrupt has occurred or not
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : WTIS_0
No interrupt has occurred (Default).
0x1 : WTIS_1
Interrupt has occurred
End of enumeration elements list.
WIE : Watchdog Timer Interrupt enable bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : WIE_0
Disable Interrupt (Default).
0x1 : WIE_1
Enable Interrupt.
End of enumeration elements list.
Watchdog Miscellaneous Control Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDE : Power Down Enable bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PDE_0
Power Down Counter of WDOG is disabled.
0x1 : PDE_1
Power Down Counter of WDOG is enabled (Default).
End of enumeration elements list.
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