\n

GPC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CNTR

IMR3

IMR4

ISR1

ISR2

ISR3

ISR4

PGR

IMR1

IMR2


CNTR

GPC Interface control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTR CNTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEGA_PDN_REQ MEGA_PUP_REQ DISPLAY_PDN_REQ DISPLAY_PUP_REQ VADC_ANALOG_OFF VADC_EXT_PWD_N GPCIRQM L2_PGE

MEGA_PDN_REQ : MEGA domain power down request
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : MEGA_PDN_REQ_0

No Request

0x1 : MEGA_PDN_REQ_1

Request power down sequence

End of enumeration elements list.

MEGA_PUP_REQ : MEGA domain power up request
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : MEGA_PUP_REQ_0

No Request

0x1 : MEGA_PUP_REQ_1

Request power up sequence

End of enumeration elements list.

DISPLAY_PDN_REQ : Display Power Down request
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISPLAY_PDN_REQ_0

no request

0x1 : DISPLAY_PDN_REQ_1

Request Power Down sequence to start for Display

End of enumeration elements list.

DISPLAY_PUP_REQ : Display Power Up request
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISPLAY_PUP_REQ_0

no request

0x1 : DISPLAY_PUP_REQ_1

Request Power Up sequence to start for Display

End of enumeration elements list.

VADC_ANALOG_OFF : Indication to VADC whether the analog power to VADC is available or not
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : VADC_ANALOG_OFF_0

VADC analog power is on

0x1 : VADC_ANALOG_OFF_1

VADC analog power is off

End of enumeration elements list.

VADC_EXT_PWD_N : VADC power down bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : VADC_EXT_PWD_N_0

VADC power down

0x1 : VADC_EXT_PWD_N_1

VADC not power down

End of enumeration elements list.

GPCIRQM : GPC interrupt/event masking
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : GPCIRQM_0

not masked

0x1 : GPCIRQM_1

interrupt/event is masked

End of enumeration elements list.

L2_PGE : L2 Cache Power Gate Enable
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : L2_PGE_0

L2 cache will keep power on even if CPU core is power down and will not be hardware invalidated when CPU core is re-power up the reset value is 1'b1

0x1 : L2_PGE_1

L2 cache power gate off request, L2 cache will be power down once when CPU core is power down and will be hardware invalidated automatically when CPU core is re-power up

End of enumeration elements list.


IMR3

IRQ masking register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR3 IMR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMR3

IMR3 : IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked
bits : 0 - 31 (32 bit)
access : read-write


IMR4

IRQ masking register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR4 IMR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMR4

IMR4 : IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked
bits : 0 - 31 (32 bit)
access : read-write


ISR1

IRQ status resister 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR1 ISR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISR1

ISR1 : IRQ[63:32] status, read only
bits : 0 - 31 (32 bit)
access : read-only


ISR2

IRQ status resister 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR2 ISR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISR2

ISR2 : IRQ[95:64] status, read only
bits : 0 - 31 (32 bit)
access : read-only


ISR3

IRQ status resister 3
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR3 ISR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISR3

ISR3 : IRQ[127:96] status, read only
bits : 0 - 31 (32 bit)
access : read-only


ISR4

IRQ status resister 4
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR4 ISR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISR4

ISR4 : IRQ[159:128] status, read only
bits : 0 - 31 (32 bit)
access : read-only


PGR

GPC Power Gating Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PGR PGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCIC

DRCIC : Debug ref cir in mux control
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0 : DRCIC_0

ccm_cosr_1_clk_in

0x1 : DRCIC_1

ccm_cosr_2_clk_in

0x2 : DRCIC_2

restricted

0x3 : DRCIC_3

restricted

End of enumeration elements list.


IMR1

IRQ masking register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR1 IMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMR1

IMR1 : IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked
bits : 0 - 31 (32 bit)
access : read-write


IMR2

IRQ masking register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR2 IMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMR2

IMR2 : IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked
bits : 0 - 31 (32 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.