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PGC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MEGA_CTRL

DISPLAY_CTRL

DISPLAY_PUPSCR

DISPLAY_PDNSCR

DISPLAY_SR

MEGA_PUPSCR

GPU_CTRL

GPU_PUPSCR

GPU_PDNSCR

GPU_SR

MEGA_PDNSCR

CPU_CTRL

CPU_PUPSCR

CPU_PDNSCR

CPU_SR

MEGA_SR


MEGA_CTRL

PGC Mega Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEGA_CTRL MEGA_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCR

PCR : Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PCR_0

Do not switch off power even if pdn_req is asserted.

0x1 : PCR_1

Switch off power when pdn_req is asserted.

End of enumeration elements list.


DISPLAY_CTRL

PGC Display Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISPLAY_CTRL DISPLAY_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCR

PCR : Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PCR_0

Do not switch off power even if pdn_req is asserted.

0x1 : PCR_1

Switch off power when pdn_req is asserted.

End of enumeration elements list.


DISPLAY_PUPSCR

PGC Display Power Up Sequence Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISPLAY_PUPSCR DISPLAY_PUPSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW SW2ISO

SW : After a power-up request (pup_req assertion), the PGC waits a number of IPG clocks equal to the value of SW before asserting power toggle on/off signal (switch_b)
bits : 0 - 5 (6 bit)
access : read-write

SW2ISO : After asserting power toggle on/off signal (switch_b), the PGC waits a number of IPG clocks equal to the value of SW2ISO before negating isolation
bits : 8 - 13 (6 bit)
access : read-write


DISPLAY_PDNSCR

PGC Display Pull Down Sequence Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISPLAY_PDNSCR DISPLAY_PDNSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISO ISO2SW

ISO : After a power-down request (pdn_req assertion), the PGC waits a number of IPG clocks equal to the value of ISO before asserting isolation
bits : 0 - 5 (6 bit)
access : read-write

ISO2SW : After asserting isolation, the PGC waits a number of IPG clocks equal to the value of ISO2SW before negating power toggle on/off signal (switch_b)
bits : 8 - 13 (6 bit)
access : read-write


DISPLAY_SR

GPU Display Power Gating Controller Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISPLAY_SR DISPLAY_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSR

PSR : Power status
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PSR_0

The target subsystem was not powered down for the previous power-down request.

0x1 : PSR_1

The target subsystem was powered down for the previous power-down request.

End of enumeration elements list.


MEGA_PUPSCR

PGC Mega Power Up Sequence Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEGA_PUPSCR MEGA_PUPSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW SW2ISO

SW : After a power-up request (pup_req assertion), the PGC waits a number of IPG clocks equal to the value of SW before asserting power toggle on/off signal (switch_b)
bits : 0 - 5 (6 bit)
access : read-write

SW2ISO : After asserting power toggle on/off signal (switch_b), the PGC waits a number of IPG clocks equal to the value of SW2ISO before negating isolation
bits : 8 - 13 (6 bit)
access : read-write


GPU_CTRL

PGC GPU PGC Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPU_CTRL GPU_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCR

PCR : Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PCR_0

Do not switch off power even if pdn_req is asserted.

0x1 : PCR_1

Switch off power when pdn_req is asserted.

End of enumeration elements list.


GPU_PUPSCR

PGC GPU Power Up Sequence Control Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPU_PUPSCR GPU_PUPSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW SW2ISO

SW : After a power-up request (pup_req assertion), the PGC waits a number of IPG clocks equal to the value of SW before asserting power toggle on/off signal (switch_b)
bits : 0 - 5 (6 bit)
access : read-write

SW2ISO : After asserting power toggle on/off signal (switch_b), the PGC waits a number of IPG clocks equal to the value of SW2ISO before negating isolation
bits : 8 - 13 (6 bit)
access : read-write


GPU_PDNSCR

PGC GPU Pull Down Sequence Control Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPU_PDNSCR GPU_PDNSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISO ISO2SW

ISO : After a power-down request (pdn_req assertion), the PGC waits a number of IPG clocks equal to the value of ISO before asserting isolation
bits : 0 - 5 (6 bit)
access : read-write

ISO2SW : After asserting isolation, the PGC waits a number of IPG clocks equal to the value of ISO2SW before negating power toggle on/off signal (switch_b)
bits : 8 - 13 (6 bit)
access : read-write


GPU_SR

PGC GPU Power Gating Controller Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPU_SR GPU_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSR

PSR : Power status
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PSR_0

The target subsystem was not powered down for the previous power-down request.

0x1 : PSR_1

The target subsystem was powered down for the previous power-down request.

End of enumeration elements list.


MEGA_PDNSCR

PGC Mega Pull Down Sequence Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEGA_PDNSCR MEGA_PDNSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISO ISO2SW

ISO : After a power-down request (pdn_req assertion), the PGC waits a number of IPG clocks equal to the value of ISO before asserting isolation
bits : 0 - 5 (6 bit)
access : read-write

ISO2SW : After asserting isolation, the PGC waits a number of IPG clocks equal to the value of ISO2SW before negating power toggle on/off signal (switch_b)
bits : 8 - 13 (6 bit)
access : read-write


CPU_CTRL

PGC CPU Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPU_CTRL CPU_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCR

PCR : Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PCR_0

Do not switch off power even if pdn_req is asserted.

0x1 : PCR_1

Switch off power when pdn_req is asserted.

End of enumeration elements list.


CPU_PUPSCR

PGC CPU Power Up Sequence Control Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPU_PUPSCR CPU_PUPSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW SW2ISO

SW : After a power-up request (pup_req assertion), the PGC waits a number of 32k clocks equal to the value of SW before asserting
bits : 0 - 5 (6 bit)
access : read-write

SW2ISO : After asserting , the PGC waits a number of 32k clocks equal to the value of SW2ISO before negating isolation
bits : 8 - 13 (6 bit)
access : read-write


CPU_PDNSCR

PGC CPU Pull Down Sequence Control Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPU_PDNSCR CPU_PDNSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISO ISO2SW

ISO : After a power-down request (pdn_req assertion), the PGC waits a number of 32k clocks equal to the value of ISO before asserting isolation
bits : 0 - 5 (6 bit)
access : read-write

ISO2SW : After asserting isolation, the PGC waits a number of 32k clocks equal to the value of ISO2SW before negating
bits : 8 - 13 (6 bit)
access : read-write


CPU_SR

PGC CPU Power Gating Controller Status Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPU_SR CPU_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSR

PSR : Power status
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PSR_0

The target subsystem was not powered down for the previous power-down request.

0x1 : PSR_1

The target subsystem was powered down for the previous power-down request.

End of enumeration elements list.


MEGA_SR

PGC Mega Power Gating Controller Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEGA_SR MEGA_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSR

PSR : Power status
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PSR_0

The target subsystem was not powered down for the previous power-down request.

0x1 : PSR_1

The target subsystem was powered down for the previous power-down request.

End of enumeration elements list.



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