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I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x16 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IADR

I2DR

DCA

IFDR

I2CR

I2SR


IADR

I2C Address Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IADR IADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADR

ADR : Slave address
bits : 1 - 7 (7 bit)
access : read-write


I2DR

I2C Data I/O Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2DR I2DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data Byte
bits : 0 - 7 (8 bit)
access : read-write


DCA

I2C Clock Duty-cycle Adjust Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCA DCA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCA

DCA : no description available
bits : 0 - 4 (5 bit)
access : read-write


IFDR

I2C Frequency Divider Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFDR IFDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC

IC : I2C clock rate
bits : 0 - 5 (6 bit)
access : read-write


I2CR

I2C Control Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CR I2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTA TXAK MTX MSTA IIEN IEN

RSTA : Repeat start
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

0 : RSTA_0

No repeat start

0x1 : RSTA_1

Generates a Repeated Start condition

End of enumeration elements list.

TXAK : Transmit acknowledge enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : TXAK_0

An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data.

0x1 : TXAK_1

No acknowledge signal response is sent (that is, the acknowledge bit = 1).

End of enumeration elements list.

MTX : Transmit/Receive mode select bit. Selects the direction of master and slave transfers.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : MTX_0

Receive.When a slave is addressed, the software should set MTX according to the slave read/write bit in the I2C status register (I2C_I2SR[SRW]).

0x1 : MTX_1

Transmit.In Master mode, MTX should be set according to the type of transfer required. Therefore, for address cycles, MTX is always 1.

End of enumeration elements list.

MSTA : Master/Slave mode select bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : MSTA_0

Slave mode. Changing MSTA from 1 to 0 generates a Stop and selects Slave mode.

0x1 : MSTA_1

Master mode. Changing MSTA from 0 to 1 signals a Start on the bus and selects Master mode.

End of enumeration elements list.

IIEN : I2C interrupt enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : IIEN_0

I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an Interrupt condition occurs.

0x1 : IIEN_1

I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set.

End of enumeration elements list.

IEN : I2C enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : IEN_0

The block is disabled, but registers can still be accessed.

0x1 : IEN_1

The I2C is enabled. This bit must be set before any other I2C_I2CR bits have an effect.

End of enumeration elements list.


I2SR

I2C Status Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2SR I2SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXAK IIF SRW IAL IBB IAAS ICF

RXAK : Received acknowledge
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : RXAK_0

An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus.

0x1 : RXAK_1

A "No acknowledge" signal was detected at the ninth clock.

End of enumeration elements list.

IIF : I2C interrupt
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : IIF_0

No I2C interrupt pending.

0x1 : IIF_1

An interrupt is pending.This causes a processor interrupt request (if the interrupt enable is asserted [IIEN = 1]). The interrupt is set when one of the following occurs: One byte transfer is completed (the interrupt is set at the falling edge of the ninth clock). An address is received that matches its own specific address in Slave Receive mode. Arbitration is lost.

End of enumeration elements list.

SRW : Slave read/write
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

0 : SRW_0

Slave receive, master writing to slave

0x1 : SRW_1

Slave transmit, master reading from slave

End of enumeration elements list.

IAL : Arbitration lost
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : IAL_0

No arbitration lost.

0x1 : IAL_1

Arbitration is lost.

End of enumeration elements list.

IBB : I2C bus busy bit
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

0 : IBB_0

Bus is idle. If a Stop signal is detected, IBB is cleared.

0x1 : IBB_1

Bus is busy. When Start is detected, IBB is set.

End of enumeration elements list.

IAAS : I2C addressed as a slave bit
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

0 : IAAS_0

Not addressed

0x1 : IAAS_1

Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address.

End of enumeration elements list.

ICF : Data transferring bit. While one byte of data is transferred, ICF is cleared.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

0 : ICF_0

Transfer is in progress.

0x1 : ICF_1

Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte transfer.

End of enumeration elements list.



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