Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
RNGB version ID register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINOR : Minor version number
bits : 0 - 7 (8 bit)
access : read-only
MAJOR : Major version number
bits : 8 - 15 (8 bit)
access : read-only
TYPE : Random number generator type
bits : 28 - 31 (4 bit)
access : read-only
Enumeration:
0 : TYPE_0
RNGA
0x1 : TYPE_1
RNGB (This is the type used in this module.)
0x2 : TYPE_2
RNGC
End of enumeration elements list.
RNGB error status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LFE : Linear feedback shift register (LFSR) error
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : LFE_0
The LFSRs are working properly.
0x1 : LFE_1
The LFSR failure occurred.
End of enumeration elements list.
OSCE : Oscillator error
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : OSCE_0
The RNG oscillator is working properly.
0x1 : OSCE_1
A problem with the RNG oscillator was detected.
End of enumeration elements list.
STE : Self-test error
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : STE_0
The RNGB did not fail the self test.
0x1 : STE_1
The RNGB failed the self test.
End of enumeration elements list.
SATE : Statistical test error
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : SATE_0
The RNGB did not fail the statistical tests.
0x1 : SATE_1
The RNGB failed the statistical tests during the initialization.
End of enumeration elements list.
FUFE : FIFO underflow error
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : FUFE_0
FIFO underflow did not occur.
0x1 : FUFE_1
FIFO underflow occurred.
End of enumeration elements list.
RNGB Output FIFO
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RANDOUT : Random output
bits : 0 - 31 (32 bit)
access : read-only
RNGB entropy register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ENT : Entropy input
bits : 0 - 31 (32 bit)
access : write-only
Verification control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SH_CLK_OFF : Shift the clocks off.
bits : 0 - 0 (1 bit)
access : read-write
FRC_SYS_CLK : Force system clock
bits : 1 - 1 (1 bit)
access : read-write
OSC_TEST : Oscillator frequency test
bits : 2 - 2 (1 bit)
access : read-write
FAKE_SEED : Fake seed
bits : 3 - 3 (1 bit)
access : read-write
RST_SHREG : Reset the shift registers.
bits : 8 - 8 (1 bit)
access : write-only
RST_XKEY : Reset the XKEY register.
bits : 9 - 9 (1 bit)
access : write-only
XKEY Data
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
XKEY : A 32-bit chunk of the 256-bit internal XKEY data structure
bits : 0 - 31 (32 bit)
access : read-only
Oscillator counter control register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCCR : Reading the number of clock cycles remaining and writing number of clock cycles during which to count the oscillator clock pulses
bits : 0 - 17 (18 bit)
access : read-write
Oscillator counter
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CLOCK_PULSES : CLOCK PULSES
bits : 0 - 19 (20 bit)
access : read-only
Oscillator counter status
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OS : Oscillator status
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : OS_0
The oscillator did not toggle 0x400 times.
0x1 : OS_1
The oscillator toggled 0x400 times.
End of enumeration elements list.
RNGB command register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ST : Self test
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ST_0
Not in the self-test mode
0x1 : ST_1
Self-test mode
End of enumeration elements list.
GS : Generate the seed.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : GS_0
Not in the seed generation mode
0x1 : GS_1
Generate the seed mode.
End of enumeration elements list.
CI : Clear the interrupt.
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
0 : CI_0
Do not clear the interrupt.
0x1 : CI_1
Clear the interrupt.
End of enumeration elements list.
CE : Clear the error.
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
0 : CE_0
Do not clear the errors and the interrupt.
0x1 : CE_1
Clear the errors and the interrupt.
End of enumeration elements list.
SR : Software reset
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
0 : SR_0
Do not perform a software reset.
0x1 : SR_1
Software reset
End of enumeration elements list.
RNGB control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUFMOD : FIFO underflow response mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : FUFMOD_0
Return all zeros and set the RNG_ESR[FUFE].
0x1 : FUFMOD_1
Return all zeros and set the RNG_ESR[FUFE].
0x2 : FUFMOD_2
Generate the bus transfer error
0x3 : FUFMOD_3
Generate the interrupt and return all zeros (overrides the RNG_CR[MASKERR]).
End of enumeration elements list.
AR : Auto-reseed
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : AR_0
Do not enable the automatic reseeding.
0x1 : AR_1
Enable the automatic reseeding.
End of enumeration elements list.
MASKDONE : Mask the interrupt done.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MASKDONE_0
No mask is applied.
0x1 : MASKDONE_1
The mask is applied.
End of enumeration elements list.
MASKERR : Mask the error interrupt.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : MASKERR_0
No mask is applied.
0x1 : MASKERR_1
The mask applied to the error interrupt
End of enumeration elements list.
RNGB status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : Busy.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : BUSY_0
Not busy
0x1 : BUSY_1
Busy
End of enumeration elements list.
SLP : Sleep
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : SLP_0
The RNGB is not in the sleep mode.
0x1 : SLP_1
The RNGB is in the sleep mode.
End of enumeration elements list.
RS : Reseed needed
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : RS_0
The RNGB does not need to be reseeded.
0x1 : RS_1
The RNGB needs to be reseeded.
End of enumeration elements list.
STDN : Self test done
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : STDN_0
Self test not completed
0x1 : STDN_1
Completed a self test since the last reset
End of enumeration elements list.
SDN : Seed done
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : SDN_0
The seed-generation process is not complete.
0x1 : SDN_1
Completed the seed generation since the last reset
End of enumeration elements list.
NSDN : New seed done
bits : 6 - 6 (1 bit)
access : read-only
FIFO_LVL : FIFO level
bits : 8 - 11 (4 bit)
access : read-only
FIFO_SIZE : FIFO size
bits : 12 - 15 (4 bit)
access : read-only
ERR : Error
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : ERR_0
No error
0x1 : ERR_1
Error detected
End of enumeration elements list.
ST_PF : Self-test pass fail
bits : 21 - 23 (3 bit)
access : read-only
Enumeration:
0 : ST_PF_0
Pass
0x1 : ST_PF_1
Fail
End of enumeration elements list.
STATPF : Statistics test pass failed.
bits : 24 - 31 (8 bit)
access : read-only
Enumeration:
0 : STATPF_0
Pass
0x1 : STATPF_1
Fail
End of enumeration elements list.
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