\n
address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
SW_MUX_CTL_PAD_TAMPER SW MUX Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_snvs_lp_wrapper_SNVS_TD1
Select mux mode: ALT0 mux port: SNVS_LP_WRAPPER_SNVS_TD1 of instance: snvs_lp_wrapper
0x5 : ALT5_gpio6_GPIO0
Select mux mode: ALT5 mux port: GPIO6_GPIO00 of instance: gpio6
End of enumeration elements list.
SW_MUX_CTL_PAD_BOOT_MODE1 SW MUX Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_src_BOOT_MODE1
Select mux mode: ALT0 mux port: SRC_BOOT_MODE01 of instance: src
0x5 : ALT5_gpio6_GPIO4
Select mux mode: ALT5 mux port: GPIO6_GPIO04 of instance: gpio6
End of enumeration elements list.
SW_PAD_CTL_PAD_TAMPER SW PAD Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRE : Slew Rate Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SRE_0_Slow_Slew_Rate
Slow Slew Rate
0x1 : SRE_1_Fast_Slew_Rate
Fast Slew Rate
End of enumeration elements list.
DSE : Drive Strength Field
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_output_driver_disabled_
output driver disabled;
0x1 : DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_
R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
0x2 : DSE_2_R0_2
R0/2
0x3 : DSE_3_R0_3
R0/3
0x4 : DSE_4_R0_4
R0/4
0x5 : DSE_5_R0_5
R0/5
0x6 : DSE_6_R0_6
R0/6
0x7 : DSE_7_R0_7
R0/7
End of enumeration elements list.
SPEED : speed Field
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : SPEED_0_low_50MHz_
low(50MHz)
0x1 : SPEED_1_medium_100MHz_
medium(100MHz)
0x2 : SPEED_2_medium_100MHz_
medium(100MHz)
0x3 : SPEED_3_max_200MHz_
max(200MHz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ODE_0_Open_Drain_Disabled
Open Drain Disabled
0x1 : ODE_1_Open_Drain_Enabled
Open Drain Enabled
End of enumeration elements list.
PKE : Pull / Keep Enable Field
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : PKE_0_Pull_Keeper_Disabled
Pull/Keeper Disabled
0x1 : PKE_1_Pull_Keeper_Enabled
Pull/Keeper Enabled
End of enumeration elements list.
PUE : Pull / Keep Select Field
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper
Keeper
0x1 : PUE_1_Pull
Pull
End of enumeration elements list.
PUS : Pull Up / Down Config. Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : PUS_0_100K_Ohm_Pull_Down
100K Ohm Pull Down
0x1 : PUS_1_47K_Ohm_Pull_Up
47K Ohm Pull Up
0x2 : PUS_2_100K_Ohm_Pull_Up
100K Ohm Pull Up
0x3 : PUS_3_22K_Ohm_Pull_Up
22K Ohm Pull Up
End of enumeration elements list.
HYS : Hyst. Enable Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_Hysteresis_Disabled
Hysteresis Disabled
0x1 : HYS_1_Hysteresis_Enabled
Hysteresis Enabled
End of enumeration elements list.
LVE : lve Field
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : LVE
High Voltage
End of enumeration elements list.
SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRE : Slew Rate Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SRE_0_Slow_Slew_Rate
Slow Slew Rate
0x1 : SRE_1_Fast_Slew_Rate
Fast Slew Rate
End of enumeration elements list.
DSE : Drive Strength Field
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_output_driver_disabled_
output driver disabled;
0x1 : DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_
R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
0x2 : DSE_2_R0_2
R0/2
0x3 : DSE_3_R0_3
R0/3
0x4 : DSE_4_R0_4
R0/4
0x5 : DSE_5_R0_5
R0/5
0x6 : DSE_6_R0_6
R0/6
0x7 : DSE_7_R0_7
R0/7
End of enumeration elements list.
SPEED : speed Field
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : SPEED_0_low_50MHz_
low(50MHz)
0x1 : SPEED_1_medium_100MHz_
medium(100MHz)
0x2 : SPEED_2_medium_100MHz_
medium(100MHz)
0x3 : SPEED_3_max_200MHz_
max(200MHz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ODE_0_Open_Drain_Disabled
Open Drain Disabled
0x1 : ODE_1_Open_Drain_Enabled
Open Drain Enabled
End of enumeration elements list.
PKE : Pull / Keep Enable Field
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : PKE_0_Pull_Keeper_Disabled
Pull/Keeper Disabled
0x1 : PKE_1_Pull_Keeper_Enabled
Pull/Keeper Enabled
End of enumeration elements list.
PUE : Pull / Keep Select Field
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper
Keeper
0x1 : PUE_1_Pull
Pull
End of enumeration elements list.
PUS : Pull Up / Down Config. Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : PUS_0_100K_Ohm_Pull_Down
100K Ohm Pull Down
0x1 : PUS_1_47K_Ohm_Pull_Up
47K Ohm Pull Up
0x2 : PUS_2_100K_Ohm_Pull_Up
100K Ohm Pull Up
0x3 : PUS_3_22K_Ohm_Pull_Up
22K Ohm Pull Up
End of enumeration elements list.
HYS : Hyst. Enable Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_Hysteresis_Disabled
Hysteresis Disabled
0x1 : HYS_1_Hysteresis_Enabled
Hysteresis Enabled
End of enumeration elements list.
LVE : lve Field
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : LVE
High Voltage
End of enumeration elements list.
SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRE : Slew Rate Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SRE_0_Slow_Slew_Rate
Slow Slew Rate
0x1 : SRE_1_Fast_Slew_Rate
Fast Slew Rate
End of enumeration elements list.
DSE : Drive Strength Field
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_output_driver_disabled_
output driver disabled;
0x1 : DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_
R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
0x2 : DSE_2_R0_2
R0/2
0x3 : DSE_3_R0_3
R0/3
0x4 : DSE_4_R0_4
R0/4
0x5 : DSE_5_R0_5
R0/5
0x6 : DSE_6_R0_6
R0/6
0x7 : DSE_7_R0_7
R0/7
End of enumeration elements list.
SPEED : speed Field
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : SPEED_0_low_50MHz_
low(50MHz)
0x1 : SPEED_1_medium_100MHz_
medium(100MHz)
0x2 : SPEED_2_medium_100MHz_
medium(100MHz)
0x3 : SPEED_3_max_200MHz_
max(200MHz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ODE_0_Open_Drain_Disabled
Open Drain Disabled
0x1 : ODE_1_Open_Drain_Enabled
Open Drain Enabled
End of enumeration elements list.
PKE : Pull / Keep Enable Field
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : PKE_0_Pull_Keeper_Disabled
Pull/Keeper Disabled
0x1 : PKE_1_Pull_Keeper_Enabled
Pull/Keeper Enabled
End of enumeration elements list.
PUE : Pull / Keep Select Field
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper
Keeper
0x1 : PUE_1_Pull
Pull
End of enumeration elements list.
PUS : Pull Up / Down Config. Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : PUS_0_100K_Ohm_Pull_Down
100K Ohm Pull Down
0x1 : PUS_1_47K_Ohm_Pull_Up
47K Ohm Pull Up
0x2 : PUS_2_100K_Ohm_Pull_Up
100K Ohm Pull Up
0x3 : PUS_3_22K_Ohm_Pull_Up
22K Ohm Pull Up
End of enumeration elements list.
HYS : Hyst. Enable Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_Hysteresis_Disabled
Hysteresis Disabled
0x1 : HYS_1_Hysteresis_Enabled
Hysteresis Enabled
End of enumeration elements list.
LVE : lve Field
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : LVE
High Voltage
End of enumeration elements list.
SW_PAD_CTL_PAD_BOOT_MODE0 SW PAD Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRE : Slew Rate Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SRE_0_Slow_Slew_Rate
Slow Slew Rate
0x1 : SRE_1_Fast_Slew_Rate
Fast Slew Rate
End of enumeration elements list.
DSE : Drive Strength Field
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_output_driver_disabled_
output driver disabled;
0x1 : DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_
R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
0x2 : DSE_2_R0_2
R0/2
0x3 : DSE_3_R0_3
R0/3
0x4 : DSE_4_R0_4
R0/4
0x5 : DSE_5_R0_5
R0/5
0x6 : DSE_6_R0_6
R0/6
0x7 : DSE_7_R0_7
R0/7
End of enumeration elements list.
SPEED : speed Field
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : SPEED_0_low_50MHz_
low(50MHz)
0x1 : SPEED_1_medium_100MHz_
medium(100MHz)
0x2 : SPEED_2_medium_100MHz_
medium(100MHz)
0x3 : SPEED_3_max_200MHz_
max(200MHz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ODE_0_Open_Drain_Disabled
Open Drain Disabled
0x1 : ODE_1_Open_Drain_Enabled
Open Drain Enabled
End of enumeration elements list.
PKE : Pull / Keep Enable Field
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : PKE_0_Pull_Keeper_Disabled
Pull/Keeper Disabled
0x1 : PKE_1_Pull_Keeper_Enabled
Pull/Keeper Enabled
End of enumeration elements list.
PUE : Pull / Keep Select Field
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper
Keeper
0x1 : PUE_1_Pull
Pull
End of enumeration elements list.
PUS : Pull Up / Down Config. Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : PUS_0_100K_Ohm_Pull_Down
100K Ohm Pull Down
0x1 : PUS_1_47K_Ohm_Pull_Up
47K Ohm Pull Up
0x2 : PUS_2_100K_Ohm_Pull_Up
100K Ohm Pull Up
0x3 : PUS_3_22K_Ohm_Pull_Up
22K Ohm Pull Up
End of enumeration elements list.
HYS : Hyst. Enable Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_Hysteresis_Disabled
Hysteresis Disabled
0x1 : HYS_1_Hysteresis_Enabled
Hysteresis Enabled
End of enumeration elements list.
LVE : lve Field
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : LVE
High Voltage
End of enumeration elements list.
SW_PAD_CTL_PAD_BOOT_MODE1 SW PAD Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRE : Slew Rate Field
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SRE_0_Slow_Slew_Rate
Slow Slew Rate
0x1 : SRE_1_Fast_Slew_Rate
Fast Slew Rate
End of enumeration elements list.
DSE : Drive Strength Field
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_output_driver_disabled_
output driver disabled;
0x1 : DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_
R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
0x2 : DSE_2_R0_2
R0/2
0x3 : DSE_3_R0_3
R0/3
0x4 : DSE_4_R0_4
R0/4
0x5 : DSE_5_R0_5
R0/5
0x6 : DSE_6_R0_6
R0/6
0x7 : DSE_7_R0_7
R0/7
End of enumeration elements list.
SPEED : speed Field
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : SPEED_0_low_50MHz_
low(50MHz)
0x1 : SPEED_1_medium_100MHz_
medium(100MHz)
0x2 : SPEED_2_medium_100MHz_
medium(100MHz)
0x3 : SPEED_3_max_200MHz_
max(200MHz)
End of enumeration elements list.
ODE : Open Drain Enable Field
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ODE_0_Open_Drain_Disabled
Open Drain Disabled
0x1 : ODE_1_Open_Drain_Enabled
Open Drain Enabled
End of enumeration elements list.
PKE : Pull / Keep Enable Field
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : PKE_0_Pull_Keeper_Disabled
Pull/Keeper Disabled
0x1 : PKE_1_Pull_Keeper_Enabled
Pull/Keeper Enabled
End of enumeration elements list.
PUE : Pull / Keep Select Field
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper
Keeper
0x1 : PUE_1_Pull
Pull
End of enumeration elements list.
PUS : Pull Up / Down Config. Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : PUS_0_100K_Ohm_Pull_Down
100K Ohm Pull Down
0x1 : PUS_1_47K_Ohm_Pull_Up
47K Ohm Pull Up
0x2 : PUS_2_100K_Ohm_Pull_Up
100K Ohm Pull Up
0x3 : PUS_3_22K_Ohm_Pull_Up
22K Ohm Pull Up
End of enumeration elements list.
HYS : Hyst. Enable Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_Hysteresis_Disabled
Hysteresis Disabled
0x1 : HYS_1_Hysteresis_Enabled
Hysteresis Enabled
End of enumeration elements list.
LVE : lve Field
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : LVE
High Voltage
End of enumeration elements list.
SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_snvs_lp_wrapper_SNVS_WAKEUP_ALARM
Select mux mode: ALT0 mux port: SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM of instance: snvs_lp_wrapper
0x5 : ALT5_gpio6_GPIO1
Select mux mode: ALT5 mux port: GPIO6_GPIO01 of instance: gpio6
End of enumeration elements list.
SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_ccm_PMIC_VSTBY_REQ
Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: ccm
0x5 : ALT5_gpio6_GPIO2
Select mux mode: ALT5 mux port: GPIO6_GPIO02 of instance: gpio6
End of enumeration elements list.
SW_MUX_CTL_PAD_BOOT_MODE0 SW MUX Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_MODE : MUX Mode Select Field.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ALT0_src_BOOT_MODE0
Select mux mode: ALT0 mux port: SRC_BOOT_MODE00 of instance: src
0x5 : ALT5_gpio6_GPIO3
Select mux mode: ALT5 mux port: GPIO6_GPIO03 of instance: gpio6
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.