\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
USB OTGn Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVER_CUR_DIS : Disable OTGn Overcurrent Detection
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : OVER_CUR_DIS_0
Enables overcurrent detection
0x1 : OVER_CUR_DIS_1
Disables overcurrent detection
End of enumeration elements list.
OVER_CUR_POL : OTGn Polarity of Overcurrent The polarity of OTGn port overcurrent event
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : OVER_CUR_POL_0
High active (high on this signal represents an overcurrent condition)
0x1 : OVER_CUR_POL_1
Low active (low on this signal represents an overcurrent condition)
End of enumeration elements list.
PWR_POL : OTGn Power Polarity This bit should be set according to PMIC Power Pin polarity.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : PWR_POL_0
PMIC Power Pin is Low active.
0x1 : PWR_POL_1
PMIC Power Pin is High active.
End of enumeration elements list.
WIE : OTGn Wake-up Interrupt Enable This bit enables or disables the OTGn wake-up interrupt
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : WIE_0
Interrupt Disabled
0x1 : WIE_1
Interrupt Enabled
End of enumeration elements list.
WKUP_SW_EN : OTGn Software Wake-up Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : WKUP_SW_EN_0
Disable
0x1 : WKUP_SW_EN_1
Enable
End of enumeration elements list.
WKUP_SW : OTGn Software Wake-up
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : WKUP_SW_0
Inactive
0x1 : WKUP_SW_1
Force wake-up
End of enumeration elements list.
WKUP_ID_EN : OTGn Wake-up on ID change enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : WKUP_ID_EN_0
Disable
0x1 : WKUP_ID_EN_1
Enable
End of enumeration elements list.
WKUP_VBUS_EN : OTGn wake-up on VBUS change enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : WKUP_VBUS_EN_0
Disable
0x1 : WKUP_VBUS_EN_1
Enable
End of enumeration elements list.
WIR : OTGn Wake-up Interrupt Request This bit indicates that a wake-up interrupt request is received on the OTGn port
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : WIR_0
No wake-up interrupt request received
0x1 : WIR_1
Wake-up Interrupt Request received
End of enumeration elements list.
OTGn UTMI PHY Control 0 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UTMI_CLK_VLD : Indicating whether OTGn UTMI PHY clock is valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UTMI_CLK_VLD_0
Invalid
0x1 : UTMI_CLK_VLD_1
Valid
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.