Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x94 byte (0x0)
mem_usage : registers
protection : not protected
Chip Select n General Configuration Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEN : CS Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CSEN_0
Chip select function is disabled; attempts to access an address mapped by this chip select results in an error respond and no assertion of the chip select output
0x1 : CSEN_1
Chip select is enabled, and is asserted when presented with a valid access.
End of enumeration elements list.
SWR : Synchronous Write Data
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SWR_0
write accesses are in Asynchronous mode
0x1 : SWR_1
write accesses are in Synchronous mode
End of enumeration elements list.
SRD : Synchronous Read Data
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRD_0
read accesses are in Asynchronous mode
0x1 : SRD_1
read accesses are in Synchronous mode
End of enumeration elements list.
MUM : Multiplexed Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : MUM_0
Multiplexed Mode disable
0x1 : MUM_1
Multiplexed Mode enable
End of enumeration elements list.
WFL : Write Fix Latency
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : WFL_0
the External device WAIT signal is being monitored, and it reflect the external data bus state
0x1 : WFL_1
the state of the External devices is determined internally (Fix latency mode only)
End of enumeration elements list.
RFL : Read Fix Latency
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : RFL_0
the External device WAIT signal is being monitored, and it reflect the external data bus state
0x1 : RFL_1
the state of the External devices is determined internally (Fix latency mode only)
End of enumeration elements list.
CRE : Configuration Register Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CRE_0
CRE signal use is disable
0x1 : CRE_1
CRE signal use is enable
End of enumeration elements list.
CREP : Configuration Register Enable Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : CREP_0
CRE signal is active low
0x1 : CREP_1
CRE signal is active high
End of enumeration elements list.
BL : Burst Length
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : BL_0
4 words Memory wrap burst length (read page burst size when APR = 1)
0x1 : BL_1
8 words Memory wrap burst length (read page burst size when APR = 1)
0x2 : BL_2
16 words Memory wrap burst length (read page burst size when APR = 1)
0x3 : BL_3
32 words Memory wrap burst length (read page burst size when APR = 1)
0x4 : BL_4
Continuous burst length (2 words read page burst size when APR = 1)
End of enumeration elements list.
WC : Write Continuous
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : WC_0
Write access burst length occurs according to BL value.
0x1 : WC_1
Write access burst length is continuous.
End of enumeration elements list.
BCD : Burst Clock Divisor
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : BCD_0
Divide EIM clock by 1
0x1 : BCD_1
Divide EIM clock by 2
0x2 : BCD_2
Divide EIM clock by 3
0x3 : BCD_3
Divide EIM clock by 4
End of enumeration elements list.
BCS : Burst Clock Start
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BCS_0
0 EIM clock cycle additional delay
0x1 : BCS_1
1 EIM clock cycle additional delay
0x2 : BCS_2
2 EIM clock cycle additional delay
0x3 : BCS_3
3 EIM clock cycle additional delay
End of enumeration elements list.
DSZ : Data Port Size
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x1 : DSZ_1
16 bit port resides on DATA[15:0]
0x2 : DSZ_2
16 bit port resides on DATA[31:16]
0x3 : DSZ_3
32 bit port resides on DATA[31:0]
0x4 : DSZ_4
8 bit port resides on DATA[7:0]
0x5 : DSZ_5
8 bit port resides on DATA[15:8]
0x6 : DSZ_6
8 bit port resides on DATA[23:16]
0x7 : DSZ_7
8 bit port resides on DATA[31:24]
End of enumeration elements list.
SP : Supervisor Protect
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SP_0
User mode accesses are allowed in the memory range defined by chip select.
0x1 : SP_1
User mode accesses are prohibited. All attempts to access an address mapped by this chip select in User mode results in an error response and no assertion of the chip select output.
End of enumeration elements list.
CSREC : CS Recovery
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : CSREC_0
0 EIM clock cycles minimum width of CS, OE and WE signals (read async. mode only)
0x1 : CSREC_1
1 EIM clock cycles minimum width of CS, OE and WE signals
0x2 : CSREC_2
2 EIM clock cycles minimum width of CS, OE and WE signals
0x7 : CSREC_7
7 EIM clock cycles minimum width of CS, OE and WE signals
End of enumeration elements list.
AUS : Address UnShifted
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : AUS_0
Address shifted according to port size (DSZ config) (128 Mbyte maximum supported memory density).
0x1 : AUS_1
Address unshifted (32 Mbyte maximum supported memory density).
End of enumeration elements list.
GBC : Gap Between Chip Selects
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : GBC_0
minimum of 0 EIM clock cycles before next access from different chip select (async. mode only)
0x1 : GBC_1
minimum of 1 EIM clock cycles before next access from different chip select
0x2 : GBC_2
minimum of 2 EIM clock cycles before next access from different chip select
0x7 : GBC_7
minimum of 7 EIM clock cycles before next access from different chip select
End of enumeration elements list.
WP : Write Protect
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : WP_0
Writes are allowed in the memory range defined by chip.
0x1 : WP_1
Writes are prohibited. All attempts to write to an address mapped by this chip select result in a error response and no assertion of the chip select output.
End of enumeration elements list.
PSZ : Page Size
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : PSZ_0
8 words page size
0x1 : PSZ_1
16 words page size
0x2 : PSZ_2
32 words page size
0x3 : PSZ_3
64 words page size
0x4 : PSZ_4
128 words page size
0x5 : PSZ_5
256 words page size
0x6 : PSZ_6
512 words page size
0x7 : PSZ_7
1024 (1k) words page size
0x8 : PSZ_8
2048 (2k) words page size
0x9 : PSZ_9
- 1111 Reserved
End of enumeration elements list.
Chip Select n Read Configuration Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCSN : Read CS Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : RCSN_0
0 EIM clock cycles between end of read access and CS negation
0x1 : RCSN_1
1 EIM clock cycles between end of read access and CS negation
0x2 : RCSN_2
2 EIM clock cycles between end of read access and CS negation
0x7 : RCSN_7
7 EIM clock cycles between end of read access and CS negation
End of enumeration elements list.
RCSA : Read CS Assertion
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : RCSA_0
0 EIM clock cycles between beginning of read access and CS assertion
0x1 : RCSA_1
1 EIM clock cycles between beginning of read access and CS assertion
0x2 : RCSA_2
2 EIM clock cycles between beginning of read access and CS assertion
0x7 : RCSA_7
7 EIM clock cycles between beginning of read access and CS assertion
End of enumeration elements list.
OEN : OE Negation
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : OEN_0
0 EIM clock cycles between end of access and OE negation
0x1 : OEN_1
1 EIM clock cycles between end of access and OE negation
0x2 : OEN_2
2 EIM clock cycles between end of access and OE negation
0x7 : OEN_7
7 EIM clock cycles between end of access and OE negation
End of enumeration elements list.
OEA : OE Assertion
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : OEA_0
0 EIM clock cycles between beginning of access and OE assertion
0x1 : OEA_1
1 EIM clock cycles between beginning of access and OE assertion
0x2 : OEA_2
2 EIM clock cycles between beginning of access and OE assertion
0x7 : OEA_7
7 EIM clock cycles between beginning of access and OE assertion
End of enumeration elements list.
RADVN : ADV Negation
bits : 16 - 18 (3 bit)
access : read-write
RAL : Read ADV Low
bits : 19 - 19 (1 bit)
access : read-write
RADVA : ADV Assertion
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : RADVA_0
0 EIM clock cycles between beginning of access and ADV assertion
0x1 : RADVA_1
1 EIM clock cycles between beginning of access and ADV assertion
0x2 : RADVA_2
2 EIM clock cycles between beginning of access and ADV assertion
0x7 : RADVA_7
7 EIM clock cycles between beginning of access and ADV assertion
End of enumeration elements list.
RWSC : Read Wait State Control
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x1 : RWSC_1
RWSC value is 1
0x2 : RWSC_2
RWSC value is 2
0x3D : RWSC_61
RWSC value is 61
0x3E : RWSC_62
RWSC value is 62
0x3F : RWSC_63
RWSC value is 63
End of enumeration elements list.
Chip Select n General Configuration Register 2
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADH : Address hold time - This bit field determine the address hold time after ADV negation when mum = 1 (muxed mode)
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ADH_0
0 cycle after ADV negation
0x1 : ADH_1
1 cycle after ADV negation
0x2 : ADH_2
2 cycle after ADV negation
End of enumeration elements list.
DAPS : Data Acknowledge Poling Start
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : DAPS_0
3 EIM clk cycle between start of access and first DTACK check
0x1 : DAPS_1
4 EIM clk cycles between start of access and first DTACK check
0x2 : DAPS_2
5 EIM clk cycles between start of access and first DTACK check
0x7 : DAPS_7
10 EIM clk cycles between start of access and first DTACK check
0xB : DAPS_11
14 EIM clk cycles between start of access and first DTACK check
0xF : DAPS_15
18 EIM clk cycles between start of access and first DTACK check
End of enumeration elements list.
DAE : Data Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DAE_0
DTACK signal use is disable
0x1 : DAE_1
DTACK signal use is enable
End of enumeration elements list.
DAP : Data Acknowledge Polarity
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DAP_0
DTACK signal is active high
0x1 : DAP_1
DTACK signal is active low
End of enumeration elements list.
MUX16_BYP_GRANT : Muxed 16 bypass grant
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : MUX16_BYP_GRANT_0
EIM waits for grant before driving a 16 bit muxed mode access to the memory.
0x1 : MUX16_BYP_GRANT_1
EIM ignores the grant signal and immediately drives a 16 bit muxed mode access to the memory.
End of enumeration elements list.
Chip Select n Read Configuration Register 1
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCSN : Read CS Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : RCSN_0
0 EIM clock cycles between end of read access and CS negation
0x1 : RCSN_1
1 EIM clock cycles between end of read access and CS negation
0x2 : RCSN_2
2 EIM clock cycles between end of read access and CS negation
0x7 : RCSN_7
7 EIM clock cycles between end of read access and CS negation
End of enumeration elements list.
RCSA : Read CS Assertion
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : RCSA_0
0 EIM clock cycles between beginning of read access and CS assertion
0x1 : RCSA_1
1 EIM clock cycles between beginning of read access and CS assertion
0x2 : RCSA_2
2 EIM clock cycles between beginning of read access and CS assertion
0x7 : RCSA_7
7 EIM clock cycles between beginning of read access and CS assertion
End of enumeration elements list.
OEN : OE Negation
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : OEN_0
0 EIM clock cycles between end of access and OE negation
0x1 : OEN_1
1 EIM clock cycles between end of access and OE negation
0x2 : OEN_2
2 EIM clock cycles between end of access and OE negation
0x7 : OEN_7
7 EIM clock cycles between end of access and OE negation
End of enumeration elements list.
OEA : OE Assertion
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : OEA_0
0 EIM clock cycles between beginning of access and OE assertion
0x1 : OEA_1
1 EIM clock cycles between beginning of access and OE assertion
0x2 : OEA_2
2 EIM clock cycles between beginning of access and OE assertion
0x7 : OEA_7
7 EIM clock cycles between beginning of access and OE assertion
End of enumeration elements list.
RADVN : ADV Negation
bits : 16 - 18 (3 bit)
access : read-write
RAL : Read ADV Low
bits : 19 - 19 (1 bit)
access : read-write
RADVA : ADV Assertion
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : RADVA_0
0 EIM clock cycles between beginning of access and ADV assertion
0x1 : RADVA_1
1 EIM clock cycles between beginning of access and ADV assertion
0x2 : RADVA_2
2 EIM clock cycles between beginning of access and ADV assertion
0x7 : RADVA_7
7 EIM clock cycles between beginning of access and ADV assertion
End of enumeration elements list.
RWSC : Read Wait State Control
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x1 : RWSC_1
RWSC value is 1
0x2 : RWSC_2
RWSC value is 2
0x3D : RWSC_61
RWSC value is 61
0x3E : RWSC_62
RWSC value is 62
0x3F : RWSC_63
RWSC value is 63
End of enumeration elements list.
Chip Select n Read Configuration Register 2
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBEN : Read BE Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : RBEN_0
0 EIM clock cycles between end of read access and BE negation
0x1 : RBEN_1
1 EIM clock cycles between end of read access and BE negation
0x2 : RBEN_2
2 EIM clock cycles between end of read access and BE negation
0x7 : RBEN_7
7 EIM clock cycles between end of read access and BE negation
End of enumeration elements list.
RBE : Read BE enable. This bit field determines if BE will be asserted during read access.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RBE_0
- BE are disabled during read access.
End of enumeration elements list.
RBEA : Read BE Assertion
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : RBEA_0
0 EIM clock cycles between beginning of read access and BE assertion
0x1 : RBEA_1
1 EIM clock cycles between beginning of read access and BE assertion
0x2 : RBEA_2
2 EIM clock cycles between beginning of read access and BE assertion
0x7 : RBEA_7
7 EIM clock cycles between beginning of read access and BE assertion
End of enumeration elements list.
RL : Read Latency
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : RL_0
Feedback clock loop delay is up to 1 cycle for BCD = 0 or 1.5 cycles for BCD != 0
0x1 : RL_1
Feedback clock loop delay is up to 2 cycles for BCD = 0 or 2.5 cycles for BCD != 0
0x2 : RL_2
Feedback clock loop delay is up to 3 cycles for BCD = 0 or 3.5 cycles for BCD != 0
0x3 : RL_3
Feedback clock loop delay is up to 4 cycles for BCD = 0 or 4.5 cycles for BCD != 0
End of enumeration elements list.
PAT : Page Access Time
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : PAT_0
Address width is 2 EIM clock cycles
0x1 : PAT_1
Address width is 3 EIM clock cycles
0x2 : PAT_2
Address width is 4 EIM clock cycles
0x3 : PAT_3
Address width is 5 EIM clock cycles
0x4 : PAT_4
Address width is 6 EIM clock cycles
0x5 : PAT_5
Address width is 7 EIM clock cycles
0x6 : PAT_6
Address width is 8 EIM clock cycles
0x7 : PAT_7
Address width is 9 EIM clock cycles
End of enumeration elements list.
APR : Asynchronous Page Read
bits : 15 - 15 (1 bit)
access : read-write
Chip Select n Write Configuration Register 1
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WCSN : Write CS Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : WCSN_0
0 EIM clock cycles between end of read access and CS negation
0x1 : WCSN_1
1 EIM clock cycles between end of read access and CS negation
0x2 : WCSN_2
2 EIM clock cycles between end of read access and CS negation
0x7 : WCSN_7
7 EIM clock cycles between end of read access and CS negation
End of enumeration elements list.
WCSA : Write CS Assertion
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : WCSA_0
0 EIM clock cycles between beginning of write access and CS assertion
0x1 : WCSA_1
1 EIM clock cycles between beginning of write access and CS assertion
0x2 : WCSA_2
2 EIM clock cycles between beginning of write access and CS assertion
0x7 : WCSA_7
7 EIMclock cycles between beginning of write access and CS assertion
End of enumeration elements list.
WEN : WE Negation
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : WEN_0
0 EIM clock cycles between beginning of access and WE assertion
0x1 : WEN_1
1 EIM clock cycles between beginning of access and WE assertion
0x2 : WEN_2
2 EIM clock cycles between beginning of access and WE assertion
0x7 : WEN_7
7 EIM clock cycles between beginning of access and WE assertion
End of enumeration elements list.
WEA : WE Assertion
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : WEA_0
0 EIM clock cycles between beginning of access and WE assertion
0x1 : WEA_1
1 EIM clock cycles between beginning of access and WE assertion
0x2 : WEA_2
2 EIM clock cycles between beginning of access and WE assertion
0x7 : WEA_7
7 EIMclock cycles between beginning of access and WE assertion
End of enumeration elements list.
WBEN : BE[3:0] Negation
bits : 12 - 14 (3 bit)
access : read-write
WBEA : BE Assertion
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0 : WBEA_0
0 EIM clock cycles between beginning of access and BE assertion
0x1 : WBEA_1
1 EIM clock cycles between beginning of access and BE assertion
0x2 : WBEA_2
2 EIM clock cycles between beginning of access and BE assertion
0x7 : WBEA_7
7 EIM clock cycles between beginning of access and BE assertion
End of enumeration elements list.
WADVN : ADV Negation
bits : 18 - 20 (3 bit)
access : read-write
WADVA : ADV Assertion
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0 : WADVA_0
0 EIM clock cycles between beginning of access and ADV assertion
0x1 : WADVA_1
1 EIM clock cycles between beginning of access and ADV assertion
0x2 : WADVA_2
2 EIM clock cycles between beginning of access and ADV assertion
0x7 : WADVA_7
7 EIM clock cycles between beginning of access and ADV assertion
End of enumeration elements list.
WWSC : Write Wait State Control
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x1 : WWSC_1
WWSC value is 1
0x2 : WWSC_2
WWSC value is 2
0x3 : WWSC_3
WWSC value is 3
0x3F : WWSC_63
WWSC value is 63
End of enumeration elements list.
WBED : Write Byte Enable Disable
bits : 30 - 30 (1 bit)
access : read-write
WAL : Write ADV Low
bits : 31 - 31 (1 bit)
access : read-write
Chip Select n General Configuration Register 1
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEN : CS Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CSEN_0
Chip select function is disabled; attempts to access an address mapped by this chip select results in an error respond and no assertion of the chip select output
0x1 : CSEN_1
Chip select is enabled, and is asserted when presented with a valid access.
End of enumeration elements list.
SWR : Synchronous Write Data
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SWR_0
write accesses are in Asynchronous mode
0x1 : SWR_1
write accesses are in Synchronous mode
End of enumeration elements list.
SRD : Synchronous Read Data
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRD_0
read accesses are in Asynchronous mode
0x1 : SRD_1
read accesses are in Synchronous mode
End of enumeration elements list.
MUM : Multiplexed Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : MUM_0
Multiplexed Mode disable
0x1 : MUM_1
Multiplexed Mode enable
End of enumeration elements list.
WFL : Write Fix Latency
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : WFL_0
the External device WAIT signal is being monitored, and it reflect the external data bus state
0x1 : WFL_1
the state of the External devices is determined internally (Fix latency mode only)
End of enumeration elements list.
RFL : Read Fix Latency
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : RFL_0
the External device WAIT signal is being monitored, and it reflect the external data bus state
0x1 : RFL_1
the state of the External devices is determined internally (Fix latency mode only)
End of enumeration elements list.
CRE : Configuration Register Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CRE_0
CRE signal use is disable
0x1 : CRE_1
CRE signal use is enable
End of enumeration elements list.
CREP : Configuration Register Enable Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : CREP_0
CRE signal is active low
0x1 : CREP_1
CRE signal is active high
End of enumeration elements list.
BL : Burst Length
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : BL_0
4 words Memory wrap burst length (read page burst size when APR = 1)
0x1 : BL_1
8 words Memory wrap burst length (read page burst size when APR = 1)
0x2 : BL_2
16 words Memory wrap burst length (read page burst size when APR = 1)
0x3 : BL_3
32 words Memory wrap burst length (read page burst size when APR = 1)
0x4 : BL_4
Continuous burst length (2 words read page burst size when APR = 1)
End of enumeration elements list.
WC : Write Continuous
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : WC_0
Write access burst length occurs according to BL value.
0x1 : WC_1
Write access burst length is continuous.
End of enumeration elements list.
BCD : Burst Clock Divisor
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : BCD_0
Divide EIM clock by 1
0x1 : BCD_1
Divide EIM clock by 2
0x2 : BCD_2
Divide EIM clock by 3
0x3 : BCD_3
Divide EIM clock by 4
End of enumeration elements list.
BCS : Burst Clock Start
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BCS_0
0 EIM clock cycle additional delay
0x1 : BCS_1
1 EIM clock cycle additional delay
0x2 : BCS_2
2 EIM clock cycle additional delay
0x3 : BCS_3
3 EIM clock cycle additional delay
End of enumeration elements list.
DSZ : Data Port Size
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x1 : DSZ_1
16 bit port resides on DATA[15:0]
0x2 : DSZ_2
16 bit port resides on DATA[31:16]
0x3 : DSZ_3
32 bit port resides on DATA[31:0]
0x4 : DSZ_4
8 bit port resides on DATA[7:0]
0x5 : DSZ_5
8 bit port resides on DATA[15:8]
0x6 : DSZ_6
8 bit port resides on DATA[23:16]
0x7 : DSZ_7
8 bit port resides on DATA[31:24]
End of enumeration elements list.
SP : Supervisor Protect
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SP_0
User mode accesses are allowed in the memory range defined by chip select.
0x1 : SP_1
User mode accesses are prohibited. All attempts to access an address mapped by this chip select in User mode results in an error response and no assertion of the chip select output.
End of enumeration elements list.
CSREC : CS Recovery
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : CSREC_0
0 EIM clock cycles minimum width of CS, OE and WE signals (read async. mode only)
0x1 : CSREC_1
1 EIM clock cycles minimum width of CS, OE and WE signals
0x2 : CSREC_2
2 EIM clock cycles minimum width of CS, OE and WE signals
0x7 : CSREC_7
7 EIM clock cycles minimum width of CS, OE and WE signals
End of enumeration elements list.
AUS : Address UnShifted
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : AUS_0
Address shifted according to port size (DSZ config) (128 Mbyte maximum supported memory density).
0x1 : AUS_1
Address unshifted (32 Mbyte maximum supported memory density).
End of enumeration elements list.
GBC : Gap Between Chip Selects
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : GBC_0
minimum of 0 EIM clock cycles before next access from different chip select (async. mode only)
0x1 : GBC_1
minimum of 1 EIM clock cycles before next access from different chip select
0x2 : GBC_2
minimum of 2 EIM clock cycles before next access from different chip select
0x7 : GBC_7
minimum of 7 EIM clock cycles before next access from different chip select
End of enumeration elements list.
WP : Write Protect
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : WP_0
Writes are allowed in the memory range defined by chip.
0x1 : WP_1
Writes are prohibited. All attempts to write to an address mapped by this chip select result in a error response and no assertion of the chip select output.
End of enumeration elements list.
PSZ : Page Size
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : PSZ_0
8 words page size
0x1 : PSZ_1
16 words page size
0x2 : PSZ_2
32 words page size
0x3 : PSZ_3
64 words page size
0x4 : PSZ_4
128 words page size
0x5 : PSZ_5
256 words page size
0x6 : PSZ_6
512 words page size
0x7 : PSZ_7
1024 (1k) words page size
0x8 : PSZ_8
2048 (2k) words page size
0x9 : PSZ_9
- 1111 Reserved
End of enumeration elements list.
Chip Select n Write Configuration Register 2
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WBCDD : Write Burst Clock Divisor Decrement
bits : 0 - 0 (1 bit)
access : read-write
Chip Select n General Configuration Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEN : CS Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CSEN_0
Chip select function is disabled; attempts to access an address mapped by this chip select results in an error respond and no assertion of the chip select output
0x1 : CSEN_1
Chip select is enabled, and is asserted when presented with a valid access.
End of enumeration elements list.
SWR : Synchronous Write Data
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SWR_0
write accesses are in Asynchronous mode
0x1 : SWR_1
write accesses are in Synchronous mode
End of enumeration elements list.
SRD : Synchronous Read Data
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRD_0
read accesses are in Asynchronous mode
0x1 : SRD_1
read accesses are in Synchronous mode
End of enumeration elements list.
MUM : Multiplexed Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : MUM_0
Multiplexed Mode disable
0x1 : MUM_1
Multiplexed Mode enable
End of enumeration elements list.
WFL : Write Fix Latency
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : WFL_0
the External device WAIT signal is being monitored, and it reflect the external data bus state
0x1 : WFL_1
the state of the External devices is determined internally (Fix latency mode only)
End of enumeration elements list.
RFL : Read Fix Latency
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : RFL_0
the External device WAIT signal is being monitored, and it reflect the external data bus state
0x1 : RFL_1
the state of the External devices is determined internally (Fix latency mode only)
End of enumeration elements list.
CRE : Configuration Register Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CRE_0
CRE signal use is disable
0x1 : CRE_1
CRE signal use is enable
End of enumeration elements list.
CREP : Configuration Register Enable Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : CREP_0
CRE signal is active low
0x1 : CREP_1
CRE signal is active high
End of enumeration elements list.
BL : Burst Length
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : BL_0
4 words Memory wrap burst length (read page burst size when APR = 1)
0x1 : BL_1
8 words Memory wrap burst length (read page burst size when APR = 1)
0x2 : BL_2
16 words Memory wrap burst length (read page burst size when APR = 1)
0x3 : BL_3
32 words Memory wrap burst length (read page burst size when APR = 1)
0x4 : BL_4
Continuous burst length (2 words read page burst size when APR = 1)
End of enumeration elements list.
WC : Write Continuous
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : WC_0
Write access burst length occurs according to BL value.
0x1 : WC_1
Write access burst length is continuous.
End of enumeration elements list.
BCD : Burst Clock Divisor
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : BCD_0
Divide EIM clock by 1
0x1 : BCD_1
Divide EIM clock by 2
0x2 : BCD_2
Divide EIM clock by 3
0x3 : BCD_3
Divide EIM clock by 4
End of enumeration elements list.
BCS : Burst Clock Start
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BCS_0
0 EIM clock cycle additional delay
0x1 : BCS_1
1 EIM clock cycle additional delay
0x2 : BCS_2
2 EIM clock cycle additional delay
0x3 : BCS_3
3 EIM clock cycle additional delay
End of enumeration elements list.
DSZ : Data Port Size
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x1 : DSZ_1
16 bit port resides on DATA[15:0]
0x2 : DSZ_2
16 bit port resides on DATA[31:16]
0x3 : DSZ_3
32 bit port resides on DATA[31:0]
0x4 : DSZ_4
8 bit port resides on DATA[7:0]
0x5 : DSZ_5
8 bit port resides on DATA[15:8]
0x6 : DSZ_6
8 bit port resides on DATA[23:16]
0x7 : DSZ_7
8 bit port resides on DATA[31:24]
End of enumeration elements list.
SP : Supervisor Protect
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SP_0
User mode accesses are allowed in the memory range defined by chip select.
0x1 : SP_1
User mode accesses are prohibited. All attempts to access an address mapped by this chip select in User mode results in an error response and no assertion of the chip select output.
End of enumeration elements list.
CSREC : CS Recovery
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : CSREC_0
0 EIM clock cycles minimum width of CS, OE and WE signals (read async. mode only)
0x1 : CSREC_1
1 EIM clock cycles minimum width of CS, OE and WE signals
0x2 : CSREC_2
2 EIM clock cycles minimum width of CS, OE and WE signals
0x7 : CSREC_7
7 EIM clock cycles minimum width of CS, OE and WE signals
End of enumeration elements list.
AUS : Address UnShifted
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : AUS_0
Address shifted according to port size (DSZ config) (128 Mbyte maximum supported memory density).
0x1 : AUS_1
Address unshifted (32 Mbyte maximum supported memory density).
End of enumeration elements list.
GBC : Gap Between Chip Selects
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : GBC_0
minimum of 0 EIM clock cycles before next access from different chip select (async. mode only)
0x1 : GBC_1
minimum of 1 EIM clock cycles before next access from different chip select
0x2 : GBC_2
minimum of 2 EIM clock cycles before next access from different chip select
0x7 : GBC_7
minimum of 7 EIM clock cycles before next access from different chip select
End of enumeration elements list.
WP : Write Protect
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : WP_0
Writes are allowed in the memory range defined by chip.
0x1 : WP_1
Writes are prohibited. All attempts to write to an address mapped by this chip select result in a error response and no assertion of the chip select output.
End of enumeration elements list.
PSZ : Page Size
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : PSZ_0
8 words page size
0x1 : PSZ_1
16 words page size
0x2 : PSZ_2
32 words page size
0x3 : PSZ_3
64 words page size
0x4 : PSZ_4
128 words page size
0x5 : PSZ_5
256 words page size
0x6 : PSZ_6
512 words page size
0x7 : PSZ_7
1024 (1k) words page size
0x8 : PSZ_8
2048 (2k) words page size
0x9 : PSZ_9
- 1111 Reserved
End of enumeration elements list.
Chip Select n Read Configuration Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBEN : Read BE Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : RBEN_0
0 EIM clock cycles between end of read access and BE negation
0x1 : RBEN_1
1 EIM clock cycles between end of read access and BE negation
0x2 : RBEN_2
2 EIM clock cycles between end of read access and BE negation
0x7 : RBEN_7
7 EIM clock cycles between end of read access and BE negation
End of enumeration elements list.
RBE : Read BE enable. This bit field determines if BE will be asserted during read access.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RBE_0
- BE are disabled during read access.
End of enumeration elements list.
RBEA : Read BE Assertion
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : RBEA_0
0 EIM clock cycles between beginning of read access and BE assertion
0x1 : RBEA_1
1 EIM clock cycles between beginning of read access and BE assertion
0x2 : RBEA_2
2 EIM clock cycles between beginning of read access and BE assertion
0x7 : RBEA_7
7 EIM clock cycles between beginning of read access and BE assertion
End of enumeration elements list.
RL : Read Latency
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : RL_0
Feedback clock loop delay is up to 1 cycle for BCD = 0 or 1.5 cycles for BCD != 0
0x1 : RL_1
Feedback clock loop delay is up to 2 cycles for BCD = 0 or 2.5 cycles for BCD != 0
0x2 : RL_2
Feedback clock loop delay is up to 3 cycles for BCD = 0 or 3.5 cycles for BCD != 0
0x3 : RL_3
Feedback clock loop delay is up to 4 cycles for BCD = 0 or 4.5 cycles for BCD != 0
End of enumeration elements list.
PAT : Page Access Time
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : PAT_0
Address width is 2 EIM clock cycles
0x1 : PAT_1
Address width is 3 EIM clock cycles
0x2 : PAT_2
Address width is 4 EIM clock cycles
0x3 : PAT_3
Address width is 5 EIM clock cycles
0x4 : PAT_4
Address width is 6 EIM clock cycles
0x5 : PAT_5
Address width is 7 EIM clock cycles
0x6 : PAT_6
Address width is 8 EIM clock cycles
0x7 : PAT_7
Address width is 9 EIM clock cycles
End of enumeration elements list.
APR : Asynchronous Page Read
bits : 15 - 15 (1 bit)
access : read-write
Chip Select n General Configuration Register 2
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADH : Address hold time - This bit field determine the address hold time after ADV negation when mum = 1 (muxed mode)
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ADH_0
0 cycle after ADV negation
0x1 : ADH_1
1 cycle after ADV negation
0x2 : ADH_2
2 cycle after ADV negation
End of enumeration elements list.
DAPS : Data Acknowledge Poling Start
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : DAPS_0
3 EIM clk cycle between start of access and first DTACK check
0x1 : DAPS_1
4 EIM clk cycles between start of access and first DTACK check
0x2 : DAPS_2
5 EIM clk cycles between start of access and first DTACK check
0x7 : DAPS_7
10 EIM clk cycles between start of access and first DTACK check
0xB : DAPS_11
14 EIM clk cycles between start of access and first DTACK check
0xF : DAPS_15
18 EIM clk cycles between start of access and first DTACK check
End of enumeration elements list.
DAE : Data Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DAE_0
DTACK signal use is disable
0x1 : DAE_1
DTACK signal use is enable
End of enumeration elements list.
DAP : Data Acknowledge Polarity
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DAP_0
DTACK signal is active high
0x1 : DAP_1
DTACK signal is active low
End of enumeration elements list.
MUX16_BYP_GRANT : Muxed 16 bypass grant
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : MUX16_BYP_GRANT_0
EIM waits for grant before driving a 16 bit muxed mode access to the memory.
0x1 : MUX16_BYP_GRANT_1
EIM ignores the grant signal and immediately drives a 16 bit muxed mode access to the memory.
End of enumeration elements list.
Chip Select n Read Configuration Register 1
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCSN : Read CS Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : RCSN_0
0 EIM clock cycles between end of read access and CS negation
0x1 : RCSN_1
1 EIM clock cycles between end of read access and CS negation
0x2 : RCSN_2
2 EIM clock cycles between end of read access and CS negation
0x7 : RCSN_7
7 EIM clock cycles between end of read access and CS negation
End of enumeration elements list.
RCSA : Read CS Assertion
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : RCSA_0
0 EIM clock cycles between beginning of read access and CS assertion
0x1 : RCSA_1
1 EIM clock cycles between beginning of read access and CS assertion
0x2 : RCSA_2
2 EIM clock cycles between beginning of read access and CS assertion
0x7 : RCSA_7
7 EIM clock cycles between beginning of read access and CS assertion
End of enumeration elements list.
OEN : OE Negation
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : OEN_0
0 EIM clock cycles between end of access and OE negation
0x1 : OEN_1
1 EIM clock cycles between end of access and OE negation
0x2 : OEN_2
2 EIM clock cycles between end of access and OE negation
0x7 : OEN_7
7 EIM clock cycles between end of access and OE negation
End of enumeration elements list.
OEA : OE Assertion
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : OEA_0
0 EIM clock cycles between beginning of access and OE assertion
0x1 : OEA_1
1 EIM clock cycles between beginning of access and OE assertion
0x2 : OEA_2
2 EIM clock cycles between beginning of access and OE assertion
0x7 : OEA_7
7 EIM clock cycles between beginning of access and OE assertion
End of enumeration elements list.
RADVN : ADV Negation
bits : 16 - 18 (3 bit)
access : read-write
RAL : Read ADV Low
bits : 19 - 19 (1 bit)
access : read-write
RADVA : ADV Assertion
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : RADVA_0
0 EIM clock cycles between beginning of access and ADV assertion
0x1 : RADVA_1
1 EIM clock cycles between beginning of access and ADV assertion
0x2 : RADVA_2
2 EIM clock cycles between beginning of access and ADV assertion
0x7 : RADVA_7
7 EIM clock cycles between beginning of access and ADV assertion
End of enumeration elements list.
RWSC : Read Wait State Control
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x1 : RWSC_1
RWSC value is 1
0x2 : RWSC_2
RWSC value is 2
0x3D : RWSC_61
RWSC value is 61
0x3E : RWSC_62
RWSC value is 62
0x3F : RWSC_63
RWSC value is 63
End of enumeration elements list.
Chip Select n Read Configuration Register 2
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBEN : Read BE Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : RBEN_0
0 EIM clock cycles between end of read access and BE negation
0x1 : RBEN_1
1 EIM clock cycles between end of read access and BE negation
0x2 : RBEN_2
2 EIM clock cycles between end of read access and BE negation
0x7 : RBEN_7
7 EIM clock cycles between end of read access and BE negation
End of enumeration elements list.
RBE : Read BE enable. This bit field determines if BE will be asserted during read access.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RBE_0
- BE are disabled during read access.
End of enumeration elements list.
RBEA : Read BE Assertion
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : RBEA_0
0 EIM clock cycles between beginning of read access and BE assertion
0x1 : RBEA_1
1 EIM clock cycles between beginning of read access and BE assertion
0x2 : RBEA_2
2 EIM clock cycles between beginning of read access and BE assertion
0x7 : RBEA_7
7 EIM clock cycles between beginning of read access and BE assertion
End of enumeration elements list.
RL : Read Latency
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : RL_0
Feedback clock loop delay is up to 1 cycle for BCD = 0 or 1.5 cycles for BCD != 0
0x1 : RL_1
Feedback clock loop delay is up to 2 cycles for BCD = 0 or 2.5 cycles for BCD != 0
0x2 : RL_2
Feedback clock loop delay is up to 3 cycles for BCD = 0 or 3.5 cycles for BCD != 0
0x3 : RL_3
Feedback clock loop delay is up to 4 cycles for BCD = 0 or 4.5 cycles for BCD != 0
End of enumeration elements list.
PAT : Page Access Time
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : PAT_0
Address width is 2 EIM clock cycles
0x1 : PAT_1
Address width is 3 EIM clock cycles
0x2 : PAT_2
Address width is 4 EIM clock cycles
0x3 : PAT_3
Address width is 5 EIM clock cycles
0x4 : PAT_4
Address width is 6 EIM clock cycles
0x5 : PAT_5
Address width is 7 EIM clock cycles
0x6 : PAT_6
Address width is 8 EIM clock cycles
0x7 : PAT_7
Address width is 9 EIM clock cycles
End of enumeration elements list.
APR : Asynchronous Page Read
bits : 15 - 15 (1 bit)
access : read-write
Chip Select n Write Configuration Register 1
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WCSN : Write CS Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : WCSN_0
0 EIM clock cycles between end of read access and CS negation
0x1 : WCSN_1
1 EIM clock cycles between end of read access and CS negation
0x2 : WCSN_2
2 EIM clock cycles between end of read access and CS negation
0x7 : WCSN_7
7 EIM clock cycles between end of read access and CS negation
End of enumeration elements list.
WCSA : Write CS Assertion
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : WCSA_0
0 EIM clock cycles between beginning of write access and CS assertion
0x1 : WCSA_1
1 EIM clock cycles between beginning of write access and CS assertion
0x2 : WCSA_2
2 EIM clock cycles between beginning of write access and CS assertion
0x7 : WCSA_7
7 EIMclock cycles between beginning of write access and CS assertion
End of enumeration elements list.
WEN : WE Negation
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : WEN_0
0 EIM clock cycles between beginning of access and WE assertion
0x1 : WEN_1
1 EIM clock cycles between beginning of access and WE assertion
0x2 : WEN_2
2 EIM clock cycles between beginning of access and WE assertion
0x7 : WEN_7
7 EIM clock cycles between beginning of access and WE assertion
End of enumeration elements list.
WEA : WE Assertion
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : WEA_0
0 EIM clock cycles between beginning of access and WE assertion
0x1 : WEA_1
1 EIM clock cycles between beginning of access and WE assertion
0x2 : WEA_2
2 EIM clock cycles between beginning of access and WE assertion
0x7 : WEA_7
7 EIMclock cycles between beginning of access and WE assertion
End of enumeration elements list.
WBEN : BE[3:0] Negation
bits : 12 - 14 (3 bit)
access : read-write
WBEA : BE Assertion
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0 : WBEA_0
0 EIM clock cycles between beginning of access and BE assertion
0x1 : WBEA_1
1 EIM clock cycles between beginning of access and BE assertion
0x2 : WBEA_2
2 EIM clock cycles between beginning of access and BE assertion
0x7 : WBEA_7
7 EIM clock cycles between beginning of access and BE assertion
End of enumeration elements list.
WADVN : ADV Negation
bits : 18 - 20 (3 bit)
access : read-write
WADVA : ADV Assertion
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0 : WADVA_0
0 EIM clock cycles between beginning of access and ADV assertion
0x1 : WADVA_1
1 EIM clock cycles between beginning of access and ADV assertion
0x2 : WADVA_2
2 EIM clock cycles between beginning of access and ADV assertion
0x7 : WADVA_7
7 EIM clock cycles between beginning of access and ADV assertion
End of enumeration elements list.
WWSC : Write Wait State Control
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x1 : WWSC_1
WWSC value is 1
0x2 : WWSC_2
WWSC value is 2
0x3 : WWSC_3
WWSC value is 3
0x3F : WWSC_63
WWSC value is 63
End of enumeration elements list.
WBED : Write Byte Enable Disable
bits : 30 - 30 (1 bit)
access : read-write
WAL : Write ADV Low
bits : 31 - 31 (1 bit)
access : read-write
Chip Select n Write Configuration Register 2
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WBCDD : Write Burst Clock Divisor Decrement
bits : 0 - 0 (1 bit)
access : read-write
Chip Select n Write Configuration Register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WCSN : Write CS Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : WCSN_0
0 EIM clock cycles between end of read access and CS negation
0x1 : WCSN_1
1 EIM clock cycles between end of read access and CS negation
0x2 : WCSN_2
2 EIM clock cycles between end of read access and CS negation
0x7 : WCSN_7
7 EIM clock cycles between end of read access and CS negation
End of enumeration elements list.
WCSA : Write CS Assertion
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : WCSA_0
0 EIM clock cycles between beginning of write access and CS assertion
0x1 : WCSA_1
1 EIM clock cycles between beginning of write access and CS assertion
0x2 : WCSA_2
2 EIM clock cycles between beginning of write access and CS assertion
0x7 : WCSA_7
7 EIMclock cycles between beginning of write access and CS assertion
End of enumeration elements list.
WEN : WE Negation
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : WEN_0
0 EIM clock cycles between beginning of access and WE assertion
0x1 : WEN_1
1 EIM clock cycles between beginning of access and WE assertion
0x2 : WEN_2
2 EIM clock cycles between beginning of access and WE assertion
0x7 : WEN_7
7 EIM clock cycles between beginning of access and WE assertion
End of enumeration elements list.
WEA : WE Assertion
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : WEA_0
0 EIM clock cycles between beginning of access and WE assertion
0x1 : WEA_1
1 EIM clock cycles between beginning of access and WE assertion
0x2 : WEA_2
2 EIM clock cycles between beginning of access and WE assertion
0x7 : WEA_7
7 EIMclock cycles between beginning of access and WE assertion
End of enumeration elements list.
WBEN : BE[3:0] Negation
bits : 12 - 14 (3 bit)
access : read-write
WBEA : BE Assertion
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0 : WBEA_0
0 EIM clock cycles between beginning of access and BE assertion
0x1 : WBEA_1
1 EIM clock cycles between beginning of access and BE assertion
0x2 : WBEA_2
2 EIM clock cycles between beginning of access and BE assertion
0x7 : WBEA_7
7 EIM clock cycles between beginning of access and BE assertion
End of enumeration elements list.
WADVN : ADV Negation
bits : 18 - 20 (3 bit)
access : read-write
WADVA : ADV Assertion
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0 : WADVA_0
0 EIM clock cycles between beginning of access and ADV assertion
0x1 : WADVA_1
1 EIM clock cycles between beginning of access and ADV assertion
0x2 : WADVA_2
2 EIM clock cycles between beginning of access and ADV assertion
0x7 : WADVA_7
7 EIM clock cycles between beginning of access and ADV assertion
End of enumeration elements list.
WWSC : Write Wait State Control
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x1 : WWSC_1
WWSC value is 1
0x2 : WWSC_2
WWSC value is 2
0x3 : WWSC_3
WWSC value is 3
0x3F : WWSC_63
WWSC value is 63
End of enumeration elements list.
WBED : Write Byte Enable Disable
bits : 30 - 30 (1 bit)
access : read-write
WAL : Write ADV Low
bits : 31 - 31 (1 bit)
access : read-write
Chip Select n General Configuration Register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADH : Address hold time - This bit field determine the address hold time after ADV negation when mum = 1 (muxed mode)
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ADH_0
0 cycle after ADV negation
0x1 : ADH_1
1 cycle after ADV negation
0x2 : ADH_2
2 cycle after ADV negation
End of enumeration elements list.
DAPS : Data Acknowledge Poling Start
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : DAPS_0
3 EIM clk cycle between start of access and first DTACK check
0x1 : DAPS_1
4 EIM clk cycles between start of access and first DTACK check
0x2 : DAPS_2
5 EIM clk cycles between start of access and first DTACK check
0x7 : DAPS_7
10 EIM clk cycles between start of access and first DTACK check
0xB : DAPS_11
14 EIM clk cycles between start of access and first DTACK check
0xF : DAPS_15
18 EIM clk cycles between start of access and first DTACK check
End of enumeration elements list.
DAE : Data Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DAE_0
DTACK signal use is disable
0x1 : DAE_1
DTACK signal use is enable
End of enumeration elements list.
DAP : Data Acknowledge Polarity
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DAP_0
DTACK signal is active high
0x1 : DAP_1
DTACK signal is active low
End of enumeration elements list.
MUX16_BYP_GRANT : Muxed 16 bypass grant
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : MUX16_BYP_GRANT_0
EIM waits for grant before driving a 16 bit muxed mode access to the memory.
0x1 : MUX16_BYP_GRANT_1
EIM ignores the grant signal and immediately drives a 16 bit muxed mode access to the memory.
End of enumeration elements list.
Chip Select n Write Configuration Register 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WBCDD : Write Burst Clock Divisor Decrement
bits : 0 - 0 (1 bit)
access : read-write
Chip Select n Read Configuration Register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCSN : Read CS Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : RCSN_0
0 EIM clock cycles between end of read access and CS negation
0x1 : RCSN_1
1 EIM clock cycles between end of read access and CS negation
0x2 : RCSN_2
2 EIM clock cycles between end of read access and CS negation
0x7 : RCSN_7
7 EIM clock cycles between end of read access and CS negation
End of enumeration elements list.
RCSA : Read CS Assertion
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : RCSA_0
0 EIM clock cycles between beginning of read access and CS assertion
0x1 : RCSA_1
1 EIM clock cycles between beginning of read access and CS assertion
0x2 : RCSA_2
2 EIM clock cycles between beginning of read access and CS assertion
0x7 : RCSA_7
7 EIM clock cycles between beginning of read access and CS assertion
End of enumeration elements list.
OEN : OE Negation
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : OEN_0
0 EIM clock cycles between end of access and OE negation
0x1 : OEN_1
1 EIM clock cycles between end of access and OE negation
0x2 : OEN_2
2 EIM clock cycles between end of access and OE negation
0x7 : OEN_7
7 EIM clock cycles between end of access and OE negation
End of enumeration elements list.
OEA : OE Assertion
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : OEA_0
0 EIM clock cycles between beginning of access and OE assertion
0x1 : OEA_1
1 EIM clock cycles between beginning of access and OE assertion
0x2 : OEA_2
2 EIM clock cycles between beginning of access and OE assertion
0x7 : OEA_7
7 EIM clock cycles between beginning of access and OE assertion
End of enumeration elements list.
RADVN : ADV Negation
bits : 16 - 18 (3 bit)
access : read-write
RAL : Read ADV Low
bits : 19 - 19 (1 bit)
access : read-write
RADVA : ADV Assertion
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : RADVA_0
0 EIM clock cycles between beginning of access and ADV assertion
0x1 : RADVA_1
1 EIM clock cycles between beginning of access and ADV assertion
0x2 : RADVA_2
2 EIM clock cycles between beginning of access and ADV assertion
0x7 : RADVA_7
7 EIM clock cycles between beginning of access and ADV assertion
End of enumeration elements list.
RWSC : Read Wait State Control
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x1 : RWSC_1
RWSC value is 1
0x2 : RWSC_2
RWSC value is 2
0x3D : RWSC_61
RWSC value is 61
0x3E : RWSC_62
RWSC value is 62
0x3F : RWSC_63
RWSC value is 63
End of enumeration elements list.
Chip Select n Read Configuration Register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBEN : Read BE Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : RBEN_0
0 EIM clock cycles between end of read access and BE negation
0x1 : RBEN_1
1 EIM clock cycles between end of read access and BE negation
0x2 : RBEN_2
2 EIM clock cycles between end of read access and BE negation
0x7 : RBEN_7
7 EIM clock cycles between end of read access and BE negation
End of enumeration elements list.
RBE : Read BE enable. This bit field determines if BE will be asserted during read access.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RBE_0
- BE are disabled during read access.
End of enumeration elements list.
RBEA : Read BE Assertion
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : RBEA_0
0 EIM clock cycles between beginning of read access and BE assertion
0x1 : RBEA_1
1 EIM clock cycles between beginning of read access and BE assertion
0x2 : RBEA_2
2 EIM clock cycles between beginning of read access and BE assertion
0x7 : RBEA_7
7 EIM clock cycles between beginning of read access and BE assertion
End of enumeration elements list.
RL : Read Latency
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : RL_0
Feedback clock loop delay is up to 1 cycle for BCD = 0 or 1.5 cycles for BCD != 0
0x1 : RL_1
Feedback clock loop delay is up to 2 cycles for BCD = 0 or 2.5 cycles for BCD != 0
0x2 : RL_2
Feedback clock loop delay is up to 3 cycles for BCD = 0 or 3.5 cycles for BCD != 0
0x3 : RL_3
Feedback clock loop delay is up to 4 cycles for BCD = 0 or 4.5 cycles for BCD != 0
End of enumeration elements list.
PAT : Page Access Time
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : PAT_0
Address width is 2 EIM clock cycles
0x1 : PAT_1
Address width is 3 EIM clock cycles
0x2 : PAT_2
Address width is 4 EIM clock cycles
0x3 : PAT_3
Address width is 5 EIM clock cycles
0x4 : PAT_4
Address width is 6 EIM clock cycles
0x5 : PAT_5
Address width is 7 EIM clock cycles
0x6 : PAT_6
Address width is 8 EIM clock cycles
0x7 : PAT_7
Address width is 9 EIM clock cycles
End of enumeration elements list.
APR : Asynchronous Page Read
bits : 15 - 15 (1 bit)
access : read-write
Chip Select n General Configuration Register 1
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEN : CS Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CSEN_0
Chip select function is disabled; attempts to access an address mapped by this chip select results in an error respond and no assertion of the chip select output
0x1 : CSEN_1
Chip select is enabled, and is asserted when presented with a valid access.
End of enumeration elements list.
SWR : Synchronous Write Data
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SWR_0
write accesses are in Asynchronous mode
0x1 : SWR_1
write accesses are in Synchronous mode
End of enumeration elements list.
SRD : Synchronous Read Data
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRD_0
read accesses are in Asynchronous mode
0x1 : SRD_1
read accesses are in Synchronous mode
End of enumeration elements list.
MUM : Multiplexed Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : MUM_0
Multiplexed Mode disable
0x1 : MUM_1
Multiplexed Mode enable
End of enumeration elements list.
WFL : Write Fix Latency
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : WFL_0
the External device WAIT signal is being monitored, and it reflect the external data bus state
0x1 : WFL_1
the state of the External devices is determined internally (Fix latency mode only)
End of enumeration elements list.
RFL : Read Fix Latency
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : RFL_0
the External device WAIT signal is being monitored, and it reflect the external data bus state
0x1 : RFL_1
the state of the External devices is determined internally (Fix latency mode only)
End of enumeration elements list.
CRE : Configuration Register Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CRE_0
CRE signal use is disable
0x1 : CRE_1
CRE signal use is enable
End of enumeration elements list.
CREP : Configuration Register Enable Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : CREP_0
CRE signal is active low
0x1 : CREP_1
CRE signal is active high
End of enumeration elements list.
BL : Burst Length
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : BL_0
4 words Memory wrap burst length (read page burst size when APR = 1)
0x1 : BL_1
8 words Memory wrap burst length (read page burst size when APR = 1)
0x2 : BL_2
16 words Memory wrap burst length (read page burst size when APR = 1)
0x3 : BL_3
32 words Memory wrap burst length (read page burst size when APR = 1)
0x4 : BL_4
Continuous burst length (2 words read page burst size when APR = 1)
End of enumeration elements list.
WC : Write Continuous
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : WC_0
Write access burst length occurs according to BL value.
0x1 : WC_1
Write access burst length is continuous.
End of enumeration elements list.
BCD : Burst Clock Divisor
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : BCD_0
Divide EIM clock by 1
0x1 : BCD_1
Divide EIM clock by 2
0x2 : BCD_2
Divide EIM clock by 3
0x3 : BCD_3
Divide EIM clock by 4
End of enumeration elements list.
BCS : Burst Clock Start
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BCS_0
0 EIM clock cycle additional delay
0x1 : BCS_1
1 EIM clock cycle additional delay
0x2 : BCS_2
2 EIM clock cycle additional delay
0x3 : BCS_3
3 EIM clock cycle additional delay
End of enumeration elements list.
DSZ : Data Port Size
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x1 : DSZ_1
16 bit port resides on DATA[15:0]
0x2 : DSZ_2
16 bit port resides on DATA[31:16]
0x3 : DSZ_3
32 bit port resides on DATA[31:0]
0x4 : DSZ_4
8 bit port resides on DATA[7:0]
0x5 : DSZ_5
8 bit port resides on DATA[15:8]
0x6 : DSZ_6
8 bit port resides on DATA[23:16]
0x7 : DSZ_7
8 bit port resides on DATA[31:24]
End of enumeration elements list.
SP : Supervisor Protect
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SP_0
User mode accesses are allowed in the memory range defined by chip select.
0x1 : SP_1
User mode accesses are prohibited. All attempts to access an address mapped by this chip select in User mode results in an error response and no assertion of the chip select output.
End of enumeration elements list.
CSREC : CS Recovery
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : CSREC_0
0 EIM clock cycles minimum width of CS, OE and WE signals (read async. mode only)
0x1 : CSREC_1
1 EIM clock cycles minimum width of CS, OE and WE signals
0x2 : CSREC_2
2 EIM clock cycles minimum width of CS, OE and WE signals
0x7 : CSREC_7
7 EIM clock cycles minimum width of CS, OE and WE signals
End of enumeration elements list.
AUS : Address UnShifted
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : AUS_0
Address shifted according to port size (DSZ config) (128 Mbyte maximum supported memory density).
0x1 : AUS_1
Address unshifted (32 Mbyte maximum supported memory density).
End of enumeration elements list.
GBC : Gap Between Chip Selects
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : GBC_0
minimum of 0 EIM clock cycles before next access from different chip select (async. mode only)
0x1 : GBC_1
minimum of 1 EIM clock cycles before next access from different chip select
0x2 : GBC_2
minimum of 2 EIM clock cycles before next access from different chip select
0x7 : GBC_7
minimum of 7 EIM clock cycles before next access from different chip select
End of enumeration elements list.
WP : Write Protect
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : WP_0
Writes are allowed in the memory range defined by chip.
0x1 : WP_1
Writes are prohibited. All attempts to write to an address mapped by this chip select result in a error response and no assertion of the chip select output.
End of enumeration elements list.
PSZ : Page Size
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : PSZ_0
8 words page size
0x1 : PSZ_1
16 words page size
0x2 : PSZ_2
32 words page size
0x3 : PSZ_3
64 words page size
0x4 : PSZ_4
128 words page size
0x5 : PSZ_5
256 words page size
0x6 : PSZ_6
512 words page size
0x7 : PSZ_7
1024 (1k) words page size
0x8 : PSZ_8
2048 (2k) words page size
0x9 : PSZ_9
- 1111 Reserved
End of enumeration elements list.
Chip Select n Write Configuration Register 1
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WCSN : Write CS Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : WCSN_0
0 EIM clock cycles between end of read access and CS negation
0x1 : WCSN_1
1 EIM clock cycles between end of read access and CS negation
0x2 : WCSN_2
2 EIM clock cycles between end of read access and CS negation
0x7 : WCSN_7
7 EIM clock cycles between end of read access and CS negation
End of enumeration elements list.
WCSA : Write CS Assertion
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : WCSA_0
0 EIM clock cycles between beginning of write access and CS assertion
0x1 : WCSA_1
1 EIM clock cycles between beginning of write access and CS assertion
0x2 : WCSA_2
2 EIM clock cycles between beginning of write access and CS assertion
0x7 : WCSA_7
7 EIMclock cycles between beginning of write access and CS assertion
End of enumeration elements list.
WEN : WE Negation
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : WEN_0
0 EIM clock cycles between beginning of access and WE assertion
0x1 : WEN_1
1 EIM clock cycles between beginning of access and WE assertion
0x2 : WEN_2
2 EIM clock cycles between beginning of access and WE assertion
0x7 : WEN_7
7 EIM clock cycles between beginning of access and WE assertion
End of enumeration elements list.
WEA : WE Assertion
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : WEA_0
0 EIM clock cycles between beginning of access and WE assertion
0x1 : WEA_1
1 EIM clock cycles between beginning of access and WE assertion
0x2 : WEA_2
2 EIM clock cycles between beginning of access and WE assertion
0x7 : WEA_7
7 EIMclock cycles between beginning of access and WE assertion
End of enumeration elements list.
WBEN : BE[3:0] Negation
bits : 12 - 14 (3 bit)
access : read-write
WBEA : BE Assertion
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0 : WBEA_0
0 EIM clock cycles between beginning of access and BE assertion
0x1 : WBEA_1
1 EIM clock cycles between beginning of access and BE assertion
0x2 : WBEA_2
2 EIM clock cycles between beginning of access and BE assertion
0x7 : WBEA_7
7 EIM clock cycles between beginning of access and BE assertion
End of enumeration elements list.
WADVN : ADV Negation
bits : 18 - 20 (3 bit)
access : read-write
WADVA : ADV Assertion
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0 : WADVA_0
0 EIM clock cycles between beginning of access and ADV assertion
0x1 : WADVA_1
1 EIM clock cycles between beginning of access and ADV assertion
0x2 : WADVA_2
2 EIM clock cycles between beginning of access and ADV assertion
0x7 : WADVA_7
7 EIM clock cycles between beginning of access and ADV assertion
End of enumeration elements list.
WWSC : Write Wait State Control
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x1 : WWSC_1
WWSC value is 1
0x2 : WWSC_2
WWSC value is 2
0x3 : WWSC_3
WWSC value is 3
0x3F : WWSC_63
WWSC value is 63
End of enumeration elements list.
WBED : Write Byte Enable Disable
bits : 30 - 30 (1 bit)
access : read-write
WAL : Write ADV Low
bits : 31 - 31 (1 bit)
access : read-write
Chip Select n Write Configuration Register 2
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WBCDD : Write Burst Clock Divisor Decrement
bits : 0 - 0 (1 bit)
access : read-write
Chip Select n General Configuration Register 2
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADH : Address hold time - This bit field determine the address hold time after ADV negation when mum = 1 (muxed mode)
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ADH_0
0 cycle after ADV negation
0x1 : ADH_1
1 cycle after ADV negation
0x2 : ADH_2
2 cycle after ADV negation
End of enumeration elements list.
DAPS : Data Acknowledge Poling Start
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : DAPS_0
3 EIM clk cycle between start of access and first DTACK check
0x1 : DAPS_1
4 EIM clk cycles between start of access and first DTACK check
0x2 : DAPS_2
5 EIM clk cycles between start of access and first DTACK check
0x7 : DAPS_7
10 EIM clk cycles between start of access and first DTACK check
0xB : DAPS_11
14 EIM clk cycles between start of access and first DTACK check
0xF : DAPS_15
18 EIM clk cycles between start of access and first DTACK check
End of enumeration elements list.
DAE : Data Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DAE_0
DTACK signal use is disable
0x1 : DAE_1
DTACK signal use is enable
End of enumeration elements list.
DAP : Data Acknowledge Polarity
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DAP_0
DTACK signal is active high
0x1 : DAP_1
DTACK signal is active low
End of enumeration elements list.
MUX16_BYP_GRANT : Muxed 16 bypass grant
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : MUX16_BYP_GRANT_0
EIM waits for grant before driving a 16 bit muxed mode access to the memory.
0x1 : MUX16_BYP_GRANT_1
EIM ignores the grant signal and immediately drives a 16 bit muxed mode access to the memory.
End of enumeration elements list.
Chip Select n Read Configuration Register 1
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCSN : Read CS Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : RCSN_0
0 EIM clock cycles between end of read access and CS negation
0x1 : RCSN_1
1 EIM clock cycles between end of read access and CS negation
0x2 : RCSN_2
2 EIM clock cycles between end of read access and CS negation
0x7 : RCSN_7
7 EIM clock cycles between end of read access and CS negation
End of enumeration elements list.
RCSA : Read CS Assertion
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : RCSA_0
0 EIM clock cycles between beginning of read access and CS assertion
0x1 : RCSA_1
1 EIM clock cycles between beginning of read access and CS assertion
0x2 : RCSA_2
2 EIM clock cycles between beginning of read access and CS assertion
0x7 : RCSA_7
7 EIM clock cycles between beginning of read access and CS assertion
End of enumeration elements list.
OEN : OE Negation
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : OEN_0
0 EIM clock cycles between end of access and OE negation
0x1 : OEN_1
1 EIM clock cycles between end of access and OE negation
0x2 : OEN_2
2 EIM clock cycles between end of access and OE negation
0x7 : OEN_7
7 EIM clock cycles between end of access and OE negation
End of enumeration elements list.
OEA : OE Assertion
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : OEA_0
0 EIM clock cycles between beginning of access and OE assertion
0x1 : OEA_1
1 EIM clock cycles between beginning of access and OE assertion
0x2 : OEA_2
2 EIM clock cycles between beginning of access and OE assertion
0x7 : OEA_7
7 EIM clock cycles between beginning of access and OE assertion
End of enumeration elements list.
RADVN : ADV Negation
bits : 16 - 18 (3 bit)
access : read-write
RAL : Read ADV Low
bits : 19 - 19 (1 bit)
access : read-write
RADVA : ADV Assertion
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : RADVA_0
0 EIM clock cycles between beginning of access and ADV assertion
0x1 : RADVA_1
1 EIM clock cycles between beginning of access and ADV assertion
0x2 : RADVA_2
2 EIM clock cycles between beginning of access and ADV assertion
0x7 : RADVA_7
7 EIM clock cycles between beginning of access and ADV assertion
End of enumeration elements list.
RWSC : Read Wait State Control
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x1 : RWSC_1
RWSC value is 1
0x2 : RWSC_2
RWSC value is 2
0x3D : RWSC_61
RWSC value is 61
0x3E : RWSC_62
RWSC value is 62
0x3F : RWSC_63
RWSC value is 63
End of enumeration elements list.
Chip Select n Read Configuration Register 2
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBEN : Read BE Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : RBEN_0
0 EIM clock cycles between end of read access and BE negation
0x1 : RBEN_1
1 EIM clock cycles between end of read access and BE negation
0x2 : RBEN_2
2 EIM clock cycles between end of read access and BE negation
0x7 : RBEN_7
7 EIM clock cycles between end of read access and BE negation
End of enumeration elements list.
RBE : Read BE enable. This bit field determines if BE will be asserted during read access.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RBE_0
- BE are disabled during read access.
End of enumeration elements list.
RBEA : Read BE Assertion
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : RBEA_0
0 EIM clock cycles between beginning of read access and BE assertion
0x1 : RBEA_1
1 EIM clock cycles between beginning of read access and BE assertion
0x2 : RBEA_2
2 EIM clock cycles between beginning of read access and BE assertion
0x7 : RBEA_7
7 EIM clock cycles between beginning of read access and BE assertion
End of enumeration elements list.
RL : Read Latency
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : RL_0
Feedback clock loop delay is up to 1 cycle for BCD = 0 or 1.5 cycles for BCD != 0
0x1 : RL_1
Feedback clock loop delay is up to 2 cycles for BCD = 0 or 2.5 cycles for BCD != 0
0x2 : RL_2
Feedback clock loop delay is up to 3 cycles for BCD = 0 or 3.5 cycles for BCD != 0
0x3 : RL_3
Feedback clock loop delay is up to 4 cycles for BCD = 0 or 4.5 cycles for BCD != 0
End of enumeration elements list.
PAT : Page Access Time
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : PAT_0
Address width is 2 EIM clock cycles
0x1 : PAT_1
Address width is 3 EIM clock cycles
0x2 : PAT_2
Address width is 4 EIM clock cycles
0x3 : PAT_3
Address width is 5 EIM clock cycles
0x4 : PAT_4
Address width is 6 EIM clock cycles
0x5 : PAT_5
Address width is 7 EIM clock cycles
0x6 : PAT_6
Address width is 8 EIM clock cycles
0x7 : PAT_7
Address width is 9 EIM clock cycles
End of enumeration elements list.
APR : Asynchronous Page Read
bits : 15 - 15 (1 bit)
access : read-write
Chip Select n General Configuration Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADH : Address hold time - This bit field determine the address hold time after ADV negation when mum = 1 (muxed mode)
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ADH_0
0 cycle after ADV negation
0x1 : ADH_1
1 cycle after ADV negation
0x2 : ADH_2
2 cycle after ADV negation
End of enumeration elements list.
DAPS : Data Acknowledge Poling Start
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : DAPS_0
3 EIM clk cycle between start of access and first DTACK check
0x1 : DAPS_1
4 EIM clk cycles between start of access and first DTACK check
0x2 : DAPS_2
5 EIM clk cycles between start of access and first DTACK check
0x7 : DAPS_7
10 EIM clk cycles between start of access and first DTACK check
0xB : DAPS_11
14 EIM clk cycles between start of access and first DTACK check
0xF : DAPS_15
18 EIM clk cycles between start of access and first DTACK check
End of enumeration elements list.
DAE : Data Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DAE_0
DTACK signal use is disable
0x1 : DAE_1
DTACK signal use is enable
End of enumeration elements list.
DAP : Data Acknowledge Polarity
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DAP_0
DTACK signal is active high
0x1 : DAP_1
DTACK signal is active low
End of enumeration elements list.
MUX16_BYP_GRANT : Muxed 16 bypass grant
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : MUX16_BYP_GRANT_0
EIM waits for grant before driving a 16 bit muxed mode access to the memory.
0x1 : MUX16_BYP_GRANT_1
EIM ignores the grant signal and immediately drives a 16 bit muxed mode access to the memory.
End of enumeration elements list.
Chip Select n Write Configuration Register 1
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WCSN : Write CS Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : WCSN_0
0 EIM clock cycles between end of read access and CS negation
0x1 : WCSN_1
1 EIM clock cycles between end of read access and CS negation
0x2 : WCSN_2
2 EIM clock cycles between end of read access and CS negation
0x7 : WCSN_7
7 EIM clock cycles between end of read access and CS negation
End of enumeration elements list.
WCSA : Write CS Assertion
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : WCSA_0
0 EIM clock cycles between beginning of write access and CS assertion
0x1 : WCSA_1
1 EIM clock cycles between beginning of write access and CS assertion
0x2 : WCSA_2
2 EIM clock cycles between beginning of write access and CS assertion
0x7 : WCSA_7
7 EIMclock cycles between beginning of write access and CS assertion
End of enumeration elements list.
WEN : WE Negation
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : WEN_0
0 EIM clock cycles between beginning of access and WE assertion
0x1 : WEN_1
1 EIM clock cycles between beginning of access and WE assertion
0x2 : WEN_2
2 EIM clock cycles between beginning of access and WE assertion
0x7 : WEN_7
7 EIM clock cycles between beginning of access and WE assertion
End of enumeration elements list.
WEA : WE Assertion
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : WEA_0
0 EIM clock cycles between beginning of access and WE assertion
0x1 : WEA_1
1 EIM clock cycles between beginning of access and WE assertion
0x2 : WEA_2
2 EIM clock cycles between beginning of access and WE assertion
0x7 : WEA_7
7 EIMclock cycles between beginning of access and WE assertion
End of enumeration elements list.
WBEN : BE[3:0] Negation
bits : 12 - 14 (3 bit)
access : read-write
WBEA : BE Assertion
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0 : WBEA_0
0 EIM clock cycles between beginning of access and BE assertion
0x1 : WBEA_1
1 EIM clock cycles between beginning of access and BE assertion
0x2 : WBEA_2
2 EIM clock cycles between beginning of access and BE assertion
0x7 : WBEA_7
7 EIM clock cycles between beginning of access and BE assertion
End of enumeration elements list.
WADVN : ADV Negation
bits : 18 - 20 (3 bit)
access : read-write
WADVA : ADV Assertion
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0 : WADVA_0
0 EIM clock cycles between beginning of access and ADV assertion
0x1 : WADVA_1
1 EIM clock cycles between beginning of access and ADV assertion
0x2 : WADVA_2
2 EIM clock cycles between beginning of access and ADV assertion
0x7 : WADVA_7
7 EIM clock cycles between beginning of access and ADV assertion
End of enumeration elements list.
WWSC : Write Wait State Control
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x1 : WWSC_1
WWSC value is 1
0x2 : WWSC_2
WWSC value is 2
0x3 : WWSC_3
WWSC value is 3
0x3F : WWSC_63
WWSC value is 63
End of enumeration elements list.
WBED : Write Byte Enable Disable
bits : 30 - 30 (1 bit)
access : read-write
WAL : Write ADV Low
bits : 31 - 31 (1 bit)
access : read-write
Chip Select n General Configuration Register 1
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEN : CS Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CSEN_0
Chip select function is disabled; attempts to access an address mapped by this chip select results in an error respond and no assertion of the chip select output
0x1 : CSEN_1
Chip select is enabled, and is asserted when presented with a valid access.
End of enumeration elements list.
SWR : Synchronous Write Data
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SWR_0
write accesses are in Asynchronous mode
0x1 : SWR_1
write accesses are in Synchronous mode
End of enumeration elements list.
SRD : Synchronous Read Data
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRD_0
read accesses are in Asynchronous mode
0x1 : SRD_1
read accesses are in Synchronous mode
End of enumeration elements list.
MUM : Multiplexed Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : MUM_0
Multiplexed Mode disable
0x1 : MUM_1
Multiplexed Mode enable
End of enumeration elements list.
WFL : Write Fix Latency
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : WFL_0
the External device WAIT signal is being monitored, and it reflect the external data bus state
0x1 : WFL_1
the state of the External devices is determined internally (Fix latency mode only)
End of enumeration elements list.
RFL : Read Fix Latency
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : RFL_0
the External device WAIT signal is being monitored, and it reflect the external data bus state
0x1 : RFL_1
the state of the External devices is determined internally (Fix latency mode only)
End of enumeration elements list.
CRE : Configuration Register Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CRE_0
CRE signal use is disable
0x1 : CRE_1
CRE signal use is enable
End of enumeration elements list.
CREP : Configuration Register Enable Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : CREP_0
CRE signal is active low
0x1 : CREP_1
CRE signal is active high
End of enumeration elements list.
BL : Burst Length
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : BL_0
4 words Memory wrap burst length (read page burst size when APR = 1)
0x1 : BL_1
8 words Memory wrap burst length (read page burst size when APR = 1)
0x2 : BL_2
16 words Memory wrap burst length (read page burst size when APR = 1)
0x3 : BL_3
32 words Memory wrap burst length (read page burst size when APR = 1)
0x4 : BL_4
Continuous burst length (2 words read page burst size when APR = 1)
End of enumeration elements list.
WC : Write Continuous
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : WC_0
Write access burst length occurs according to BL value.
0x1 : WC_1
Write access burst length is continuous.
End of enumeration elements list.
BCD : Burst Clock Divisor
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : BCD_0
Divide EIM clock by 1
0x1 : BCD_1
Divide EIM clock by 2
0x2 : BCD_2
Divide EIM clock by 3
0x3 : BCD_3
Divide EIM clock by 4
End of enumeration elements list.
BCS : Burst Clock Start
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BCS_0
0 EIM clock cycle additional delay
0x1 : BCS_1
1 EIM clock cycle additional delay
0x2 : BCS_2
2 EIM clock cycle additional delay
0x3 : BCS_3
3 EIM clock cycle additional delay
End of enumeration elements list.
DSZ : Data Port Size
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x1 : DSZ_1
16 bit port resides on DATA[15:0]
0x2 : DSZ_2
16 bit port resides on DATA[31:16]
0x3 : DSZ_3
32 bit port resides on DATA[31:0]
0x4 : DSZ_4
8 bit port resides on DATA[7:0]
0x5 : DSZ_5
8 bit port resides on DATA[15:8]
0x6 : DSZ_6
8 bit port resides on DATA[23:16]
0x7 : DSZ_7
8 bit port resides on DATA[31:24]
End of enumeration elements list.
SP : Supervisor Protect
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SP_0
User mode accesses are allowed in the memory range defined by chip select.
0x1 : SP_1
User mode accesses are prohibited. All attempts to access an address mapped by this chip select in User mode results in an error response and no assertion of the chip select output.
End of enumeration elements list.
CSREC : CS Recovery
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : CSREC_0
0 EIM clock cycles minimum width of CS, OE and WE signals (read async. mode only)
0x1 : CSREC_1
1 EIM clock cycles minimum width of CS, OE and WE signals
0x2 : CSREC_2
2 EIM clock cycles minimum width of CS, OE and WE signals
0x7 : CSREC_7
7 EIM clock cycles minimum width of CS, OE and WE signals
End of enumeration elements list.
AUS : Address UnShifted
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : AUS_0
Address shifted according to port size (DSZ config) (128 Mbyte maximum supported memory density).
0x1 : AUS_1
Address unshifted (32 Mbyte maximum supported memory density).
End of enumeration elements list.
GBC : Gap Between Chip Selects
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : GBC_0
minimum of 0 EIM clock cycles before next access from different chip select (async. mode only)
0x1 : GBC_1
minimum of 1 EIM clock cycles before next access from different chip select
0x2 : GBC_2
minimum of 2 EIM clock cycles before next access from different chip select
0x7 : GBC_7
minimum of 7 EIM clock cycles before next access from different chip select
End of enumeration elements list.
WP : Write Protect
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : WP_0
Writes are allowed in the memory range defined by chip.
0x1 : WP_1
Writes are prohibited. All attempts to write to an address mapped by this chip select result in a error response and no assertion of the chip select output.
End of enumeration elements list.
PSZ : Page Size
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : PSZ_0
8 words page size
0x1 : PSZ_1
16 words page size
0x2 : PSZ_2
32 words page size
0x3 : PSZ_3
64 words page size
0x4 : PSZ_4
128 words page size
0x5 : PSZ_5
256 words page size
0x6 : PSZ_6
512 words page size
0x7 : PSZ_7
1024 (1k) words page size
0x8 : PSZ_8
2048 (2k) words page size
0x9 : PSZ_9
- 1111 Reserved
End of enumeration elements list.
EIM Configuration Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCM : Burst Clock Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : BCM_0
The burst clock runs only when accessing a chip select range with the SWR/SRD bits set. When the burst clock is not running it remains in a logic 0 state. When the burst clock is running it is configured by the BCD and BCS bit fields in the chip select Configuration Register.
0x1 : BCM_1
The burst clock runs whenever ACLK is active (independent of chip select configuration)
End of enumeration elements list.
GBCD : General Burst Clock Divisor
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : GBCD_0
Divide EIM clock by 1
0x1 : GBCD_1
Divide EIM clock by 2
0x2 : GBCD_2
Divide EIM clock by 3
0x3 : GBCD_3
Divide EIM clock by 4
End of enumeration elements list.
CONT_BCLK_SEL : Continuous BCLK select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : CONT_BCLK_SEL_0
BCLK When nesserary
0x1 : CONT_BCLK_SEL_1
BCLK Continuous
End of enumeration elements list.
INTEN : Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : INTEN_0
External interrupt Disable
0x1 : INTEN_1
External interrupt Enable
End of enumeration elements list.
INTPOL : Interrupt Polarity. This bit field determines the polarity of the external device interrupt.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : INTPOL_0
External interrupt polarity is active low
0x1 : INTPOL_1
External interrupt polarity is active high
End of enumeration elements list.
WDOG_EN : Memory WDOG enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : WDOG_EN_0
Memory WDOG is Disabled
0x1 : WDOG_EN_1
Memory WDOG is Enabled
End of enumeration elements list.
WDOG_LIMIT : Memory Watchdog (WDOG) cycle limit
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
0 : WDOG_LIMIT_0
128 BCLK cycles
0x1 : WDOG_LIMIT_1
256 BCLK cycles
0x2 : WDOG_LIMIT_2
512 BCLK cycles
0x3 : WDOG_LIMIT_3
1024 BCLK cycles
End of enumeration elements list.
FRUN_ACLK_EN : Free run ACLK enable
bits : 11 - 11 (1 bit)
access : read-write
Chip Select n Write Configuration Register 2
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WBCDD : Write Burst Clock Divisor Decrement
bits : 0 - 0 (1 bit)
access : read-write
Chip Select n General Configuration Register 2
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADH : Address hold time - This bit field determine the address hold time after ADV negation when mum = 1 (muxed mode)
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ADH_0
0 cycle after ADV negation
0x1 : ADH_1
1 cycle after ADV negation
0x2 : ADH_2
2 cycle after ADV negation
End of enumeration elements list.
DAPS : Data Acknowledge Poling Start
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : DAPS_0
3 EIM clk cycle between start of access and first DTACK check
0x1 : DAPS_1
4 EIM clk cycles between start of access and first DTACK check
0x2 : DAPS_2
5 EIM clk cycles between start of access and first DTACK check
0x7 : DAPS_7
10 EIM clk cycles between start of access and first DTACK check
0xB : DAPS_11
14 EIM clk cycles between start of access and first DTACK check
0xF : DAPS_15
18 EIM clk cycles between start of access and first DTACK check
End of enumeration elements list.
DAE : Data Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DAE_0
DTACK signal use is disable
0x1 : DAE_1
DTACK signal use is enable
End of enumeration elements list.
DAP : Data Acknowledge Polarity
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DAP_0
DTACK signal is active high
0x1 : DAP_1
DTACK signal is active low
End of enumeration elements list.
MUX16_BYP_GRANT : Muxed 16 bypass grant
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : MUX16_BYP_GRANT_0
EIM waits for grant before driving a 16 bit muxed mode access to the memory.
0x1 : MUX16_BYP_GRANT_1
EIM ignores the grant signal and immediately drives a 16 bit muxed mode access to the memory.
End of enumeration elements list.
Chip Select n Read Configuration Register 1
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCSN : Read CS Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : RCSN_0
0 EIM clock cycles between end of read access and CS negation
0x1 : RCSN_1
1 EIM clock cycles between end of read access and CS negation
0x2 : RCSN_2
2 EIM clock cycles between end of read access and CS negation
0x7 : RCSN_7
7 EIM clock cycles between end of read access and CS negation
End of enumeration elements list.
RCSA : Read CS Assertion
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : RCSA_0
0 EIM clock cycles between beginning of read access and CS assertion
0x1 : RCSA_1
1 EIM clock cycles between beginning of read access and CS assertion
0x2 : RCSA_2
2 EIM clock cycles between beginning of read access and CS assertion
0x7 : RCSA_7
7 EIM clock cycles between beginning of read access and CS assertion
End of enumeration elements list.
OEN : OE Negation
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : OEN_0
0 EIM clock cycles between end of access and OE negation
0x1 : OEN_1
1 EIM clock cycles between end of access and OE negation
0x2 : OEN_2
2 EIM clock cycles between end of access and OE negation
0x7 : OEN_7
7 EIM clock cycles between end of access and OE negation
End of enumeration elements list.
OEA : OE Assertion
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : OEA_0
0 EIM clock cycles between beginning of access and OE assertion
0x1 : OEA_1
1 EIM clock cycles between beginning of access and OE assertion
0x2 : OEA_2
2 EIM clock cycles between beginning of access and OE assertion
0x7 : OEA_7
7 EIM clock cycles between beginning of access and OE assertion
End of enumeration elements list.
RADVN : ADV Negation
bits : 16 - 18 (3 bit)
access : read-write
RAL : Read ADV Low
bits : 19 - 19 (1 bit)
access : read-write
RADVA : ADV Assertion
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : RADVA_0
0 EIM clock cycles between beginning of access and ADV assertion
0x1 : RADVA_1
1 EIM clock cycles between beginning of access and ADV assertion
0x2 : RADVA_2
2 EIM clock cycles between beginning of access and ADV assertion
0x7 : RADVA_7
7 EIM clock cycles between beginning of access and ADV assertion
End of enumeration elements list.
RWSC : Read Wait State Control
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x1 : RWSC_1
RWSC value is 1
0x2 : RWSC_2
RWSC value is 2
0x3D : RWSC_61
RWSC value is 61
0x3E : RWSC_62
RWSC value is 62
0x3F : RWSC_63
RWSC value is 63
End of enumeration elements list.
Chip Select n Read Configuration Register 2
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBEN : Read BE Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : RBEN_0
0 EIM clock cycles between end of read access and BE negation
0x1 : RBEN_1
1 EIM clock cycles between end of read access and BE negation
0x2 : RBEN_2
2 EIM clock cycles between end of read access and BE negation
0x7 : RBEN_7
7 EIM clock cycles between end of read access and BE negation
End of enumeration elements list.
RBE : Read BE enable. This bit field determines if BE will be asserted during read access.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RBE_0
- BE are disabled during read access.
End of enumeration elements list.
RBEA : Read BE Assertion
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : RBEA_0
0 EIM clock cycles between beginning of read access and BE assertion
0x1 : RBEA_1
1 EIM clock cycles between beginning of read access and BE assertion
0x2 : RBEA_2
2 EIM clock cycles between beginning of read access and BE assertion
0x7 : RBEA_7
7 EIM clock cycles between beginning of read access and BE assertion
End of enumeration elements list.
RL : Read Latency
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : RL_0
Feedback clock loop delay is up to 1 cycle for BCD = 0 or 1.5 cycles for BCD != 0
0x1 : RL_1
Feedback clock loop delay is up to 2 cycles for BCD = 0 or 2.5 cycles for BCD != 0
0x2 : RL_2
Feedback clock loop delay is up to 3 cycles for BCD = 0 or 3.5 cycles for BCD != 0
0x3 : RL_3
Feedback clock loop delay is up to 4 cycles for BCD = 0 or 4.5 cycles for BCD != 0
End of enumeration elements list.
PAT : Page Access Time
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : PAT_0
Address width is 2 EIM clock cycles
0x1 : PAT_1
Address width is 3 EIM clock cycles
0x2 : PAT_2
Address width is 4 EIM clock cycles
0x3 : PAT_3
Address width is 5 EIM clock cycles
0x4 : PAT_4
Address width is 6 EIM clock cycles
0x5 : PAT_5
Address width is 7 EIM clock cycles
0x6 : PAT_6
Address width is 8 EIM clock cycles
0x7 : PAT_7
Address width is 9 EIM clock cycles
End of enumeration elements list.
APR : Asynchronous Page Read
bits : 15 - 15 (1 bit)
access : read-write
Chip Select n Write Configuration Register 1
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WCSN : Write CS Negation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : WCSN_0
0 EIM clock cycles between end of read access and CS negation
0x1 : WCSN_1
1 EIM clock cycles between end of read access and CS negation
0x2 : WCSN_2
2 EIM clock cycles between end of read access and CS negation
0x7 : WCSN_7
7 EIM clock cycles between end of read access and CS negation
End of enumeration elements list.
WCSA : Write CS Assertion
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : WCSA_0
0 EIM clock cycles between beginning of write access and CS assertion
0x1 : WCSA_1
1 EIM clock cycles between beginning of write access and CS assertion
0x2 : WCSA_2
2 EIM clock cycles between beginning of write access and CS assertion
0x7 : WCSA_7
7 EIMclock cycles between beginning of write access and CS assertion
End of enumeration elements list.
WEN : WE Negation
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : WEN_0
0 EIM clock cycles between beginning of access and WE assertion
0x1 : WEN_1
1 EIM clock cycles between beginning of access and WE assertion
0x2 : WEN_2
2 EIM clock cycles between beginning of access and WE assertion
0x7 : WEN_7
7 EIM clock cycles between beginning of access and WE assertion
End of enumeration elements list.
WEA : WE Assertion
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : WEA_0
0 EIM clock cycles between beginning of access and WE assertion
0x1 : WEA_1
1 EIM clock cycles between beginning of access and WE assertion
0x2 : WEA_2
2 EIM clock cycles between beginning of access and WE assertion
0x7 : WEA_7
7 EIMclock cycles between beginning of access and WE assertion
End of enumeration elements list.
WBEN : BE[3:0] Negation
bits : 12 - 14 (3 bit)
access : read-write
WBEA : BE Assertion
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0 : WBEA_0
0 EIM clock cycles between beginning of access and BE assertion
0x1 : WBEA_1
1 EIM clock cycles between beginning of access and BE assertion
0x2 : WBEA_2
2 EIM clock cycles between beginning of access and BE assertion
0x7 : WBEA_7
7 EIM clock cycles between beginning of access and BE assertion
End of enumeration elements list.
WADVN : ADV Negation
bits : 18 - 20 (3 bit)
access : read-write
WADVA : ADV Assertion
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0 : WADVA_0
0 EIM clock cycles between beginning of access and ADV assertion
0x1 : WADVA_1
1 EIM clock cycles between beginning of access and ADV assertion
0x2 : WADVA_2
2 EIM clock cycles between beginning of access and ADV assertion
0x7 : WADVA_7
7 EIM clock cycles between beginning of access and ADV assertion
End of enumeration elements list.
WWSC : Write Wait State Control
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x1 : WWSC_1
WWSC value is 1
0x2 : WWSC_2
WWSC value is 2
0x3 : WWSC_3
WWSC value is 3
0x3F : WWSC_63
WWSC value is 63
End of enumeration elements list.
WBED : Write Byte Enable Disable
bits : 30 - 30 (1 bit)
access : read-write
WAL : Write ADV Low
bits : 31 - 31 (1 bit)
access : read-write
Chip Select n General Configuration Register 1
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEN : CS Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CSEN_0
Chip select function is disabled; attempts to access an address mapped by this chip select results in an error respond and no assertion of the chip select output
0x1 : CSEN_1
Chip select is enabled, and is asserted when presented with a valid access.
End of enumeration elements list.
SWR : Synchronous Write Data
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SWR_0
write accesses are in Asynchronous mode
0x1 : SWR_1
write accesses are in Synchronous mode
End of enumeration elements list.
SRD : Synchronous Read Data
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRD_0
read accesses are in Asynchronous mode
0x1 : SRD_1
read accesses are in Synchronous mode
End of enumeration elements list.
MUM : Multiplexed Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : MUM_0
Multiplexed Mode disable
0x1 : MUM_1
Multiplexed Mode enable
End of enumeration elements list.
WFL : Write Fix Latency
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : WFL_0
the External device WAIT signal is being monitored, and it reflect the external data bus state
0x1 : WFL_1
the state of the External devices is determined internally (Fix latency mode only)
End of enumeration elements list.
RFL : Read Fix Latency
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : RFL_0
the External device WAIT signal is being monitored, and it reflect the external data bus state
0x1 : RFL_1
the state of the External devices is determined internally (Fix latency mode only)
End of enumeration elements list.
CRE : Configuration Register Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CRE_0
CRE signal use is disable
0x1 : CRE_1
CRE signal use is enable
End of enumeration elements list.
CREP : Configuration Register Enable Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : CREP_0
CRE signal is active low
0x1 : CREP_1
CRE signal is active high
End of enumeration elements list.
BL : Burst Length
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : BL_0
4 words Memory wrap burst length (read page burst size when APR = 1)
0x1 : BL_1
8 words Memory wrap burst length (read page burst size when APR = 1)
0x2 : BL_2
16 words Memory wrap burst length (read page burst size when APR = 1)
0x3 : BL_3
32 words Memory wrap burst length (read page burst size when APR = 1)
0x4 : BL_4
Continuous burst length (2 words read page burst size when APR = 1)
End of enumeration elements list.
WC : Write Continuous
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : WC_0
Write access burst length occurs according to BL value.
0x1 : WC_1
Write access burst length is continuous.
End of enumeration elements list.
BCD : Burst Clock Divisor
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : BCD_0
Divide EIM clock by 1
0x1 : BCD_1
Divide EIM clock by 2
0x2 : BCD_2
Divide EIM clock by 3
0x3 : BCD_3
Divide EIM clock by 4
End of enumeration elements list.
BCS : Burst Clock Start
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : BCS_0
0 EIM clock cycle additional delay
0x1 : BCS_1
1 EIM clock cycle additional delay
0x2 : BCS_2
2 EIM clock cycle additional delay
0x3 : BCS_3
3 EIM clock cycle additional delay
End of enumeration elements list.
DSZ : Data Port Size
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x1 : DSZ_1
16 bit port resides on DATA[15:0]
0x2 : DSZ_2
16 bit port resides on DATA[31:16]
0x3 : DSZ_3
32 bit port resides on DATA[31:0]
0x4 : DSZ_4
8 bit port resides on DATA[7:0]
0x5 : DSZ_5
8 bit port resides on DATA[15:8]
0x6 : DSZ_6
8 bit port resides on DATA[23:16]
0x7 : DSZ_7
8 bit port resides on DATA[31:24]
End of enumeration elements list.
SP : Supervisor Protect
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SP_0
User mode accesses are allowed in the memory range defined by chip select.
0x1 : SP_1
User mode accesses are prohibited. All attempts to access an address mapped by this chip select in User mode results in an error response and no assertion of the chip select output.
End of enumeration elements list.
CSREC : CS Recovery
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : CSREC_0
0 EIM clock cycles minimum width of CS, OE and WE signals (read async. mode only)
0x1 : CSREC_1
1 EIM clock cycles minimum width of CS, OE and WE signals
0x2 : CSREC_2
2 EIM clock cycles minimum width of CS, OE and WE signals
0x7 : CSREC_7
7 EIM clock cycles minimum width of CS, OE and WE signals
End of enumeration elements list.
AUS : Address UnShifted
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : AUS_0
Address shifted according to port size (DSZ config) (128 Mbyte maximum supported memory density).
0x1 : AUS_1
Address unshifted (32 Mbyte maximum supported memory density).
End of enumeration elements list.
GBC : Gap Between Chip Selects
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : GBC_0
minimum of 0 EIM clock cycles before next access from different chip select (async. mode only)
0x1 : GBC_1
minimum of 1 EIM clock cycles before next access from different chip select
0x2 : GBC_2
minimum of 2 EIM clock cycles before next access from different chip select
0x7 : GBC_7
minimum of 7 EIM clock cycles before next access from different chip select
End of enumeration elements list.
WP : Write Protect
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : WP_0
Writes are allowed in the memory range defined by chip.
0x1 : WP_1
Writes are prohibited. All attempts to write to an address mapped by this chip select result in a error response and no assertion of the chip select output.
End of enumeration elements list.
PSZ : Page Size
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : PSZ_0
8 words page size
0x1 : PSZ_1
16 words page size
0x2 : PSZ_2
32 words page size
0x3 : PSZ_3
64 words page size
0x4 : PSZ_4
128 words page size
0x5 : PSZ_5
256 words page size
0x6 : PSZ_6
512 words page size
0x7 : PSZ_7
1024 (1k) words page size
0x8 : PSZ_8
2048 (2k) words page size
0x9 : PSZ_9
- 1111 Reserved
End of enumeration elements list.
Chip Select n Write Configuration Register 2
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WBCDD : Write Burst Clock Divisor Decrement
bits : 0 - 0 (1 bit)
access : read-write
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