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OCOTP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8F4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

TIMING

TIMING2

DATA

READ_CTRL

CTRL_SET

READ_FUSE_DATA

LOCK

CFG0

CFG1

CFG2

CFG3

CFG4

CFG5

CFG6

MEM0

MEM1

MEM2

MEM3

MEM4

ANA0

ANA1

ANA2

SW_STICKY

OTPMK0

OTPMK1

OTPMK2

OTPMK3

OTPMK4

OTPMK5

OTPMK6

OTPMK7

SRK0

SRK1

SRK2

SRK3

SRK4

SRK5

SRK6

SRK7

SCS

SJC_RESP0

SJC_RESP1

MAC0

MAC1

SCS_SET

MAC

CRC

GP1

GP2

SCS_CLR

SW_GP0

SW_GP1

SW_GP2

SW_GP3

SCS_TOG

SW_GP4

MISC_CONF

FIELD_RETURN

SRK_REVOKE

CRC_ADDR

CTRL_CLR

CRC_VALUE

ROM_PATCH0

ROM_PATCH1

ROM_PATCH2

ROM_PATCH3

ROM_PATCH4

ROM_PATCH5

ROM_PATCH6

ROM_PATCH7

GP3_0

GP3_1

GP3_2

GP3_3

GP3_4

GP4_0

GP4_1

GP4_2

VERSION

CTRL_TOG


CTRL

OTP Controller Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RSVD0 BUSY ERROR RELOAD_SHADOWS CRC_TEST CRC_FAIL RSVD1 WR_UNLOCK

ADDR : OTP write and read access address register
bits : 0 - 5 (6 bit)
access : read-write

RSVD0 : Reserved
bits : 6 - 7 (2 bit)
access : read-only

BUSY : OTP controller status bit
bits : 8 - 8 (1 bit)
access : read-only

ERROR : Set by the controller when an access to a locked region(OTP or shadow register) is requested
bits : 9 - 9 (1 bit)
access : read-write

RELOAD_SHADOWS : Set to force re-loading the shadow registers (HW/SW capability and LOCK)
bits : 10 - 10 (1 bit)
access : read-write

CRC_TEST : Set to calculate CRC according to start address and end address in CRC_ADDR register
bits : 11 - 11 (1 bit)
access : read-write

CRC_FAIL : Set by controller when calculated CRC value is not equal to appointed CRC fuse word
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : Reserved
bits : 13 - 15 (3 bit)
access : read-only

WR_UNLOCK : Write 0x3E77 to enable OTP write accesses
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0x3E77 : KEY

Key needed to unlock HW_OCOTP_DATA register.

End of enumeration elements list.


TIMING

OTP Controller Timing Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMING TIMING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STROBE_PROG RELAX STROBE_READ WAIT RSRVD0

STROBE_PROG : This count value specifies the strobe period in one time write OTP
bits : 0 - 11 (12 bit)
access : read-write

RELAX : This count value specifies the time to add to all default timing parameters other than the Tpgm and Trd
bits : 12 - 15 (4 bit)
access : read-write

STROBE_READ : This count value specifies the strobe period in one time read OTP
bits : 16 - 21 (6 bit)
access : read-write

WAIT : This count value specifies time interval between auto read and write access in one time program
bits : 22 - 27 (6 bit)
access : read-write

RSRVD0 : These bits always read back zero.
bits : 28 - 31 (4 bit)
access : read-only


TIMING2

OTP Controller Timing Register 2
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMING2 TIMING2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RELAX_PROG RELAX_READ RELAX1

RELAX_PROG : This count value specifies the time to add to write OTP for complement address enable time.
bits : 0 - 11 (12 bit)
access : read-write

RELAX_READ : This count value specifies the time to add to read OTP for complement address enable cycle time.
bits : 16 - 21 (6 bit)
access : read-write

RELAX1 : Not used, preserved
bits : 22 - 28 (7 bit)
access : read-write


DATA

OTP Controller Write Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Used to initiate a write to OTP
bits : 0 - 31 (32 bit)
access : read-write


READ_CTRL

OTP Controller Write Data Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READ_CTRL READ_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_FUSE RSVD0

READ_FUSE : Used to initiate a read to OTP
bits : 0 - 0 (1 bit)
access : read-write

RSVD0 : Reserved
bits : 1 - 31 (31 bit)
access : read-only


CTRL_SET

OTP Controller Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_SET CTRL_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RSVD0 BUSY ERROR RELOAD_SHADOWS CRC_TEST CRC_FAIL RSVD1 WR_UNLOCK

ADDR : OTP write and read access address register
bits : 0 - 5 (6 bit)
access : read-write

RSVD0 : Reserved
bits : 6 - 7 (2 bit)
access : read-only

BUSY : OTP controller status bit
bits : 8 - 8 (1 bit)
access : read-only

ERROR : Set by the controller when an access to a locked region(OTP or shadow register) is requested
bits : 9 - 9 (1 bit)
access : read-write

RELOAD_SHADOWS : Set to force re-loading the shadow registers (HW/SW capability and LOCK)
bits : 10 - 10 (1 bit)
access : read-write

CRC_TEST : Set to calculate CRC according to start address and end address in CRC_ADDR register
bits : 11 - 11 (1 bit)
access : read-write

CRC_FAIL : Set by controller when calculated CRC value is not equal to appointed CRC fuse word
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : Reserved
bits : 13 - 15 (3 bit)
access : read-only

WR_UNLOCK : Write 0x3E77 to enable OTP write accesses
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0x3E77 : KEY

Key needed to unlock HW_OCOTP_DATA register.

End of enumeration elements list.


READ_FUSE_DATA

OTP Controller Read Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READ_FUSE_DATA READ_FUSE_DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : The data read from OTP
bits : 0 - 31 (32 bit)
access : read-write


LOCK

Value of OTP Bank0 Word0 (Lock controls)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TESTER BOOT_CFG MEM_TRIM SJC_RESP RSVD0 MAC_ADDR GP1 GP2 SRK GP3 SW_GP OTPMK ANALOG OTPMK_CRC ROM_PATCH MISC_CONF GP4 PIN GP4_RLOCK GP3_RLOCK

TESTER : Status of shadow register and OTP write lock for tester region
bits : 0 - 1 (2 bit)
access : read-only

BOOT_CFG : Status of shadow register and OTP write lock for boot_cfg region
bits : 2 - 3 (2 bit)
access : read-only

MEM_TRIM : Status of shadow register and OTP write lock for mem_trim region
bits : 4 - 5 (2 bit)
access : read-only

SJC_RESP : Status of shadow register read and write, OTP read and write lock for sjc_resp region
bits : 6 - 6 (1 bit)
access : read-only

RSVD0 : Reserved
bits : 7 - 7 (1 bit)
access : read-only

MAC_ADDR : Status of shadow register and OTP write lock for mac_addr region
bits : 8 - 9 (2 bit)
access : read-only

GP1 : Status of shadow register and OTP write lock for gp2 region
bits : 10 - 11 (2 bit)
access : read-only

GP2 : Status of shadow register and OTP write lock for gp2 region
bits : 12 - 13 (2 bit)
access : read-only

SRK : Status of shadow register and OTP write lock for srk region
bits : 14 - 14 (1 bit)
access : read-only

GP3 : Status of shadow register and OTP write lock for GP3 region
bits : 15 - 15 (1 bit)
access : read-only

SW_GP : Status of shadow register and OTP write lock for SW_GP region
bits : 16 - 16 (1 bit)
access : read-only

OTPMK : Status of shadow register and OTP write lock for OTPMK region
bits : 17 - 17 (1 bit)
access : read-only

ANALOG : Status of shadow register and OTP write lock for analog region
bits : 18 - 19 (2 bit)
access : read-only

OTPMK_CRC : Status of shadow register and OTP write lock for otpmk crc region
bits : 20 - 20 (1 bit)
access : read-only

ROM_PATCH : Status of shadow register and OTP write lock for rom_patch region
bits : 21 - 21 (1 bit)
access : read-only

MISC_CONF : Status of shadow register and OTP write lock for misc_conf region
bits : 22 - 22 (1 bit)
access : read-only

GP4 : Status of shadow register and OTP write lock for GP4 region
bits : 23 - 23 (1 bit)
access : read-only

PIN : Status of Pin access lock bit. When set, pin access is disabled.
bits : 25 - 25 (1 bit)
access : read-only

GP4_RLOCK : Status of shadow register and OTP read lock for GP4 region
bits : 30 - 30 (1 bit)
access : read-write

GP3_RLOCK : Status of shadow register and OTP read lock for GP3 region
bits : 31 - 31 (1 bit)
access : read-only


CFG0

Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.)
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG0 CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : This register contains 32 bits of the Unique ID and SJC_CHALLENGE field
bits : 0 - 31 (32 bit)
access : read-write


CFG1

Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.)
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG1 CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : This register contains 32 bits of the Unique ID and SJC_CHALLENGE field
bits : 0 - 31 (32 bit)
access : read-write


CFG2

Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.)
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG2 CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 0, word 3 (ADDR = 0x03)
bits : 0 - 31 (32 bit)
access : read-write


CFG3

Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.)
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG3 CFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 0, word 4 (ADDR = 0x04)
bits : 0 - 31 (32 bit)
access : read-write


CFG4

Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.)
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG4 CFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 0, word 5 (ADDR = 0x05)
bits : 0 - 31 (32 bit)
access : read-write


CFG5

Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.)
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG5 CFG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 0, word 6 (ADDR = 0x06)
bits : 0 - 31 (32 bit)
access : read-write


CFG6

Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.)
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG6 CFG6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 0, word 7 (ADDR = 0x07)
bits : 0 - 31 (32 bit)
access : read-write


MEM0

Value of OTP Bank1 Word0 (Memory Related Info.)
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM0 MEM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP bank 1, word 0 (ADDR = 0x08)
bits : 0 - 31 (32 bit)
access : read-write


MEM1

Value of OTP Bank1 Word1 (Memory Related Info.)
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM1 MEM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP bank 1, word 1 (ADDR = 0x09)
bits : 0 - 31 (32 bit)
access : read-write


MEM2

Value of OTP Bank1 Word2 (Memory Related Info.)
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM2 MEM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP bank 1, word 2 (ADDR = 0x0A)
bits : 0 - 31 (32 bit)
access : read-write


MEM3

Value of OTP Bank1 Word3 (Memory Related Info.)
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM3 MEM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP bank 1, word 3 (ADDR = 0x0B)
bits : 0 - 31 (32 bit)
access : read-write


MEM4

Value of OTP Bank1 Word4 (Memory Related Info.)
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM4 MEM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP bank 1, word 4 (ADDR = 0x0C)
bits : 0 - 31 (32 bit)
access : read-write


ANA0

Value of OTP Bank1 Word5 (Memory Related Info.)
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANA0 ANA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP bank 1, word 5 (ADDR = 0x0D)
bits : 0 - 31 (32 bit)
access : read-write


ANA1

Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.)
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANA1 ANA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP bank 1, word 6 (ADDR = 0x0E)
bits : 0 - 31 (32 bit)
access : read-write


ANA2

Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.)
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANA2 ANA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP bank 1, word 7 (ADDR = 0x0F)
bits : 0 - 31 (32 bit)
access : read-write


SW_STICKY

Sticky bit Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_STICKY SW_STICKY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRK_REVOKE_LOCK FIELD_RETURN_LOCK RSVD0

SRK_REVOKE_LOCK : Shadow register write and OTP write lock for SRK_REVOKE region
bits : 1 - 1 (1 bit)
access : read-write

FIELD_RETURN_LOCK : Shadow register write and OTP write lock for FIELD_RETURN region
bits : 2 - 2 (1 bit)
access : read-write

RSVD0 : Reserved
bits : 5 - 31 (27 bit)
access : read-only


OTPMK0

Value of OTP Bank2 Word0 (OTPMK Key)
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK0 OTPMK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 0 (ADDR = 0x10))
bits : 0 - 31 (32 bit)
access : read-write


OTPMK1

Value of OTP Bank2 Word1 (OTPMK Key)
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK1 OTPMK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 1 (ADDR = 0x11))
bits : 0 - 31 (32 bit)
access : read-write


OTPMK2

Value of OTP Bank2 Word2 (OTPMK Key)
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK2 OTPMK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 2 (ADDR = 0x12))
bits : 0 - 31 (32 bit)
access : read-write


OTPMK3

Value of OTP Bank2 Word3 (OTPMK Key)
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK3 OTPMK3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 3 (ADDR = 0x13))
bits : 0 - 31 (32 bit)
access : read-write


OTPMK4

Value of OTP Bank2 Word4 (OTPMK Key)
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK4 OTPMK4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 4 (ADDR = 0x14))
bits : 0 - 31 (32 bit)
access : read-write


OTPMK5

Value of OTP Bank2 Word5 (OTPMK Key)
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK5 OTPMK5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 4 (ADDR = 0x14))
bits : 0 - 31 (32 bit)
access : read-write


OTPMK6

Value of OTP Bank2 Word6 (OTPMK Key)
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK6 OTPMK6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 6 (ADDR = 0x16))
bits : 0 - 31 (32 bit)
access : read-write


OTPMK7

Value of OTP Bank2 Word7 (OTPMK Key)
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK7 OTPMK7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 7 (ADDR = 0x17))
bits : 0 - 31 (32 bit)
access : read-write


SRK0

Shadow Register for OTP Bank3 Word0 (SRK Hash)
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK0 SRK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the hash of the Super Root Key word0 (Copy of OTP Bank 3, word 0 (ADDR = 0x18))
bits : 0 - 31 (32 bit)
access : read-write


SRK1

Shadow Register for OTP Bank3 Word1 (SRK Hash)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK1 SRK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the hash of the Super Root Key word1 (Copy of OTP Bank 3, word 1 (ADDR = 0x19))
bits : 0 - 31 (32 bit)
access : read-write


SRK2

Shadow Register for OTP Bank3 Word2 (SRK Hash)
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK2 SRK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the hash of the Super Root Key word2 (Copy of OTP Bank 3, word 2 (ADDR = 0x1A))
bits : 0 - 31 (32 bit)
access : read-write


SRK3

Shadow Register for OTP Bank3 Word3 (SRK Hash)
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK3 SRK3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the hash of the Super Root Key word3 (Copy of OTP Bank 3, word 3 (ADDR = 0x1B))
bits : 0 - 31 (32 bit)
access : read-write


SRK4

Shadow Register for OTP Bank3 Word4 (SRK Hash)
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK4 SRK4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the hash of the Super Root Key word4 (Copy of OTP Bank 3, word 4 (ADDR = 0x1C))
bits : 0 - 31 (32 bit)
access : read-write


SRK5

Shadow Register for OTP Bank3 Word5 (SRK Hash)
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK5 SRK5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the hash of the Super Root Key word5 (Copy of OTP Bank 3, word 5 (ADDR = 0x1D))
bits : 0 - 31 (32 bit)
access : read-write


SRK6

Shadow Register for OTP Bank3 Word6 (SRK Hash)
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK6 SRK6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the hash of the Super Root Key word6 (Copy of OTP Bank 3, word 6 (ADDR = 0x1E))
bits : 0 - 31 (32 bit)
access : read-write


SRK7

Shadow Register for OTP Bank3 Word7 (SRK Hash)
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK7 SRK7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the hash of the Super Root Key word7 (Copy of OTP Bank 3, word 7 (ADDR = 0x1F))
bits : 0 - 31 (32 bit)
access : read-write


SCS

Software Controllable Signals Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCS SCS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAB_JDE SPARE LOCK

HAB_JDE : HAB JTAG Debug Enable
bits : 0 - 0 (1 bit)
access : read-write

SPARE : Unallocated read/write bits for implementation specific software use.
bits : 1 - 30 (30 bit)
access : read-write

LOCK : When set, all of the bits in this register are locked and can not be changed through SW programming
bits : 31 - 31 (1 bit)
access : read-write


SJC_RESP0

Value of OTP Bank4 Word0 (Secure JTAG Response Field)
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SJC_RESP0 SJC_RESP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the SJC_RESP Key word0 (Copy of OTP Bank 4, word 0 (ADDR = 0x20))
bits : 0 - 31 (32 bit)
access : read-write


SJC_RESP1

Value of OTP Bank4 Word1 (Secure JTAG Response Field)
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SJC_RESP1 SJC_RESP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the SJC_RESP Key word1 (Copy of OTP Bank 4, word 1 (ADDR = 0x21))
bits : 0 - 31 (32 bit)
access : read-write


MAC0

Value of OTP Bank4 Word2 (MAC Address)
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC0 MAC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 4, word 2 (ADDR = 0x22).
bits : 0 - 31 (32 bit)
access : read-write


MAC1

Value of OTP Bank4 Word3 (MAC Address)
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC1 MAC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 4, word 3 (ADDR = 0x23).
bits : 0 - 31 (32 bit)
access : read-write


SCS_SET

Software Controllable Signals Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCS_SET SCS_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAB_JDE SPARE LOCK

HAB_JDE : HAB JTAG Debug Enable
bits : 0 - 0 (1 bit)
access : read-write

SPARE : Unallocated read/write bits for implementation specific software use.
bits : 1 - 30 (30 bit)
access : read-write

LOCK : When set, all of the bits in this register are locked and can not be changed through SW programming
bits : 31 - 31 (1 bit)
access : read-write


MAC

Value of OTP Bank4 Word4 (MAC Address) (OCOTP_RESERVED)
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC MAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 4, word 4 (ADDR = 0x24).
bits : 0 - 31 (32 bit)
access : read-write


CRC

Value of OTP Bank4 Word5 (CRC Key)
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC CRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 4, word 5 (ADDR = 0x25).
bits : 0 - 31 (32 bit)
access : read-write


GP1

Value of OTP Bank4 Word6 (General Purpose Customer Defined Info)
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP1 GP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 4, word 6 (ADDR = 0x26).
bits : 0 - 31 (32 bit)
access : read-write


GP2

Value of OTP Bank4 Word7 (General Purpose Customer Defined Info)
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP2 GP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 4, word 7 (ADDR = 0x27).
bits : 0 - 31 (32 bit)
access : read-write


SCS_CLR

Software Controllable Signals Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCS_CLR SCS_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAB_JDE SPARE LOCK

HAB_JDE : HAB JTAG Debug Enable
bits : 0 - 0 (1 bit)
access : read-write

SPARE : Unallocated read/write bits for implementation specific software use.
bits : 1 - 30 (30 bit)
access : read-write

LOCK : When set, all of the bits in this register are locked and can not be changed through SW programming
bits : 31 - 31 (1 bit)
access : read-write


SW_GP0

Value of OTP Bank5 Word0 (SW GP)
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_GP0 SW_GP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 5, word 0 (ADDR = 0x28).
bits : 0 - 31 (32 bit)
access : read-write


SW_GP1

Value of OTP Bank5 Word1 (SW GP)
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_GP1 SW_GP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 5, word 1 (ADDR = 0x29).
bits : 0 - 31 (32 bit)
access : read-write


SW_GP2

Value of OTP Bank5 Word2 (SW GP)
address_offset : 0x6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_GP2 SW_GP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 5, word 2 (ADDR = 0x2a).
bits : 0 - 31 (32 bit)
access : read-write


SW_GP3

Value of OTP Bank5 Word3 (SW GP)
address_offset : 0x6B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_GP3 SW_GP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 5, word 3 (ADDR = 0x2b).
bits : 0 - 31 (32 bit)
access : read-write


SCS_TOG

Software Controllable Signals Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCS_TOG SCS_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAB_JDE SPARE LOCK

HAB_JDE : HAB JTAG Debug Enable
bits : 0 - 0 (1 bit)
access : read-write

SPARE : Unallocated read/write bits for implementation specific software use.
bits : 1 - 30 (30 bit)
access : read-write

LOCK : When set, all of the bits in this register are locked and can not be changed through SW programming
bits : 31 - 31 (1 bit)
access : read-write


SW_GP4

Value of OTP Bank5 Word4 (SW GP)
address_offset : 0x6C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_GP4 SW_GP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 5, word 4 (ADDR = 0x2c).
bits : 0 - 31 (32 bit)
access : read-write


MISC_CONF

Value of OTP Bank5 Word5 (Misc Conf)
address_offset : 0x6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MISC_CONF MISC_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 5, word 5 (ADDR = 0x2d).
bits : 0 - 31 (32 bit)
access : read-write


FIELD_RETURN

Value of OTP Bank5 Word6 (Field Return)
address_offset : 0x6E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIELD_RETURN FIELD_RETURN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 5, word 6 (ADDR = 0x2e).
bits : 0 - 31 (32 bit)
access : read-write


SRK_REVOKE

Value of OTP Bank5 Word7 (SRK Revoke)
address_offset : 0x6F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK_REVOKE SRK_REVOKE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 5, word 7 (ADDR = 0x2f).
bits : 0 - 31 (32 bit)
access : read-write


CRC_ADDR

OTP Controller CRC test address
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC_ADDR CRC_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_START_ADDR DATA_END_ADDR CRC_ADDR OTPMK_CRC RSVD0

DATA_START_ADDR : End address of fuse location for CRC calculation
bits : 0 - 7 (8 bit)
access : read-write

DATA_END_ADDR : Start address of fuse location for CRC calculation
bits : 8 - 15 (8 bit)
access : read-write

CRC_ADDR : Address of 32-bit CRC result for comparing
bits : 16 - 18 (3 bit)
access : read-write

OTPMK_CRC : Enable bit for CRC32 calculation address When OTPMK_CRC_ADDR_OTPMK_CRC bit sets to 1, calculation address sets to OTPMK_CRC (recommend)
bits : 19 - 19 (1 bit)
access : read-write

RSVD0 : Reserved
bits : 20 - 31 (12 bit)
access : read-only


CTRL_CLR

OTP Controller Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_CLR CTRL_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RSVD0 BUSY ERROR RELOAD_SHADOWS CRC_TEST CRC_FAIL RSVD1 WR_UNLOCK

ADDR : OTP write and read access address register
bits : 0 - 5 (6 bit)
access : read-write

RSVD0 : Reserved
bits : 6 - 7 (2 bit)
access : read-only

BUSY : OTP controller status bit
bits : 8 - 8 (1 bit)
access : read-only

ERROR : Set by the controller when an access to a locked region(OTP or shadow register) is requested
bits : 9 - 9 (1 bit)
access : read-write

RELOAD_SHADOWS : Set to force re-loading the shadow registers (HW/SW capability and LOCK)
bits : 10 - 10 (1 bit)
access : read-write

CRC_TEST : Set to calculate CRC according to start address and end address in CRC_ADDR register
bits : 11 - 11 (1 bit)
access : read-write

CRC_FAIL : Set by controller when calculated CRC value is not equal to appointed CRC fuse word
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : Reserved
bits : 13 - 15 (3 bit)
access : read-only

WR_UNLOCK : Write 0x3E77 to enable OTP write accesses
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0x3E77 : KEY

Key needed to unlock HW_OCOTP_DATA register.

End of enumeration elements list.


CRC_VALUE

OTP Controller CRC Value Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC_VALUE CRC_VALUE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : The crc32 value based on CRC_ADDR
bits : 0 - 31 (32 bit)
access : read-write


ROM_PATCH0

Value of OTP Bank6 Word0 (ROM Patch)
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROM_PATCH0 ROM_PATCH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 6, word 0 (ADDR = 0x30).
bits : 0 - 31 (32 bit)
access : read-write


ROM_PATCH1

Value of OTP Bank6 Word1 (ROM Patch)
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROM_PATCH1 ROM_PATCH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 6, word 1 (ADDR = 0x31).
bits : 0 - 31 (32 bit)
access : read-write


ROM_PATCH2

Value of OTP Bank6 Word2 (ROM Patch)
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROM_PATCH2 ROM_PATCH2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 6, word 2 (ADDR = 0x32).
bits : 0 - 31 (32 bit)
access : read-write


ROM_PATCH3

Value of OTP Bank6 Word3 (ROM Patch)
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROM_PATCH3 ROM_PATCH3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 6, word 3 (ADDR = 0x33).
bits : 0 - 31 (32 bit)
access : read-write


ROM_PATCH4

Value of OTP Bank6 Word4 (ROM Patch)
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROM_PATCH4 ROM_PATCH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 6, word 4 (ADDR = 0x34).
bits : 0 - 31 (32 bit)
access : read-write


ROM_PATCH5

Value of OTP Bank6 Word5 (ROM Patch)
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROM_PATCH5 ROM_PATCH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 6, word 5 (ADDR = 0x35).
bits : 0 - 31 (32 bit)
access : read-write


ROM_PATCH6

Value of OTP Bank6 Word6 (ROM Patch)
address_offset : 0x860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROM_PATCH6 ROM_PATCH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 6, word 6 (ADDR = 0x36).
bits : 0 - 31 (32 bit)
access : read-write


ROM_PATCH7

Value of OTP Bank6 Word7 (ROM Patch)
address_offset : 0x870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROM_PATCH7 ROM_PATCH7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 6, word 7 (ADDR = 0x37).
bits : 0 - 31 (32 bit)
access : read-write


GP3_0

Value of OTP Bank7 Word0 (General Purpose Customer Defined Info)
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP3_0 GP3_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 8, word 0 (ADDR = 0x40).
bits : 0 - 31 (32 bit)
access : read-write


GP3_1

Value of OTP Bank7 Word1 (General Purpose Customer Defined Info)
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP3_1 GP3_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 8, word 1 (ADDR = 0x41).
bits : 0 - 31 (32 bit)
access : read-write


GP3_2

Value of OTP Bank7 Word2 (General Purpose Customer Defined Info)
address_offset : 0x8A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP3_2 GP3_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 8, word 2 (ADDR = 0x42).
bits : 0 - 31 (32 bit)
access : read-write


GP3_3

Value of OTP Bank7 Word3 (General Purpose Customer Defined Info)
address_offset : 0x8B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP3_3 GP3_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 8, word 3 (ADDR = 0x43).
bits : 0 - 31 (32 bit)
access : read-write


GP3_4

Value of OTP Bank8 Word4 (General Purpose Customer Defined Info)
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP3_4 GP3_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 8, word 4 (ADDR = 0x44).
bits : 0 - 31 (32 bit)
access : read-write


GP4_0

Value of OTP Bank7 Word5 (General Purpose Customer Defined Info)
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP4_0 GP4_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 8, word 5 (ADDR = 0x45).
bits : 0 - 31 (32 bit)
access : read-write


GP4_1

Value of OTP Bank7 Word6 (General Purpose Customer Defined Info)
address_offset : 0x8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP4_1 GP4_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 8, word 6 (ADDR = 0x46).
bits : 0 - 31 (32 bit)
access : read-write


GP4_2

Value of OTP Bank7 Word7 (General Purpose Customer Defined Info)
address_offset : 0x8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP4_2 GP4_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Reflects value of OTP Bank 8, word 7 (ADDR = 0x47).
bits : 0 - 31 (32 bit)
access : read-write


VERSION

OTP Controller Version Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STEP MINOR MAJOR

STEP : Fixed read-only value reflecting the stepping of the RTL version.
bits : 0 - 15 (16 bit)
access : read-only

MINOR : Fixed read-only value reflecting the MINOR field of the RTL version.
bits : 16 - 23 (8 bit)
access : read-only

MAJOR : Fixed read-only value reflecting the MAJOR field of the RTL version.
bits : 24 - 31 (8 bit)
access : read-only


CTRL_TOG

OTP Controller Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_TOG CTRL_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RSVD0 BUSY ERROR RELOAD_SHADOWS CRC_TEST CRC_FAIL RSVD1 WR_UNLOCK

ADDR : OTP write and read access address register
bits : 0 - 5 (6 bit)
access : read-write

RSVD0 : Reserved
bits : 6 - 7 (2 bit)
access : read-only

BUSY : OTP controller status bit
bits : 8 - 8 (1 bit)
access : read-only

ERROR : Set by the controller when an access to a locked region(OTP or shadow register) is requested
bits : 9 - 9 (1 bit)
access : read-write

RELOAD_SHADOWS : Set to force re-loading the shadow registers (HW/SW capability and LOCK)
bits : 10 - 10 (1 bit)
access : read-write

CRC_TEST : Set to calculate CRC according to start address and end address in CRC_ADDR register
bits : 11 - 11 (1 bit)
access : read-write

CRC_FAIL : Set by controller when calculated CRC value is not equal to appointed CRC fuse word
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : Reserved
bits : 13 - 15 (3 bit)
access : read-only

WR_UNLOCK : Write 0x3E77 to enable OTP write accesses
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0x3E77 : KEY

Key needed to unlock HW_OCOTP_DATA register.

End of enumeration elements list.



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