Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC00 byte (0x0)
mem_usage : registers
protection : not protected
SNVS_HP Lock register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MC_SL : Monotonic Counter Soft Lock When set, it prevents any writes (increments) to the MC registers and the MC_ENV bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : MC_SL_0
Write access (increment) is allowed.
0x1 : MC_SL_1
Write access (increment) is not allowed.
End of enumeration elements list.
GPR_SL : General-Purpose Register Soft Lock When set, it prevents any writes to the GPR
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : GPR_SL_0
Write access is allowed.
0x1 : GPR_SL_1
Write access is not allowed.
End of enumeration elements list.
SNVS_HP Status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTN : Value of the BTN input
bits : 6 - 6 (1 bit)
access : read-only
BI : Button interrupt. The ipi_snvs_btn_int_b signal was asserted.
bits : 7 - 7 (1 bit)
access : read-write
SNVS_HP Real-Time Counter MSB Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC : HP Real-Time Counter Most significant 32 bits
bits : 0 - 31 (32 bit)
access : read-write
SNVS_HP Real-Time Counter LSB Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC : HP Real-Time Counter Least significant 32 bits
bits : 0 - 31 (32 bit)
access : read-write
SNVS_HP Time Alarm MSB Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPTA : HP Time Alarm Most significant 15 bits
bits : 0 - 14 (15 bit)
access : read-write
SNVS_HP Time Alarm LSB Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPTA : HP Time Alarm The least significant bits
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP Lock Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MC_HL : Monotonic Counter Hard Lock When set, it blocks any writes (increments) to the MC registers and the MC_ENV bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : MC_HL_0
Write access (increment) is allowed.
0x1 : MC_HL_1
Write access (increment) is not allowed.
End of enumeration elements list.
GPR_HL : General-Purpose Register Hard Lock When set, it blocks any writes to the GPR
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : GPR_HL_0
Write access is allowed.
0x1 : GPR_HL_1
Write access is not allowed.
End of enumeration elements list.
SNVS_LP Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MC_ENV : Monotonic Counter Enable and Valid When set, the MC can be incremented (by a write transaction to the LPSMCMR or LPSMCLR)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : MC_ENV_0
MC is disabled or invalid.
0x1 : MC_ENV_1
MC is enabled and valid.
End of enumeration elements list.
DP_EN : Dumb PMIC Enabled When set, the software can control the system power
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DP_EN_0
Smart PMIC is enabled.
0x1 : DP_EN_1
Dumb PMIC is enabled.
End of enumeration elements list.
TOP : Turn off System Power Asserting this bit causes a signal to be sent to the power management IC to turn the system power off
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : TOP_0
Leave the system power on.
0x1 : TOP_1
Turn the system power off.
End of enumeration elements list.
PWR_GLITCH_EN : By default, the detection of a power glitch does not cause the pmic_en_b signal to be asserted
bits : 7 - 7 (1 bit)
access : read-write
BTN_PRESS_TIME : Button press timeout values for the PMIC logic
bits : 16 - 17 (2 bit)
access : read-write
DEBOUNCE : This field configures the amount of debounce time for the BTN input signal
bits : 18 - 19 (2 bit)
access : read-write
ON_TIME : The ON_TIME field is used to configure the period of time after the BTN is asserted before the pmic_en_b is asserted to turn on the SoC power
bits : 20 - 21 (2 bit)
access : read-write
PK_EN : PMIC On Request Enable
bits : 22 - 22 (1 bit)
access : read-write
PK_OVERRIDE : PMIC On Request Override
bits : 23 - 23 (1 bit)
access : read-write
SNVS_HP Command register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LP_SWR : LP Software Reset When set, it resets the SNVS_LP section
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
0 : LP_SWR_0
No action
0x1 : LP_SWR_1
Reset LP section
End of enumeration elements list.
LP_SWR_DIS : LP Software Reset Disable When set, it disables the LP software reset
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : LP_SWR_DIS_0
LP software reset is enabled.
0x1 : LP_SWR_DIS_1
LP software reset is disabled.
End of enumeration elements list.
NPSWA_EN : Non-Privileged Software Access Enable When set, it allows non-privileged software to access all SNVS registers, including those that are privileged-software read/write access only
bits : 31 - 31 (1 bit)
access : read-write
SNVS_LP Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCR : Monotonic Counter Rollover
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : MCR_0
MC did not reach its maximum value.
0x1 : MCR_1
MC reached its maximum value.
End of enumeration elements list.
EO : Emergency Off This bit is set when a power off is requested.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : EO_0
Emergency off is not detected.
0x1 : EO_1
Emergency off is detected.
End of enumeration elements list.
SPO : Set Power Off The SPO bit is set when the set_pwr_off_irq interrupt is triggered, which happens when the software writes a 1 to the TOP bit in the LPCR or when the power button is pressed longer than the configured debounce time
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SPO_0
Emergency off is not detected.
0x1 : SPO_1
Emergency off is detected.
End of enumeration elements list.
SNVS_LP Secure Monotonic Counter MSB Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MON_COUNTER : Monotonic Counter Most-Significant 16 Bits The MC is incremented by one when: A write transaction to the LPSMCMR register or the LPSMCLR register is detected
bits : 0 - 15 (16 bit)
access : read-write
MC_ERA_BITS : Monotonic Counter Era Bits These bits are the inputs to the module and are typically connected to the fuses
bits : 16 - 31 (16 bit)
access : read-write
SNVS_LP Secure Monotonic Counter LSB Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MON_COUNTER : Monotonic Counter bits The MC is incremented by one when: A write transaction to the LPSMCMR register or the LPSMCLR register is detected
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP General-Purpose Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR : General-Purpose Register When the GPR_SL or GPR_HL bit is set, the register can't be programmed.
bits : 0 - 31 (32 bit)
access : read-write
SNVS_HP Control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC_EN : HP Real-Time Counter Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RTC_EN_0
RTC is disabled.
0x1 : RTC_EN_1
RTC is enabled.
End of enumeration elements list.
HPTA_EN : HP Time Alarm Enable When set, the time alarm interrupt is generated if the value in the HP time alarm registers is equal to the value of the HP real-time counter
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : HPTA_EN_0
HP time alarm interrupt is disabled.
0x1 : HPTA_EN_1
HP time alarm interrupt is enabled.
End of enumeration elements list.
PI_EN : HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP real-time counter is enabled
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PI_EN_0
HP periodic interrupt is disabled.
0x1 : PI_EN_1
HP periodic interrupt is enabled.
End of enumeration elements list.
PI_FREQ : Periodic Interrupt Frequency Defines the frequency of the periodic interrupt
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : PI_FREQ_0
- Bit 0 of the RTC is selected as the source of the periodic interrupt.
0x1 : PI_FREQ_1
- Bit 1 of the RTC is selected as the source of the periodic interrupt.
0x2 : PI_FREQ_2
- Bit 2 of the RTC is selected as the source of the periodic interrupt.
0x3 : PI_FREQ_3
- Bit 3 of the RTC is selected as the source of the periodic interrupt.
0x4 : PI_FREQ_4
- Bit 4 of the RTC is selected as the source of the periodic interrupt.
0x5 : PI_FREQ_5
- Bit 5 of the RTC is selected as the source of the periodic interrupt.
0x6 : PI_FREQ_6
- Bit 6 of the RTC is selected as the source of the periodic interrupt.
0x7 : PI_FREQ_7
- Bit 7 of the RTC is selected as the source of the periodic interrupt.
0x8 : PI_FREQ_8
- Bit 8 of the RTC is selected as the source of the periodic interrupt.
0x9 : PI_FREQ_9
- Bit 9 of the RTC is selected as the source of the periodic interrupt.
0xA : PI_FREQ_10
- Bit 10 of the RTC is selected as the source of the periodic interrupt.
0xB : PI_FREQ_11
- Bit 11 of the RTC is selected as the source of the periodic interrupt.
0xC : PI_FREQ_12
- Bit 12 of the RTC is selected as the source of the periodic interrupt.
0xD : PI_FREQ_13
- Bit 13 of the RTC is selected as the source of the periodic interrupt.
0xE : PI_FREQ_14
- Bit 14 of the RTC is selected as the source of the periodic interrupt.
0xF : PI_FREQ_15
- Bit 15 of the RTC is selected as the source of the periodic interrupt.
End of enumeration elements list.
HPCALB_EN : HP Real-Time Counter Calibration Enabled Indicates that the time-calibration mechanism is enabled.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : HPCALB_EN_0
HP timer calibration is disabled.
0x1 : HPCALB_EN_1
HP timer calibration is enabled.
End of enumeration elements list.
HPCALB_VAL : HP Calibration Value Defines the signed calibration value for the HP real-time counter
bits : 10 - 14 (5 bit)
access : read-write
Enumeration:
0 : HPCALB_VAL_0
+0 counts per each 32768 ticks of the counter
0x1 : HPCALB_VAL_1
+1 counts per each 32768 ticks of the counter
0x2 : HPCALB_VAL_2
+2 counts per each 32768 ticks of the counter
0xF : HPCALB_VAL_15
+15 counts per each 32768 ticks of the counter
0x10 : HPCALB_VAL_16
-16 counts per each 32768 ticks of the counter
0x11 : HPCALB_VAL_17
-15 counts per each 32768 ticks of the counter
0x1E : HPCALB_VAL_30
-2 counts per each 32768 ticks of the counter
0x1F : HPCALB_VAL_31
-1 counts per each 32768 ticks of the counter
End of enumeration elements list.
BTN_CONFIG : Button configuration
bits : 24 - 26 (3 bit)
access : read-write
BTN_MASK : Button interrupt mask
bits : 27 - 27 (1 bit)
access : read-write
SNVS_HP Version ID Register 1
address_offset : 0xBF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINOR_REV : SNVS block minor version number
bits : 0 - 7 (8 bit)
access : read-only
MAJOR_REV : SNVS block major version number
bits : 8 - 15 (8 bit)
access : read-only
IP_ID : SNVS block ID
bits : 16 - 31 (16 bit)
access : read-only
SNVS_HP Version ID Register 2
address_offset : 0xBFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CONFIG_OPT : SNVS Configuration Option
bits : 0 - 7 (8 bit)
access : read-only
ECO_REV : SNVS ECO Revision
bits : 8 - 15 (8 bit)
access : read-only
INTG_OPT : SNVS Integration Option
bits : 16 - 23 (8 bit)
access : read-only
IP_ERA : Era of the IP design
bits : 24 - 31 (8 bit)
access : read-only
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