Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8C byte (0x0)
mem_usage : registers
protection : not protected
CCM Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSCNT : Oscillator ready counter value
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0 : OSCNT_0
count 1 ckil
0x7F : OSCNT_127
count 128 ckil's
End of enumeration elements list.
COSC_EN : On chip oscillator enable bit - this bit value is reflected on the output cosc_en
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : COSC_EN_0
disable on chip oscillator
0x1 : COSC_EN_1
enable on chip oscillator
End of enumeration elements list.
REG_BYPASS_COUNT : Counter for analog_reg_bypass signal assertion after standby voltage request by PMIC_STBY_REQ
bits : 21 - 26 (6 bit)
access : read-write
Enumeration:
0 : REG_BYPASS_COUNT_0
no delay
0x1 : REG_BYPASS_COUNT_1
1 CKIL clock period delay
0x3F : REG_BYPASS_COUNT_63
63 CKIL clock periods delay
End of enumeration elements list.
RBC_EN : Enable for REG_BYPASS_COUNTER
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : RBC_EN_0
REG_BYPASS_COUNTER disabled
0x1 : RBC_EN_1
REG_BYPASS_COUNTER enabled.
End of enumeration elements list.
CCM Arm Clock Root Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARM_PODF : Divider for ARM clock root
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ARM_PODF_0
divide by 1
0x1 : ARM_PODF_1
divide by 2
0x2 : ARM_PODF_2
divide by 3
0x3 : ARM_PODF_3
divide by 4
0x4 : ARM_PODF_4
divide by 5
0x5 : ARM_PODF_5
divide by 6
0x6 : ARM_PODF_6
divide by 7
0x7 : ARM_PODF_7
divide by 8
End of enumeration elements list.
CCM Bus Clock Divider Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPH2_CLK2_PODF : Divider for periph2_clk2 podf. Divider should be updated when output clock is gated.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : PERIPH2_CLK2_PODF_0
divide by 1
0x1 : PERIPH2_CLK2_PODF_1
divide by 2
0x2 : PERIPH2_CLK2_PODF_2
divide by 3
0x3 : PERIPH2_CLK2_PODF_3
divide by 4
0x4 : PERIPH2_CLK2_PODF_4
divide by 5
0x5 : PERIPH2_CLK2_PODF_5
divide by 6
0x6 : PERIPH2_CLK2_PODF_6
divide by 7
0x7 : PERIPH2_CLK2_PODF_7
divide by 8
End of enumeration elements list.
FABRIC_MMDC_PODF : Post divider for fabric / mmdc clock.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : FABRIC_MMDC_PODF_0
divide by 1
0x1 : FABRIC_MMDC_PODF_1
divide by 2
0x2 : FABRIC_MMDC_PODF_2
divide by 3
0x3 : FABRIC_MMDC_PODF_3
divide by 4
0x4 : FABRIC_MMDC_PODF_4
divide by 5
0x5 : FABRIC_MMDC_PODF_5
divide by 6
0x6 : FABRIC_MMDC_PODF_6
divide by 7
0x7 : FABRIC_MMDC_PODF_7
divide by 8
End of enumeration elements list.
AXI_CLK_SEL : AXI clock source select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : AXI_CLK_SEL_0
Periph_clk output will be used as AXI clock root
0x1 : AXI_CLK_SEL_1
AXI alternative clock will be used as AXI clock root
End of enumeration elements list.
AXI_ALT_CLK_SEL : AXI alternative clock select
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : AXI_ALT_CLK_SEL_0
PLL2 PFD2 will be selected as alternative clock for AXI root clock
0x1 : AXI_ALT_CLK_SEL_1
PLL3 PFD1 will be selected as alternative clock for AXI root clock
End of enumeration elements list.
IPG_PODF : Divider for ipg podf
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : IPG_PODF_0
divide by 1
0x1 : IPG_PODF_1
divide by 2
0x2 : IPG_PODF_2
divide by 3
0x3 : IPG_PODF_3
divide by 4
End of enumeration elements list.
AHB_PODF : Divider for AHB PODF
bits : 10 - 12 (3 bit)
access : read-write
Enumeration:
0 : AHB_PODF_0
divide by 1
0x1 : AHB_PODF_1
divide by 2
0x2 : AHB_PODF_2
divide by 3
0x3 : AHB_PODF_3
divide by 4
0x4 : AHB_PODF_4
divide by 5
0x5 : AHB_PODF_5
divide by 6
0x6 : AHB_PODF_6
divide by 7
0x7 : AHB_PODF_7
divide by 8
End of enumeration elements list.
AXI_PODF : Post divider for axi clock
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : AXI_PODF_0
Divide by 1
0x1 : AXI_PODF_1
Divide by 2
0x2 : AXI_PODF_2
Divide by 3
0x3 : AXI_PODF_3
Divide by 4
0x4 : AXI_PODF_4
Divide by 5
0x5 : AXI_PODF_5
Divide by 6
0x6 : AXI_PODF_6
Divide by 7
0x7 : AXI_PODF_7
Divide by 8
End of enumeration elements list.
PERIPH_CLK_SEL : Selector for peripheral main clock)
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : PERIPH_CLK_SEL_0
PLL2 (pll2_main_clk)
0x1 : PERIPH_CLK_SEL_1
derive clock from periph_clk2_clk clock source.
End of enumeration elements list.
PERIPH2_CLK_SEL : Selector for peripheral2 main clock (source of mmdc_clk_root )
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : PERIPH2_CLK_SEL_0
PLL2 (pll2_main_clk)
0x1 : PERIPH2_CLK_SEL_1
derive clock from periph2_clk2_clk clock source.
End of enumeration elements list.
PERIPH_CLK2_PODF : Divider for periph_clk2_podf.
bits : 27 - 29 (3 bit)
access : read-write
Enumeration:
0 : PERIPH_CLK2_PODF_0
divide by 1
0x1 : PERIPH_CLK2_PODF_1
divide by 2
0x2 : PERIPH_CLK2_PODF_2
divide by 3
0x3 : PERIPH_CLK2_PODF_3
divide by 4
0x4 : PERIPH_CLK2_PODF_4
divide by 5
0x5 : PERIPH_CLK2_PODF_5
divide by 6
0x6 : PERIPH_CLK2_PODF_6
divide by 7
0x7 : PERIPH_CLK2_PODF_7
divide by 8
End of enumeration elements list.
CCM Bus Clock Multiplexer Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPH_CLK2_SEL : Selector for peripheral clk2 clock multiplexer
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : PERIPH_CLK2_SEL_0
derive clock from pll3_sw_clk
0x1 : PERIPH_CLK2_SEL_1
derive clock from osc_clk (pll1_ref_clk)
0x2 : PERIPH_CLK2_SEL_2
derive clock from pll2_bypass_clk
End of enumeration elements list.
PRE_PERIPH_CLK_SEL : Selector for pre_periph clock multiplexer
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : PRE_PERIPH_CLK_SEL_0
derive clock from PLL2
0x1 : PRE_PERIPH_CLK_SEL_1
derive clock from PLL2 PFD2
0x2 : PRE_PERIPH_CLK_SEL_2
derive clock from PLL2 PFD0
0x3 : PRE_PERIPH_CLK_SEL_3
derive clock from divided (/2) PLL2 PFD2
End of enumeration elements list.
PERIPH2_CLK2_SEL : Selector for periph2_clk2 clock multiplexer
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : PERIPH2_CLK2_SEL_0
derive clock from pll3_sw_clk
0x1 : PERIPH2_CLK2_SEL_1
derive clock fromOSC
End of enumeration elements list.
PRE_PERIPH2_CLK_SEL : Selector for pre_periph2 clock multiplexer
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0 : PRE_PERIPH2_CLK_SEL_0
derive clock from PLL2
0x1 : PRE_PERIPH2_CLK_SEL_1
derive clock from PLL2 PFD2
0x2 : PRE_PERIPH2_CLK_SEL_2
derive clock from PLL2 PFD0
0x3 : PRE_PERIPH2_CLK_SEL_3
derive clock from PLL4
End of enumeration elements list.
LCDIF1_PODF : Post-divider for lcdif1 clock.
bits : 23 - 25 (3 bit)
access : read-write
Enumeration:
0 : LCDIF1_PODF_0
divide by 1
0x1 : LCDIF1_PODF_1
divide by 2
0x2 : LCDIF1_PODF_2
divide by 3
0x3 : LCDIF1_PODF_3
divide by 4
0x4 : LCDIF1_PODF_4
divide by 5
0x5 : LCDIF1_PODF_5
divide by 6
0x6 : LCDIF1_PODF_6
divide by 7
0x7 : LCDIF1_PODF_7
divide by 8
End of enumeration elements list.
CCM Serial Clock Multiplexer Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERCLK_PODF : Divider for perclk podf.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : PERCLK_PODF_0
divide by 1
0x1 : PERCLK_PODF_1
divide by 2
0x2 : PERCLK_PODF_2
divide by 3
0x3 : PERCLK_PODF_3
divide by 4
0x4 : PERCLK_PODF_4
divide by 5
0x5 : PERCLK_PODF_5
divide by 6
0x6 : PERCLK_PODF_6
divide by 7
0x7 : PERCLK_PODF_7
divide by 8
End of enumeration elements list.
PERCLK_CLK_SEL : Selector for the perclk clock multiplexor
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : PERCLK_CLK_SEL_0
derive clock from ipg clk root
0x1 : PERCLK_CLK_SEL_1
derive clock from osc_clk
End of enumeration elements list.
QSPI1_CLK_SEL : QSPI1 clock select
bits : 7 - 9 (3 bit)
access : read-write
Enumeration:
0 : QSPI1_CLK_SEL_0
Derive clock from PLL3
0x1 : QSPI1_CLK_SEL_1
Derive clock from PLL2 PFD0
0x2 : QSPI1_CLK_SEL_2
Derive clock from PLL2 PFD2
0x3 : QSPI1_CLK_SEL_3
Derive clock from PLL2
0x4 : QSPI1_CLK_SEL_4
Derive clock from PLL3 PFD3
0x5 : QSPI1_CLK_SEL_5
Derive clock from PLL3 PFD2
End of enumeration elements list.
SAI1_CLK_SEL : Selector for sai1 clock multiplexer
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : SAI1_CLK_SEL_0
derive clock from PLL3 PFD2
0x1 : SAI1_CLK_SEL_1
derive clock from PLL5
0x2 : SAI1_CLK_SEL_2
derive clock from PLL4
End of enumeration elements list.
SAI2_CLK_SEL : Selector for sai2 clock multiplexer
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : SAI2_CLK_SEL_0
derive clock from PLL3 PFD2
0x1 : SAI2_CLK_SEL_1
derive clock from PLL5
0x2 : SAI2_CLK_SEL_2
derive clock from PLL4
End of enumeration elements list.
SAI3_CLK_SEL : Selector for sai3 clock multiplexer
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : SAI3_CLK_SEL_0
derive clock from PLL3 PFD2
0x1 : SAI3_CLK_SEL_1
derive clock from PLL5
0x2 : SAI3_CLK_SEL_2
derive clock from PLL4
End of enumeration elements list.
USDHC1_CLK_SEL : Selector for usdhc1 clock multiplexer
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : USDHC1_CLK_SEL_0
derive clock from PLL2 PFD2
0x1 : USDHC1_CLK_SEL_1
derive clock from PLL2 PFD0
End of enumeration elements list.
USDHC2_CLK_SEL : Selector for usdhc2 clock multiplexer
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : USDHC2_CLK_SEL_0
derive clock from PLL2 PFD2
0x1 : USDHC2_CLK_SEL_1
derive clock from PLL2 PFD0
End of enumeration elements list.
BCH_CLK_SEL : Selector for bch clock multiplexer
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : BCH_CLK_SEL_0
derive clock from PLL2 PFD2
0x1 : BCH_CLK_SEL_1
derive clock from PLL2 PFD0
End of enumeration elements list.
GPMI_CLK_SEL : Selector for gpmi clock multiplexer
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : GPMI_CLK_SEL_0
derive clock from PLL2 PFD2
0x1 : GPMI_CLK_SEL_1
derive clock from PLL2 PFD0
End of enumeration elements list.
ACLK_EIM_SLOW_PODF : Divider for aclk_eim_slow clock root.
bits : 23 - 25 (3 bit)
access : read-write
Enumeration:
0 : ACLK_EIM_SLOW_PODF_0
divide by 1
0x1 : ACLK_EIM_SLOW_PODF_1
divide by 2
0x2 : ACLK_EIM_SLOW_PODF_2
divide by 3
0x3 : ACLK_EIM_SLOW_PODF_3
divide by 4
0x4 : ACLK_EIM_SLOW_PODF_4
divide by 5
0x5 : ACLK_EIM_SLOW_PODF_5
divide by 6
0x6 : ACLK_EIM_SLOW_PODF_6
divide by 7
0x7 : ACLK_EIM_SLOW_PODF_7
divide by 8
End of enumeration elements list.
QSPI1_PODF : Divider for QSPI1 clock root
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
0 : QSPI1_PODF_0
divide by 1
0x1 : QSPI1_PODF_1
divide by 2
0x7 : QSPI1_PODF_7
divide by 8
End of enumeration elements list.
ACLK_EIM_SLOW_SEL : Selector for aclk_eim_slow root clock multiplexer
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : ACLK_EIM_SLOW_SEL_0
derive clock from AXI
0x1 : ACLK_EIM_SLOW_SEL_1
derive clock from pll3_sw_clk
0x2 : ACLK_EIM_SLOW_SEL_2
derive clock from PLL2 PFD2
0x3 : ACLK_EIM_SLOW_SEL_3
derive clock from PLL3 PFD0
End of enumeration elements list.
CCM Serial Clock Multiplexer Register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAN_CLK_PODF : Divider for can clock podf.
bits : 2 - 7 (6 bit)
access : read-write
Enumeration:
0 : CAN_CLK_PODF_0
divide by 1
0x7 : CAN_CLK_PODF_7
divide by 8
0x3F : CAN_CLK_PODF_63
divide by 2^6
End of enumeration elements list.
CAN_CLK_SEL : Selector for FlexCAN clock multiplexer
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : CAN_CLK_SEL_0
derive clock from pll3_sw_clk divided clock (60M)
0x1 : CAN_CLK_SEL_1
derive clock from osc_clk (24M)
0x2 : CAN_CLK_SEL_2
derive clock from pll3_sw_clk divided clock (80M)
0x3 : CAN_CLK_SEL_3
Disable FlexCAN clock
End of enumeration elements list.
LDB_DI0_DIV : Control for divider of ldb clock for di0
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : LDB_DI0_DIV_0
divide by 3.5
0x1 : LDB_DI0_DIV_1
divide by 7
End of enumeration elements list.
LDB_DI1_DIV : Control for divider of ldb clock for di1
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : LDB_DI1_DIV_0
divide by 3.5
0x1 : LDB_DI1_DIV_1
divide by 7
End of enumeration elements list.
ESAI_CLK_SEL : Selector for the ESAI clock
bits : 19 - 20 (2 bit)
access : read-write
VID_CLK_SEL : Selector for vid clock multiplexer
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0 : VID_CLK_SEL_0
PLL3 PFD1
0x1 : VID_CLK_SEL_1
PLL3
0x2 : VID_CLK_SEL_2
PLL3 PFD3
0x3 : VID_CLK_SEL_3
PLL4
0x4 : VID_CLK_SEL_4
PLL5
End of enumeration elements list.
VID_CLK_PRE_PODF : Post-divider for vid clock root
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : VID_CLK_PRE_PODF_0
divide by 1
0x1 : VID_CLK_PRE_PODF_1
divide by 2
0x2 : VID_CLK_PRE_PODF_2
divide by 3
0x3 : VID_CLK_PRE_PODF_3
divide by 4
End of enumeration elements list.
VID_CLK_PODF : Post-divider for vid clock root
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
0 : VID_CLK_PODF_0
divide by 1
0x1 : VID_CLK_PODF_1
divide by 2
0x2 : VID_CLK_PODF_2
divide by 3
0x3 : VID_CLK_PODF_3
divide by 4
0x4 : VID_CLK_PODF_4
divide by 5
0x5 : VID_CLK_PODF_5
divide by 6
0x6 : VID_CLK_PODF_6
divide by 7
0x7 : VID_CLK_PODF_7
divide by 8
End of enumeration elements list.
CCM Serial Clock Divider Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART_CLK_PODF : Divider for uart clock podf.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : UART_CLK_PODF_0
divide by 1
0x3F : UART_CLK_PODF_63
divide by 2^6
End of enumeration elements list.
UART_CLK_SEL : Selector for the UART clock multiplexor
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : UART_CLK_SEL_0
derive clock from pll3_80m
0x1 : UART_CLK_SEL_1
derive clock from osc_clk
End of enumeration elements list.
USDHC1_PODF : Divider for usdhc1 clock podf. Divider should be updated when output clock is gated.
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : USDHC1_PODF_0
divide by 1
0x1 : USDHC1_PODF_1
divide by 2
0x2 : USDHC1_PODF_2
divide by 3
0x3 : USDHC1_PODF_3
divide by 4
0x4 : USDHC1_PODF_4
divide by 5
0x5 : USDHC1_PODF_5
divide by 6
0x6 : USDHC1_PODF_6
divide by 7
0x7 : USDHC1_PODF_7
divide by 8
End of enumeration elements list.
USDHC2_PODF : Divider for usdhc2 clock. Divider should be updated when output clock is gated.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : USDHC2_PODF_0
divide by 1
0x1 : USDHC2_PODF_1
divide by 2
0x2 : USDHC2_PODF_2
divide by 3
0x3 : USDHC2_PODF_3
divide by 4
0x4 : USDHC2_PODF_4
divide by 5
0x5 : USDHC2_PODF_5
divide by 6
0x6 : USDHC2_PODF_6
divide by 7
0x7 : USDHC2_PODF_7
divide by 8
End of enumeration elements list.
BCH_PODF : Divider for bch clock podf. Divider should be updated when output clock is gated.
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : BCH_PODF_0
divide by 1
0x1 : BCH_PODF_1
divide by 2
0x2 : BCH_PODF_2
divide by 3
0x3 : BCH_PODF_3
divide by 4
0x4 : BCH_PODF_4
divide by 5
0x5 : BCH_PODF_5
divide by 6
0x6 : BCH_PODF_6
divide by 7
0x7 : BCH_PODF_7
divide by 8
End of enumeration elements list.
GPMI_PODF : Divider for gpmi clock pred. Divider should be updated when output clock is gated.
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
0 : GPMI_PODF_0
divide by 1
0x1 : GPMI_PODF_1
divide by 2
0x2 : GPMI_PODF_2
divide by 3
0x3 : GPMI_PODF_3
divide by 4
0x4 : GPMI_PODF_4
divide by 5
0x5 : GPMI_PODF_5
divide by 6
0x6 : GPMI_PODF_6
divide by 7
0x7 : GPMI_PODF_7
divide by 8
End of enumeration elements list.
CCM SAI1 Clock Divider Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAI1_CLK_PODF : Divider for sai1 clock podf
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : SAI1_CLK_PODF_0
divide by 1
0x3F : SAI1_CLK_PODF_63
divide by 2^6
End of enumeration elements list.
SAI1_CLK_PRED : Divider for sai1 clock pred.
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : SAI1_CLK_PRED_0
divide by 1
0x1 : SAI1_CLK_PRED_1
divide by 2
0x2 : SAI1_CLK_PRED_2
divide by 3
0x3 : SAI1_CLK_PRED_3
divide by 4
0x4 : SAI1_CLK_PRED_4
divide by 5
0x5 : SAI1_CLK_PRED_5
divide by 6
0x6 : SAI1_CLK_PRED_6
divide by 7
0x7 : SAI1_CLK_PRED_7
divide by 8
End of enumeration elements list.
ESAI_CLK_PRED : Divider for ESAI clock pred
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : ESAI_CLK_PRED_0
Divide by 1
0x1 : ESAI_CLK_PRED_1
Divide by 2
0x2 : ESAI_CLK_PRED_2
Divide by 3
0x3 : ESAI_CLK_PRED_3
Divide by 4
0x4 : ESAI_CLK_PRED_4
Divide by 5
0x5 : ESAI_CLK_PRED_5
Divide by 6
0x6 : ESAI_CLK_PRED_6
Divide by 7
0x7 : ESAI_CLK_PRED_7
Divide by 8
End of enumeration elements list.
SAI3_CLK_PODF : Divider for sai3 clock podf
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : SAI3_CLK_PODF_0
divide by 1
0x3F : SAI3_CLK_PODF_63
divide by 2^6
End of enumeration elements list.
SAI3_CLK_PRED : Divider for sai3 clock pred.
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
0 : SAI3_CLK_PRED_0
divide by 1
0x1 : SAI3_CLK_PRED_1
divide by 2
0x2 : SAI3_CLK_PRED_2
divide by 3
0x3 : SAI3_CLK_PRED_3
divide by 4
0x4 : SAI3_CLK_PRED_4
divide by 5
0x5 : SAI3_CLK_PRED_5
divide by 6
0x6 : SAI3_CLK_PRED_6
divide by 7
0x7 : SAI3_CLK_PRED_7
divide by 8
End of enumeration elements list.
ESAI_CLK_PODF : Divider for ESAI clock
bits : 25 - 27 (3 bit)
access : read-write
Enumeration:
0 : ESAI_CLK_PODF_0
Divide by 1
0x1 : ESAI_CLK_PODF_1
Divide by 2
0x2 : ESAI_CLK_PODF_2
Divide by 3
0x3 : ESAI_CLK_PODF_3
Divide by 4
0x4 : ESAI_CLK_PODF_4
Divide by 5
0x5 : ESAI_CLK_PODF_5
Divide by 6
0x6 : ESAI_CLK_PODF_6
Divide by 7
0x7 : ESAI_CLK_PODF_7
Divide by 8
End of enumeration elements list.
CCM SAI2 Clock Divider Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAI2_CLK_PODF : Divider for sai2 clock podf
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : SAI2_CLK_PODF_0
divide by 1
0x3F : SAI2_CLK_PODF_63
divide by 2^6
End of enumeration elements list.
SAI2_CLK_PRED : Divider for sai2 clock pred.Divider should be updated when output clock is gated.
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : SAI2_CLK_PRED_0
divide by 1
0x1 : SAI2_CLK_PRED_1
divide by 2
0x2 : SAI2_CLK_PRED_2
divide by 3
0x3 : SAI2_CLK_PRED_3
divide by 4
0x4 : SAI2_CLK_PRED_4
divide by 5
0x5 : SAI2_CLK_PRED_5
divide by 6
0x6 : SAI2_CLK_PRED_6
divide by 7
0x7 : SAI2_CLK_PRED_7
divide by 8
End of enumeration elements list.
LDB_DI0_CLK_SEL : Selector for ldb_di0 clock multiplexerMultiplexor should be updated when both input and output clocks are gated
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : LDB_DI0_CLK_SEL_0
PLL5 clock
0x1 : LDB_DI0_CLK_SEL_1
PLL2 PFD0
0x2 : LDB_DI0_CLK_SEL_2
PLL2 PFD2
0x3 : LDB_DI0_CLK_SEL_3
PLL2 PFD3
0x4 : LDB_DI0_CLK_SEL_4
PLL2 PFD1
0x5 : LDB_DI0_CLK_SEL_5
PLL3 PFD3
End of enumeration elements list.
ENFC_CLK_SEL : Selector for enfc clock multiplexer Multiplexor should be updated when output clock is gated.
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0 : ENFC_CLK_SEL_0
derive clock from PLL2 PFD0
0x1 : ENFC_CLK_SEL_1
derive clock from PLL2
0x2 : ENFC_CLK_SEL_2
derive clock from pll3_sw_clk
0x3 : ENFC_CLK_SEL_3
derive clock from PLL2 PFD2
0x4 : ENFC_CLK_SEL_4
derive clock from PLL3 PFD3
End of enumeration elements list.
ENFC_CLK_PRED : Divider for enfc clock pred divider.Divider should be updated when output clock is gated.
bits : 18 - 20 (3 bit)
access : read-write
Enumeration:
0 : ENFC_CLK_PRED_0
divide by 1
0x1 : ENFC_CLK_PRED_1
divide by 2
0x2 : ENFC_CLK_PRED_2
divide by 3
0x3 : ENFC_CLK_PRED_3
divide by 4
0x4 : ENFC_CLK_PRED_4
divide by 5
0x5 : ENFC_CLK_PRED_5
divide by 6
0x6 : ENFC_CLK_PRED_6
divide by 7
0x7 : ENFC_CLK_PRED_7
divide by 8
End of enumeration elements list.
ENFC_CLK_PODF : Divider for enfc clock divider.
bits : 21 - 26 (6 bit)
access : read-write
Enumeration:
0 : ENFC_CLK_PODF_0
divide by 1
0x1 : ENFC_CLK_PODF_1
divide by 2
0x3F : ENFC_CLK_PODF_63
divide by 2^6
End of enumeration elements list.
CCM D1 Clock Divider Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPDIF0_CLK_SEL : Selector for spdif0 clock multiplexer
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : SPDIF0_CLK_SEL_0
derive clock from PLL4
0x1 : SPDIF0_CLK_SEL_1
derive clock from PLL3 PFD2
0x2 : SPDIF0_CLK_SEL_2
derive clock from PLL5
0x3 : SPDIF0_CLK_SEL_3
derive clock from pll3_sw_clk
End of enumeration elements list.
SPDIF0_CLK_PODF : Divider for spdif0 clock podf. Divider should be updated when output clock is gated.
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
0 : SPDIF0_CLK_PODF_0
divide by 1
0x7 : SPDIF0_CLK_PODF_7
divide by 8
End of enumeration elements list.
SPDIF0_CLK_PRED : Divider for spdif0 clock pred. Divider should be updated when output clock is gated.
bits : 25 - 27 (3 bit)
access : read-write
Enumeration:
0 : SPDIF0_CLK_PRED_0
divide by 1 (do not use with high input frequencies)
0x1 : SPDIF0_CLK_PRED_1
divide by 2
0x2 : SPDIF0_CLK_PRED_2
divide by 3
0x7 : SPDIF0_CLK_PRED_7
divide by 8
End of enumeration elements list.
CCM HSC Clock Divider Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPDC_CLK_SEL : Selector for EPDC root clock multiplexer
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : EPDC_CLK_SEL_0
Derive clock from divided pre-muxed EPDC clock
0x1 : EPDC_CLK_SEL_1
Derive clock from ipp_di0_clk
0x2 : EPDC_CLK_SEL_2
Derive clock from ipp_di1_clk
0x3 : EPDC_CLK_SEL_3
Derive clock from ldb_di0_clk
0x4 : EPDC_CLK_SEL_4
Derive clock from ldb_di1_clk
End of enumeration elements list.
EPDC_PODF : Divider for EPDC clock divider. Divider should be updated when output clock is gated.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : EPDC_PODF_0
Divide by 1
0x1 : EPDC_PODF_1
Divide by 2
0x2 : EPDC_PODF_2
Divide by 3
0x3 : EPDC_PODF_3
Divide by 4
0x4 : EPDC_PODF_4
Divide by 5
0x5 : EPDC_PODF_5
Divide by 6
0x6 : EPDC_PODF_6
Divide by 7
0x7 : EPDC_PODF_7
Divide by 8
End of enumeration elements list.
EPDC_PRE_CLK_SEL : Selector for EPDC root clock pre-multiplexer
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0 : EPDC_PRE_CLK_SEL_0
Derive clock from PLL2
0x1 : EPDC_PRE_CLK_SEL_1
Derive clock from PLL3_SW_CLK
0x2 : EPDC_PRE_CLK_SEL_2
Derive clock from PLL5
0x3 : EPDC_PRE_CLK_SEL_3
Derive clock from PLL2 PFD0
0x4 : EPDC_PRE_CLK_SEL_4
Derive clock from PLL2 PFD2
0x5 : EPDC_PRE_CLK_SEL_5
Derive clock from PLL3 PFD2
End of enumeration elements list.
CCM Serial Clock Divider Register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDIF1_CLK_SEL : Selector for lcdif1 root clock multiplexer
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : LCDIF1_CLK_SEL_0
derive clock from divided pre-muxed lcdif1 clock
0x1 : LCDIF1_CLK_SEL_1
derive clock from ipp_di0_clk
0x2 : LCDIF1_CLK_SEL_2
derive clock from ipp_di1_clk
0x3 : LCDIF1_CLK_SEL_3
derive clock from ldb_di0_clk
0x4 : LCDIF1_CLK_SEL_4
derive clock from ldb_di1_clk
End of enumeration elements list.
LCDIF1_PRED : Pre-divider for lcdif1 clock. Divider should be updated when output clock is gated.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : LCDIF1_PRED_0
divide by 1
0x1 : LCDIF1_PRED_1
divide by 2
0x2 : LCDIF1_PRED_2
divide by 3
0x3 : LCDIF1_PRED_3
divide by 4
0x4 : LCDIF1_PRED_4
divide by 5
0x5 : LCDIF1_PRED_5
divide by 6
0x6 : LCDIF1_PRED_6
divide by 7
0x7 : LCDIF1_PRED_7
divide by 8
End of enumeration elements list.
LCDIF1_PRE_CLK_SEL : Selector for lcdif1 root clock pre-multiplexer
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0 : LCDIF1_PRE_CLK_SEL_0
derive clock from PLL2
0x1 : LCDIF1_PRE_CLK_SEL_1
derive clock from PLL3 PFD3
0x2 : LCDIF1_PRE_CLK_SEL_2
derive clock from PLL5
0x3 : LCDIF1_PRE_CLK_SEL_3
derive clock from PLL2 PFD0
0x4 : LCDIF1_PRE_CLK_SEL_4
derive clock from PLL2 PFD1
0x5 : LCDIF1_PRE_CLK_SEL_5
derive clock from PLL3 PFD1
End of enumeration elements list.
ECSPI_CLK_SEL : Selector for the ECSPI clock multiplexor
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : ECSPI_CLK_SEL_0
derive clock from pll3_60m
0x1 : ECSPI_CLK_SEL_1
derive clock from osc_clk
End of enumeration elements list.
ECSPI_CLK_PODF : Divider for ecspi clock podf
bits : 19 - 24 (6 bit)
access : read-write
Enumeration:
0 : ECSPI_CLK_PODF_0
divide by 1
0x3F : ECSPI_CLK_PODF_63
divide by 2^6
End of enumeration elements list.
CCM Serial Clock Divider Register 3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSI_CLK_SEL : Selector for csi clock multiplexer
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
0 : CSI_CLK_SEL_0
derive clock from osc_clk (24M)
0x1 : CSI_CLK_SEL_1
derive clock from PLL2 PFD2
0x2 : CSI_CLK_SEL_2
derive clock from pll3_120M
0x3 : CSI_CLK_SEL_3
derive clock from PLL3 PFD1
End of enumeration elements list.
CSI_PODF : Post divider for csi_core clock. Divider should be updated when output clock is gated.
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : CSI_PODF_0
divide by 1
0x1 : CSI_PODF_1
divide by 2
0x2 : CSI_PODF_2
divide by 3
0x3 : CSI_PODF_3
divide by 4
0x4 : CSI_PODF_4
divide by 5
0x5 : CSI_PODF_5
divide by 6
0x6 : CSI_PODF_6
divide by 7
0x7 : CSI_PODF_7
divide by 8
End of enumeration elements list.
CCM Control Divider Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MMDC_MASK : During divider ratio mmdc_axi_podf change or sync mux periph2_clk_sel change (but not jtag) or SRC request during warm reset, mask handshake with mmdc module
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : MMDC_MASK_0
Allow handshake with mmdc module.
0x1 : MMDC_MASK_1
Mask handshake with mmdc. Request signal will not be generated.
End of enumeration elements list.
CCM Wakeup Detector Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CCM Divider Handshake In-Process Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AXI_PODF_BUSY : Busy indicator for axi_podf.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : AXI_PODF_BUSY_0
divider is not busy and its value represents the actual division.
0x1 : AXI_PODF_BUSY_1
divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the axi_podf will be applied.
End of enumeration elements list.
AHB_PODF_BUSY : Busy indicator for ahb_podf.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : AHB_PODF_BUSY_0
divider is not busy and its value represents the actual division.
0x1 : AHB_PODF_BUSY_1
divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied.
End of enumeration elements list.
MMDC_PODF_BUSY : Busy indicator for mmdc_axi_podf.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : MMDC_PODF_BUSY_0
divider is not busy and its value represents the actual division.
0x1 : MMDC_PODF_BUSY_1
divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the mmdc_axi_podf will be applied.
End of enumeration elements list.
PERIPH2_CLK_SEL_BUSY : Busy indicator for periph2_clk_sel mux control.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : PERIPH2_CLK_SEL_BUSY_0
mux is not busy and its value represents the actual division.
0x1 : PERIPH2_CLK_SEL_BUSY_1
mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied.
End of enumeration elements list.
PERIPH_CLK_SEL_BUSY : Busy indicator for periph_clk_sel mux control.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : PERIPH_CLK_SEL_BUSY_0
mux is not busy and its value represents the actual division.
0x1 : PERIPH_CLK_SEL_BUSY_1
mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied.
End of enumeration elements list.
ARM_PODF_BUSY : Busy indicator for arm_podf.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : ARM_PODF_BUSY_0
divider is not busy and its value represents the actual division.
0x1 : ARM_PODF_BUSY_1
divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the arm_podf will be applied.
End of enumeration elements list.
CCM Low Power Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPM : Setting the low power mode that system will enter on next assertion of dsm_request signal.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : LPM_0
Remain in run mode
0x1 : LPM_1
Transfer to wait mode
0x2 : LPM_2
Transfer to stop mode
End of enumeration elements list.
ARM_CLK_DIS_ON_LPM : Define if ARM clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ARM_CLK_DIS_ON_LPM_0
ARM clock enabled on wait mode.
0x1 : ARM_CLK_DIS_ON_LPM_1
ARM clock disabled on wait mode. .
End of enumeration elements list.
SBYOS : Standby clock oscillator bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SBYOS_0
On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0')
0x1 : SBYOS_1
On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process.
End of enumeration elements list.
DIS_REF_OSC : dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock, i
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DIS_REF_OSC_0
external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'.
0x1 : DIS_REF_OSC_1
external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'
End of enumeration elements list.
VSTBY : Voltage standby request bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : VSTBY_0
Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0')
0x1 : VSTBY_1
Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1').
End of enumeration elements list.
STBY_COUNT : Standby counter definition
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
0 : STBY_COUNT_0
CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles
0x1 : STBY_COUNT_1
CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles
0x2 : STBY_COUNT_2
CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles
0x3 : STBY_COUNT_3
CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles
End of enumeration elements list.
COSC_PWRDOWN : In run mode, software can manually control powering down of on chip oscillator, i
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : COSC_PWRDOWN_0
On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'.
0x1 : COSC_PWRDOWN_1
On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'.
End of enumeration elements list.
BYPASS_MMDC_LPM_HS : Bypass handshake with mmdc on next entrance to low power mode (STOP or WAIT)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : BYPASS_MMDC_LPM_HS_0
handshake with mmdc on next entrance to low power mode will be performed. .
0x1 : BYPASS_MMDC_LPM_HS_1
handshake with mmdc on next entrance to low power mode will be bypassed.
End of enumeration elements list.
MASK_CORE0_WFI : Mask WFI of core0 for entering low power mode Assertion of all bits[27:22] will generate low power mode request
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : MASK_CORE0_WFI_0
WFI of core0 is not masked
0x1 : MASK_CORE0_WFI_1
WFI of core0 is masked
End of enumeration elements list.
MASK_SCU_IDLE : Mask SCU IDLE for entering low power mode Assertion of all bits[27:22] will generate low power mode request
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : MASK_SCU_IDLE_0
SCU IDLE is not masked
0x1 : MASK_SCU_IDLE_1
SCU IDLE is masked
End of enumeration elements list.
MASK_L2CC_IDLE : Mask L2CC IDLE for entering low power mode
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : MASK_L2CC_IDLE_0
L2CC IDLE is not masked
0x1 : MASK_L2CC_IDLE_1
L2CC IDLE is masked
End of enumeration elements list.
CCM Interrupt Status Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LRF_PLL : CCM interrupt request 2 generated due to lock of all enabled and not bypaseed PLLs
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LRF_PLL_0
interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs
0x1 : LRF_PLL_1
interrupt generated due to lock ready of all enabled and not bypaseed PLLs
End of enumeration elements list.
COSC_READY : CCM interrupt request 2 generated due to on board oscillator ready, i
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : COSC_READY_0
interrupt is not generated due to on board oscillator ready
0x1 : COSC_READY_1
interrupt generated due to on board oscillator ready
End of enumeration elements list.
AXI_PODF_LOADED : CCM interrupt request 1 generated due to frequency change of axi_podf
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : AXI_PODF_LOADED_0
interrupt is not generated due to frequency change of axi_podf
0x1 : AXI_PODF_LOADED_1
interrupt generated due to frequency change of axi_podf
End of enumeration elements list.
PERIPH2_CLK_SEL_LOADED : CCM interrupt request 1 generated due to frequency change of periph2_clk_sel
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : PERIPH2_CLK_SEL_LOADED_0
interrupt is not generated due to frequency change of periph2_clk_sel
0x1 : PERIPH2_CLK_SEL_LOADED_1
interrupt generated due to frequency change of periph2_clk_sel
End of enumeration elements list.
AHB_PODF_LOADED : CCM interrupt request 1 generated due to frequency change of ahb_podf
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : AHB_PODF_LOADED_0
interrupt is not generated due to frequency change of ahb_podf
0x1 : AHB_PODF_LOADED_1
interrupt generated due to frequency change of ahb_podf
End of enumeration elements list.
MMDC_PODF_LOADED : CCM interrupt request 1 generated due to frequency change of mmdc_podf_ loaded
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : MMDC_PODF_LOADED_0
interrupt is not generated due to frequency change of mmdc_podf_ loaded
0x1 : MMDC_PODF_LOADED_1
interrupt generated due to frequency change of mmdc_podf_ loaded
End of enumeration elements list.
PERIPH_CLK_SEL_LOADED : CCM interrupt request 1 generated due to update of periph_clk_sel.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : PERIPH_CLK_SEL_LOADED_0
interrupt is not generated due to update of periph_clk_sel.
0x1 : PERIPH_CLK_SEL_LOADED_1
interrupt generated due to update of periph_clk_sel.
End of enumeration elements list.
ARM_PODF_LOADED : CCM interrupt request 1 generated due to frequency change of arm_podf
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : ARM_PODF_LOADED_0
interrupt is not generated due to frequency change of arm_podf
0x1 : ARM_PODF_LOADED_1
interrupt generated due to frequency change of arm_podf
End of enumeration elements list.
CCM Interrupt Mask Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK_LRF_PLL : mask interrupt generation due to lrf of PLLs
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MASK_LRF_PLL_0
don't mask interrupt due to lrf of PLLs - interrupt will be created
0x1 : MASK_LRF_PLL_1
mask interrupt due to lrf of PLLs
End of enumeration elements list.
MASK_COSC_READY : mask interrupt generation due to on board oscillator ready
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : MASK_COSC_READY_0
don't mask interrupt due to on board oscillator ready - interrupt will be created
0x1 : MASK_COSC_READY_1
mask interrupt due to on board oscillator ready
End of enumeration elements list.
MASK_AXI_PODF_LOADED : mask interrupt generation due to frequency change of axi_podf
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : MASK_AXI_PODF_LOADED_0
don't mask interrupt due to frequency change of axi_podf - interrupt will be created
0x1 : MASK_AXI_PODF_LOADED_1
mask interrupt due to frequency change of axi_podf
End of enumeration elements list.
MASK_PERIPH2_CLK_SEL_LOADED : mask interrupt generation due to update of periph2_clk_sel.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : MASK_PERIPH2_CLK_SEL_LOADED_0
don't mask interrupt due to update of periph2_clk_sel - interrupt will be created
0x1 : MASK_PERIPH2_CLK_SEL_LOADED_1
mask interrupt due to update of periph2_clk_sel
End of enumeration elements list.
MASK_AHB_PODF_LOADED : mask interrupt generation due to frequency change of ahb_podf
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : MASK_AHB_PODF_LOADED_0
don't mask interrupt due to frequency change of ahb_podf - interrupt will be created
0x1 : MASK_AHB_PODF_LOADED_1
mask interrupt due to frequency change of ahb_podf
End of enumeration elements list.
MASK_MMDC_PODF_LOADED : mask interrupt generation due to update of mask_mmdc_podf
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : MASK_MMDC_PODF_LOADED_0
don't mask interrupt due to update of mask_mmdc_podf - interrupt will be created
0x1 : MASK_MMDC_PODF_LOADED_1
mask interrupt due to update of mask_mmdc_podf
End of enumeration elements list.
MASK_PERIPH_CLK_SEL_LOADED : mask interrupt generation due to update of periph_clk_sel.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : MASK_PERIPH_CLK_SEL_LOADED_0
don't mask interrupt due to update of periph_clk_sel - interrupt will be created
0x1 : MASK_PERIPH_CLK_SEL_LOADED_1
mask interrupt due to update of periph_clk_sel
End of enumeration elements list.
ARM_PODF_LOADED : mask interrupt generation due to frequency change of arm_podf
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : ARM_PODF_LOADED_0
don't mask interrupt due to frequency change of arm_podf - interrupt will be created
0x1 : ARM_PODF_LOADED_1
mask interrupt due to frequency change of arm_podf
End of enumeration elements list.
CCM Clock Output Source Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKO_SEL : Selection of the clock to be generated on CCM_CLKO1
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x5 : CLKO_SEL_5
axi_clk_root
0x6 : CLKO_SEL_6
enfc_clk_root
0x7 : CLKO_SEL_7
no description available
0x8 : CLKO_SEL_8
epdc_clk_root
0x9 : CLKO_SEL_9
no description available
0xA : CLKO_SEL_10
lcdif_pix_clk_root
0xB : CLKO_SEL_11
ahb_clk_root
0xC : CLKO_SEL_12
ipg_clk_root
0xD : CLKO_SEL_13
perclk_root
0xE : CLKO_SEL_14
ckil_sync_clk_root
0xF : CLKO_SEL_15
pll4_main_clk
End of enumeration elements list.
CLKO1_DIV : Setting the divider of CCM_CLKO1
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : CLKO1_DIV_0
divide by 1
0x1 : CLKO1_DIV_1
divide by 2
0x2 : CLKO1_DIV_2
divide by 3
0x3 : CLKO1_DIV_3
divide by 4
0x4 : CLKO1_DIV_4
divide by 5
0x5 : CLKO1_DIV_5
divide by 6
0x6 : CLKO1_DIV_6
divide by 7
0x7 : CLKO1_DIV_7
divide by 8
End of enumeration elements list.
CLKO1_EN : Enable of CCM_CLKO1 clock
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : CLKO1_EN_0
CCM_CLKO1 disabled.
0x1 : CLKO1_EN_1
CCM_CLKO1 enabled.
End of enumeration elements list.
CLK_OUT_SEL : CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CLK_OUT_SEL_0
CCM_CLKO1 output drives CCM_CLKO1 clock
0x1 : CLK_OUT_SEL_1
CCM_CLKO1 output drives CCM_CLKO2 clock
End of enumeration elements list.
CLKO2_SEL : Selection of the clock to be generated on CCM_CLKO2
bits : 16 - 20 (5 bit)
access : read-write
Enumeration:
0x1 : CLKO2_SEL_1
mmdc_clk_root
0x2 : CLKO2_SEL_2
gpmi_clk_root
0x3 : CLKO2_SEL_3
usdhc1_clk_root
0x5 : CLKO2_SEL_5
wrck_clk_root
0x6 : CLKO2_SEL_6
ecspi_clk_root
0x8 : CLKO2_SEL_8
bch_clk_root
0xA : CLKO2_SEL_10
arm_clk_root
0xB : CLKO2_SEL_11
csi_core
0xE : CLKO2_SEL_14
osc_clk
0x11 : CLKO2_SEL_17
usdhc2_clk_root
0x12 : CLKO2_SEL_18
sai1_clk_root
0x13 : CLKO2_SEL_19
sai2_clk_root
0x14 : CLKO2_SEL_20
sai3_clk_root
0x17 : CLKO2_SEL_23
can_clk_root
0x19 : CLKO2_SEL_25
qspi1_clk_root
0x1B : CLKO2_SEL_27
aclk_eim_slow_clk_root
0x1C : CLKO2_SEL_28
uart_clk_root
0x1D : CLKO2_SEL_29
spdif0_clk_root
End of enumeration elements list.
CLKO2_DIV : Setting the divider of CCM_CLKO2
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0 : CLKO2_DIV_0
divide by 1
0x1 : CLKO2_DIV_1
divide by 2
0x2 : CLKO2_DIV_2
divide by 3
0x3 : CLKO2_DIV_3
divide by 4
0x4 : CLKO2_DIV_4
divide by 5
0x5 : CLKO2_DIV_5
divide by 6
0x6 : CLKO2_DIV_6
divide by 7
0x7 : CLKO2_DIV_7
divide by 8
End of enumeration elements list.
CLKO2_EN : Enable of CCM_CLKO2 clock
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : CLKO2_EN_0
CCM_CLKO2 disabled.
0x1 : CLKO2_EN_1
CCM_CLKO2 enabled.
End of enumeration elements list.
CCM General Purpose Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMIC_DELAY_SCALER : Defines clock dividion of clock for stby_count (pmic delay counter)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PMIC_DELAY_SCALER_0
clock is not divided
0x1 : PMIC_DELAY_SCALER_1
clock is divided /8
End of enumeration elements list.
MMDC_EXT_CLK_DIS : Disable external clock driver of MMDC during STOP mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : MMDC_EXT_CLK_DIS_0
don't disable during stop mode.
0x1 : MMDC_EXT_CLK_DIS_1
disable during stop mode
End of enumeration elements list.
EFUSE_PROG_SUPPLY_GATE : Defines the value of the output signal cgpr_dout[4]. Gate of program supply for efuse programing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : EFUSE_PROG_SUPPLY_GATE_0
fuse programing supply voltage is gated off to the efuse module
0x1 : EFUSE_PROG_SUPPLY_GATE_1
allow fuse programing.
End of enumeration elements list.
SYS_MEM_DS_CTRL : System memory DS control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : SYS_MEM_DS_CTRL_0
Disable memory DS mode always
0x1 : SYS_MEM_DS_CTRL_1
Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled
End of enumeration elements list.
FPL : Fast PLL enable.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : FPL_0
Engage PLL enable default way.
0x1 : FPL_1
Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode.
End of enumeration elements list.
INT_MEM_CLK_LPM : Control for the Deep Sleep signal to the ARM Platform memories with additional control logic based on the ARM WFI signal
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : INT_MEM_CLK_LPM_0
Disable the clock to the ARM platform memories when entering Low Power Mode
0x1 : INT_MEM_CLK_LPM_1
Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating)
End of enumeration elements list.
CCM Clock Gating Register 0
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : aips_tz1 clocks (aips_tz1_clk_enable)
bits : 0 - 1 (2 bit)
access : read-write
CG1 : aips_tz2 clocks (aips_tz2_clk_enable)
bits : 2 - 3 (2 bit)
access : read-write
CG2 : apbhdma hclk clock (apbhdma_hclk_enable)
bits : 4 - 5 (2 bit)
access : read-write
CG3 : asrc clock (asrc_clk_enable)
bits : 6 - 7 (2 bit)
access : read-write
CG4 : Reserved
bits : 8 - 9 (2 bit)
access : read-write
CG5 : dcp clock (dcp_clk_enable)
bits : 10 - 11 (2 bit)
access : read-write
CG6 : enet clock (enet_clk_enable)
bits : 12 - 13 (2 bit)
access : read-write
CG7 : can1 clock (can1_clk_enable)
bits : 14 - 15 (2 bit)
access : read-write
CG8 : can1_serial clock (can1_serial_clk_enable)
bits : 16 - 17 (2 bit)
access : read-write
CG9 : can2 clock (can2_clk_enable)
bits : 18 - 19 (2 bit)
access : read-write
CG10 : can2_serial clock (can2_serial_clk_enable)
bits : 20 - 21 (2 bit)
access : read-write
CG11 : CPU debug clocks (arm_dbg_clk_enable)
bits : 22 - 23 (2 bit)
access : read-write
CG12 : dcic1 clocks (dcic1_clk_enable) gpt2 bus clocks (gpt2_bus_clk_enable)
bits : 24 - 25 (2 bit)
access : read-write
CG13 : gpt2 serial clocks (gpt2_serial_clk_enable)
bits : 26 - 27 (2 bit)
access : read-write
CG14 : uart2 clock (uart2_clk_enable)
bits : 28 - 29 (2 bit)
access : read-write
CG15 : gpio2_clocks (gpio2_clk_enable)
bits : 30 - 31 (2 bit)
access : read-write
CCM Clock Gating Register 1
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : ecspi1 clocks (ecspi1_clk_enable)
bits : 0 - 1 (2 bit)
access : read-write
CG1 : ecspi2 clocks (ecspi2_clk_enable)
bits : 2 - 3 (2 bit)
access : read-write
CG2 : ecspi3 clocks (ecspi3_clk_enable)
bits : 4 - 5 (2 bit)
access : read-write
CG3 : ecspi4 clocks (ecspi4_clk_enable)
bits : 6 - 7 (2 bit)
access : read-write
CG4 : adc2 clock (adc2_clk_enable)
bits : 8 - 9 (2 bit)
access : read-write
CG5 : uart3 clock (uart3_clk_enable)
bits : 10 - 11 (2 bit)
access : read-write
CG6 : epit1 clocks (epit1_clk_enable)
bits : 12 - 13 (2 bit)
access : read-write
CG7 : epit2 clocks (epit2_clk_enable)
bits : 14 - 15 (2 bit)
access : read-write
CG8 : adc1 clock (adc1_clk_enable)
bits : 16 - 17 (2 bit)
access : read-write
CG9 : sim_s clock (sim_s_clk_enable)
bits : 18 - 19 (2 bit)
access : read-write
CG10 : gpt bus clock (gpt_clk_enable)
bits : 20 - 21 (2 bit)
access : read-write
CG11 : gpt serial clock (gpt_serial_clk_enable)
bits : 22 - 23 (2 bit)
access : read-write
CG12 : uart4 clock (uart4_clk_enable)
bits : 24 - 25 (2 bit)
access : read-write
CG13 : gpio1 clock (gpio1_clk_enable)
bits : 26 - 27 (2 bit)
access : read-write
CG14 : csu clock (csu_clk_enable)
bits : 28 - 29 (2 bit)
access : read-write
CG15 : gpio5 clock (gpio5_clk_enable)
bits : 30 - 31 (2 bit)
access : read-write
CCM Clock Gating Register 2
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : esai clock (esai_clk_enable)
bits : 0 - 1 (2 bit)
access : read-write
CG1 : csi clock (csi_clk_enable)
bits : 2 - 3 (2 bit)
access : read-write
CG2 : iomuxc_snvs clock (iomuxc_snvs_clk_enable)
bits : 4 - 5 (2 bit)
access : read-write
CG3 : i2c1_serial clock (i2c1_serial_clk_enable)
bits : 6 - 7 (2 bit)
access : read-write
CG4 : i2c2_serial clock (i2c2_serial_clk_enable)
bits : 8 - 9 (2 bit)
access : read-write
CG5 : i2c3_serial clock (i2c3_serial_clk_enable)
bits : 10 - 11 (2 bit)
access : read-write
CG6 : OCOTP_CTRL clock (iim_clk_enable)
bits : 12 - 13 (2 bit)
access : read-write
CG7 : iomux_ipt_clk_io clock (iomux_ipt_clk_io_enable)
bits : 14 - 15 (2 bit)
access : read-write
CG8 : ipmux1 clock (ipmux1_clk_enable)
bits : 16 - 17 (2 bit)
access : read-write
CG9 : ipmux2 clock (ipmux2_clk_enable)
bits : 18 - 19 (2 bit)
access : read-write
CG10 : ipmux3 clock (ipmux3_clk_enable)
bits : 20 - 21 (2 bit)
access : read-write
CG11 : ipsync_ip2apb_tzasc1_ipg clocks (ipsync_ip2apb_tzasc1_ipg_master_clk_enable)
bits : 22 - 23 (2 bit)
access : read-write
CG12 : Reserved
bits : 24 - 25 (2 bit)
access : read-write
CG13 : gpio3 clock (gpio3_clk_enable)
bits : 26 - 27 (2 bit)
access : read-write
CG14 : lcd clocks (lcd_clk_enable)
bits : 28 - 29 (2 bit)
access : read-write
CG15 : pxp clocks (pxp_clk_enable)
bits : 30 - 31 (2 bit)
access : read-write
CCM Clock Gating Register 3
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : Reserved
bits : 0 - 1 (2 bit)
access : read-write
CG1 : uart5 clock (uart5_clk_enable)
bits : 2 - 3 (2 bit)
access : read-write
CG2 : epdc clock (epdc_clk_enable)
bits : 4 - 5 (2 bit)
access : read-write
CG3 : uart6 clock (uart6_clk_enable)
bits : 6 - 7 (2 bit)
access : read-write
CG4 : CA7 CCM DAP clock (ccm_dap_clk_enable)
bits : 8 - 9 (2 bit)
access : read-write
CG5 : lcdif1 pix clock (lcdif1_pix_clk_enable)
bits : 10 - 11 (2 bit)
access : read-write
CG6 : gpio4 clock (gpio4_clk_enable)
bits : 12 - 13 (2 bit)
access : read-write
CG7 : qspi1 clock (qspi1_clk_enable)
bits : 14 - 15 (2 bit)
access : read-write
CG8 : wdog1 clock (wdog1_clk_enable)
bits : 16 - 17 (2 bit)
access : read-write
CG9 : a7 clkdiv patch clock (a7_clkdiv_patch_clk_enable)
bits : 18 - 19 (2 bit)
access : read-write
CG10 : mmdc_core_aclk_fast_core_p0 clock (mmdc_core_aclk_fast_core_p0_enable)
bits : 20 - 21 (2 bit)
access : read-write
CG11 : Reserved
bits : 22 - 23 (2 bit)
access : read-write
CG12 : mmdc_core_ipg_clk_p0 clock (mmdc_core_ipg_clk_p0_enable)
bits : 24 - 25 (2 bit)
access : read-write
CG13 : mmdc_core_ipg_clk_p1 clock (mmdc_core_ipg_clk_p1_enable)
bits : 26 - 27 (2 bit)
access : read-write
CG14 : axi clock (axi_clk_enable)
bits : 28 - 29 (2 bit)
access : read-write
CG15 : iomuxc_snvs_gpr clock (iomuxc_snvs_gpr_clk_enable)
bits : 30 - 31 (2 bit)
access : read-write
CCM Clock Gating Register 4
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : Reserved
bits : 0 - 1 (2 bit)
access : read-write
CG1 : iomuxc clock (iomuxc_clk_enable)
bits : 2 - 3 (2 bit)
access : read-write
CG2 : iomuxc gpr clock (iomuxc_gpr_clk_enable)
bits : 4 - 5 (2 bit)
access : read-write
CG3 : sim_cpu clock (sim_cpu_clk_enable)
bits : 6 - 7 (2 bit)
access : read-write
CG4 : cxapbsyncbridge slave clock (cxapbsyncbridge_slave_clk_enable)
bits : 8 - 9 (2 bit)
access : read-write
CG5 : tsc_dig clock (tsc_clk_enable)
bits : 10 - 11 (2 bit)
access : read-write
CG6 : pl301_mx6qper1_bch clocks (pl301_mx6qper1_bchclk_enable) This gates bch_clk_root to sim_m fabric.
bits : 12 - 13 (2 bit)
access : read-write
CG7 : pl301_mx6qper2_mainclk_enable (pl301_mx6qper2_mainclk_enable)
bits : 14 - 15 (2 bit)
access : read-write
CG8 : pwm1 clocks (pwm1_clk_enable)
bits : 16 - 17 (2 bit)
access : read-write
CG9 : pwm2 clocks (pwm2_clk_enable)
bits : 18 - 19 (2 bit)
access : read-write
CG10 : pwm3 clocks (pwm3_clk_enable)
bits : 20 - 21 (2 bit)
access : read-write
CG11 : pwm4 clocks (pwm4_clk_enable)
bits : 22 - 23 (2 bit)
access : read-write
CG12 : rawnand_u_bch_input_apb clock (rawnand_u_bch_input_apb_clk_enable)
bits : 24 - 25 (2 bit)
access : read-write
CG13 : rawnand_u_gpmi_bch_input_bch clock (rawnand_u_gpmi_bch_input_bch_clk_enable)
bits : 26 - 27 (2 bit)
access : read-write
CG14 : rawnand_u_gpmi_bch_input_gpmi_io clock (rawnand_u_gpmi_bch_input_gpmi_io_clk_enable)
bits : 28 - 29 (2 bit)
access : read-write
CG15 : rawnand_u_gpmi_input_apb clock (rawnand_u_gpmi_input_apb_clk_enable)
bits : 30 - 31 (2 bit)
access : read-write
CCM Clock Gating Register 5
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : rom clock (rom_clk_enable)
bits : 0 - 1 (2 bit)
access : read-write
CG1 : stcr clock (stcr_clk_enable)
bits : 2 - 3 (2 bit)
access : read-write
CG2 : snvs dryice clock (snvs_dryice_clk_enable)
bits : 4 - 5 (2 bit)
access : read-write
CG3 : sdma clock (sdma_clk_enable)
bits : 6 - 7 (2 bit)
access : read-write
CG4 : kpp clock (kpp_clk_enable)
bits : 8 - 9 (2 bit)
access : read-write
CG5 : wdog2 clock (wdog2_clk_enable)
bits : 10 - 11 (2 bit)
access : read-write
CG6 : spba clock (spba_clk_enable)
bits : 12 - 13 (2 bit)
access : read-write
CG7 : spdif / audio clock (spdif_clk_enable, audio_clk_root)
bits : 14 - 15 (2 bit)
access : read-write
CG8 : sim_main clock (sim_main_clk_enable)
bits : 16 - 17 (2 bit)
access : read-write
CG9 : snvs_hp clock (snvs_hp_clk_enable)
bits : 18 - 19 (2 bit)
access : read-write
CG10 : snvs_lp clock (snvs_lp_clk_enable)
bits : 20 - 21 (2 bit)
access : read-write
CG11 : sai3 clock (sai3_clk_enable)
bits : 22 - 23 (2 bit)
access : read-write
CG12 : uart1 clock (uart1_clk_enable)
bits : 24 - 25 (2 bit)
access : read-write
CG13 : uart7 clock (uart7_clk_enable)
bits : 26 - 27 (2 bit)
access : read-write
CG14 : sai1 clock (sai1_clk_enable)
bits : 28 - 29 (2 bit)
access : read-write
CG15 : sai2 clock (sai2_clk_enable)
bits : 30 - 31 (2 bit)
access : read-write
CCM Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REF_EN_B : Status of the value of CCM_REF_EN_B output of ccm
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : REF_EN_B_0
value of CCM_REF_EN_B is '0'
0x1 : REF_EN_B_1
value of CCM_REF_EN_B is '1'
End of enumeration elements list.
COSC_READY : Status indication of on board oscillator
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : COSC_READY_0
on board oscillator is not ready.
0x1 : COSC_READY_1
on board oscillator is ready.
End of enumeration elements list.
CCM Clock Gating Register 6
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : usboh3 clock (usboh3_clk_enable)
bits : 0 - 1 (2 bit)
access : read-write
CG1 : usdhc1 clocks (usdhc1_clk_enable)
bits : 2 - 3 (2 bit)
access : read-write
CG2 : usdhc2 clocks (usdhc2_clk_enable)
bits : 4 - 5 (2 bit)
access : read-write
CG3 : Reserved
bits : 6 - 7 (2 bit)
access : read-write
CG4 : ipmux4 clock (ipmux4_clk_enable)
bits : 8 - 9 (2 bit)
access : read-write
CG5 : eim_slow clocks (eim_slow_clk_enable)
bits : 10 - 11 (2 bit)
access : read-write
CG6 : Reserved
bits : 12 - 13 (2 bit)
access : read-write
CG7 : uart8 clocks (uart8_clk_enable)
bits : 14 - 15 (2 bit)
access : read-write
CG8 : pwm8 clocks (pwm8_clk_enable)
bits : 16 - 17 (2 bit)
access : read-write
CG9 : aips_tz3 clock (aips_tz3_clk_enable)
bits : 18 - 19 (2 bit)
access : read-write
CG10 : wdog3 clock (wdog3_clk_enable)
bits : 20 - 21 (2 bit)
access : read-write
CG11 : anadig clocks (anadig_clk_enable)
bits : 22 - 23 (2 bit)
access : read-write
CG12 : i2c4 serial clock (i2c4_serial_clk_enable)
bits : 24 - 25 (2 bit)
access : read-write
CG13 : pwm5 clocks (pwm5_clk_enable)
bits : 26 - 27 (2 bit)
access : read-write
CG14 : pwm6 clocks (pwm6_clk_enable)
bits : 28 - 29 (2 bit)
access : read-write
CG15 : pwm7 clocks (pwm7_clk_enable)
bits : 30 - 31 (2 bit)
access : read-write
CCM Module Enable Overide Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_EN_OV_GPT : Overide clock enable signal from GPT - clock will not be gated based on GPT's signal 'ipg_enable_clk'
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MOD_EN_OV_GPT_0
don't override module enable signal
0x1 : MOD_EN_OV_GPT_1
override module enable signal
End of enumeration elements list.
MOD_EN_OV_EPIT : Overide clock enable signal from EPIT - clock will not be gated based on EPIT's signal 'ipg_enable_clk'
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : MOD_EN_OV_EPIT_0
don't override module enable signal
0x1 : MOD_EN_OV_EPIT_1
override module enable signal
End of enumeration elements list.
MOD_EN_USDHC : overide clock enable signal from USDHC.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MOD_EN_USDHC_0
don't override module enable signal
0x1 : MOD_EN_USDHC_1
override module enable signal
End of enumeration elements list.
MOD_EN_OV_CAN2_CPI : Overide clock enable signal from CAN2 - clock will not be gated based on CAN's signal 'enable_clk_cpi'
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : MOD_EN_OV_CAN2_CPI_0
don't override module enable signal
0x1 : MOD_EN_OV_CAN2_CPI_1
override module enable signal
End of enumeration elements list.
MOD_EN_OV_CAN1_CPI : Overide clock enable signal from CAN1 - clock will not be gated based on CAN's signal 'enable_clk_cpi'
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : MOD_EN_OV_CAN1_CPI_0
don't overide module enable signal
0x1 : MOD_EN_OV_CAN1_CPI_1
overide module enable signal
End of enumeration elements list.
CCM Clock Switcher Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL3_SW_CLK_SEL : Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PLL3_SW_CLK_SEL_0
pll3_main_clk
0x1 : PLL3_SW_CLK_SEL_1
pll3 bypass clock
End of enumeration elements list.
PLL1_SW_CLK_SEL : Selects source to generate pll1_sw_clk.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PLL1_SW_CLK_SEL_0
pll1_main_clk
0x1 : PLL1_SW_CLK_SEL_1
step_clk
End of enumeration elements list.
SECONDARY_CLK_SEL : Select source to generate secondary_clk
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECONDARY_CLK_SEL_0
PLL2 PFD2 (400 M)
0x1 : SECONDARY_CLK_SEL_1
PLL2 (528 M)
End of enumeration elements list.
STEP_SEL : Selects the option to be chosen for the step frequency when shifting ARM frequency
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : STEP_SEL_0
derive clock from osc_clk (24M) - source for lp_apm.
0x1 : STEP_SEL_1
derive clock from secondary_clk
End of enumeration elements list.
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