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USBPHY

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x84 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PWD

TX

TX_SET

TX_CLR

TX_TOG

RX

RX_SET

RX_CLR

RX_TOG

CTRL

CTRL_SET

CTRL_CLR

CTRL_TOG

PWD_SET

STATUS

DEBUG

DEBUG_SET

DEBUG_CLR

DEBUG_TOG

DEBUG0_STATUS

DEBUG1

DEBUG1_SET

DEBUG1_CLR

DEBUG1_TOG

PWD_CLR

VERSION

PWD_TOG


PWD

USB PHY Power-Down Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWD PWD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 TXPWDFS TXPWDIBIAS TXPWDV2I RSVD1 RXPWDENV RXPWD1PT1 RXPWDDIFF RXPWDRX RSVD2

RSVD0 : Reserved.
bits : 0 - 9 (10 bit)
access : read-only

TXPWDFS : 0 = Normal operation
bits : 10 - 10 (1 bit)
access : read-write

TXPWDIBIAS : 0 = Normal operation
bits : 11 - 11 (1 bit)
access : read-write

TXPWDV2I : 0 = Normal operation
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : Reserved.
bits : 13 - 16 (4 bit)
access : read-only

RXPWDENV : 0 = Normal operation
bits : 17 - 17 (1 bit)
access : read-write

RXPWD1PT1 : 0 = Normal operation
bits : 18 - 18 (1 bit)
access : read-write

RXPWDDIFF : 0 = Normal operation
bits : 19 - 19 (1 bit)
access : read-write

RXPWDRX : 0 = Normal operation
bits : 20 - 20 (1 bit)
access : read-write

RSVD2 : Reserved.
bits : 21 - 31 (11 bit)
access : read-only


TX

USB PHY Transmitter Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX TX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D_CAL RSVD0 TXCAL45DN RSVD1 TXCAL45DP RSVD2 USBPHY_TX_EDGECTRL RSVD5

D_CAL : Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%
bits : 0 - 3 (4 bit)
access : read-write

RSVD0 : Reserved. Note: This bit should remain clear.
bits : 4 - 7 (4 bit)
access : read-write

TXCAL45DN : Decode to select a 45-Ohm resistance to the USB_DN output pin
bits : 8 - 11 (4 bit)
access : read-write

RSVD1 : Reserved. Note: This bit should remain clear.
bits : 12 - 15 (4 bit)
access : read-write

TXCAL45DP : Decode to select a 45-Ohm resistance to the USB_DP output pin
bits : 16 - 19 (4 bit)
access : read-write

RSVD2 : Reserved.
bits : 20 - 25 (6 bit)
access : read-only

USBPHY_TX_EDGECTRL : Controls the edge-rate of the current sensing transistors used in HS transmit
bits : 26 - 28 (3 bit)
access : read-write

RSVD5 : Reserved.
bits : 29 - 31 (3 bit)
access : read-only


TX_SET

USB PHY Transmitter Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_SET TX_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D_CAL RSVD0 TXCAL45DN RSVD1 TXCAL45DP RSVD2 USBPHY_TX_EDGECTRL RSVD5

D_CAL : Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%
bits : 0 - 3 (4 bit)
access : read-write

RSVD0 : Reserved. Note: This bit should remain clear.
bits : 4 - 7 (4 bit)
access : read-write

TXCAL45DN : Decode to select a 45-Ohm resistance to the USB_DN output pin
bits : 8 - 11 (4 bit)
access : read-write

RSVD1 : Reserved. Note: This bit should remain clear.
bits : 12 - 15 (4 bit)
access : read-write

TXCAL45DP : Decode to select a 45-Ohm resistance to the USB_DP output pin
bits : 16 - 19 (4 bit)
access : read-write

RSVD2 : Reserved.
bits : 20 - 25 (6 bit)
access : read-only

USBPHY_TX_EDGECTRL : Controls the edge-rate of the current sensing transistors used in HS transmit
bits : 26 - 28 (3 bit)
access : read-write

RSVD5 : Reserved.
bits : 29 - 31 (3 bit)
access : read-only


TX_CLR

USB PHY Transmitter Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_CLR TX_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D_CAL RSVD0 TXCAL45DN RSVD1 TXCAL45DP RSVD2 USBPHY_TX_EDGECTRL RSVD5

D_CAL : Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%
bits : 0 - 3 (4 bit)
access : read-write

RSVD0 : Reserved. Note: This bit should remain clear.
bits : 4 - 7 (4 bit)
access : read-write

TXCAL45DN : Decode to select a 45-Ohm resistance to the USB_DN output pin
bits : 8 - 11 (4 bit)
access : read-write

RSVD1 : Reserved. Note: This bit should remain clear.
bits : 12 - 15 (4 bit)
access : read-write

TXCAL45DP : Decode to select a 45-Ohm resistance to the USB_DP output pin
bits : 16 - 19 (4 bit)
access : read-write

RSVD2 : Reserved.
bits : 20 - 25 (6 bit)
access : read-only

USBPHY_TX_EDGECTRL : Controls the edge-rate of the current sensing transistors used in HS transmit
bits : 26 - 28 (3 bit)
access : read-write

RSVD5 : Reserved.
bits : 29 - 31 (3 bit)
access : read-only


TX_TOG

USB PHY Transmitter Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_TOG TX_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D_CAL RSVD0 TXCAL45DN RSVD1 TXCAL45DP RSVD2 USBPHY_TX_EDGECTRL RSVD5

D_CAL : Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%
bits : 0 - 3 (4 bit)
access : read-write

RSVD0 : Reserved. Note: This bit should remain clear.
bits : 4 - 7 (4 bit)
access : read-write

TXCAL45DN : Decode to select a 45-Ohm resistance to the USB_DN output pin
bits : 8 - 11 (4 bit)
access : read-write

RSVD1 : Reserved. Note: This bit should remain clear.
bits : 12 - 15 (4 bit)
access : read-write

TXCAL45DP : Decode to select a 45-Ohm resistance to the USB_DP output pin
bits : 16 - 19 (4 bit)
access : read-write

RSVD2 : Reserved.
bits : 20 - 25 (6 bit)
access : read-only

USBPHY_TX_EDGECTRL : Controls the edge-rate of the current sensing transistors used in HS transmit
bits : 26 - 28 (3 bit)
access : read-write

RSVD5 : Reserved.
bits : 29 - 31 (3 bit)
access : read-only


RX

USB PHY Receiver Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX RX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENVADJ RSVD0 DISCONADJ RSVD1 RXDBYPASS RSVD2

ENVADJ : The ENVADJ field adjusts the trip point for the envelope detector
bits : 0 - 2 (3 bit)
access : read-write

RSVD0 : Reserved.
bits : 3 - 3 (1 bit)
access : read-only

DISCONADJ : The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0
bits : 4 - 6 (3 bit)
access : read-write

RSVD1 : Reserved.
bits : 7 - 21 (15 bit)
access : read-only

RXDBYPASS : 0 = Normal operation
bits : 22 - 22 (1 bit)
access : read-write

RSVD2 : Reserved.
bits : 23 - 31 (9 bit)
access : read-only


RX_SET

USB PHY Receiver Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_SET RX_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENVADJ RSVD0 DISCONADJ RSVD1 RXDBYPASS RSVD2

ENVADJ : The ENVADJ field adjusts the trip point for the envelope detector
bits : 0 - 2 (3 bit)
access : read-write

RSVD0 : Reserved.
bits : 3 - 3 (1 bit)
access : read-only

DISCONADJ : The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0
bits : 4 - 6 (3 bit)
access : read-write

RSVD1 : Reserved.
bits : 7 - 21 (15 bit)
access : read-only

RXDBYPASS : 0 = Normal operation
bits : 22 - 22 (1 bit)
access : read-write

RSVD2 : Reserved.
bits : 23 - 31 (9 bit)
access : read-only


RX_CLR

USB PHY Receiver Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_CLR RX_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENVADJ RSVD0 DISCONADJ RSVD1 RXDBYPASS RSVD2

ENVADJ : The ENVADJ field adjusts the trip point for the envelope detector
bits : 0 - 2 (3 bit)
access : read-write

RSVD0 : Reserved.
bits : 3 - 3 (1 bit)
access : read-only

DISCONADJ : The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0
bits : 4 - 6 (3 bit)
access : read-write

RSVD1 : Reserved.
bits : 7 - 21 (15 bit)
access : read-only

RXDBYPASS : 0 = Normal operation
bits : 22 - 22 (1 bit)
access : read-write

RSVD2 : Reserved.
bits : 23 - 31 (9 bit)
access : read-only


RX_TOG

USB PHY Receiver Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_TOG RX_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENVADJ RSVD0 DISCONADJ RSVD1 RXDBYPASS RSVD2

ENVADJ : The ENVADJ field adjusts the trip point for the envelope detector
bits : 0 - 2 (3 bit)
access : read-write

RSVD0 : Reserved.
bits : 3 - 3 (1 bit)
access : read-only

DISCONADJ : The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0
bits : 4 - 6 (3 bit)
access : read-write

RSVD1 : Reserved.
bits : 7 - 21 (15 bit)
access : read-only

RXDBYPASS : 0 = Normal operation
bits : 22 - 22 (1 bit)
access : read-write

RSVD2 : Reserved.
bits : 23 - 31 (9 bit)
access : read-only


CTRL

USB PHY General Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENOTG_ID_CHG_IRQ ENHOSTDISCONDETECT ENIRQHOSTDISCON HOSTDISCONDETECT_IRQ ENDEVPLUGINDETECT DEVPLUGIN_POLARITY OTG_ID_CHG_IRQ ENOTGIDDETECT RESUMEIRQSTICKY ENIRQRESUMEDETECT RESUME_IRQ ENIRQDEVPLUGIN DEVPLUGIN_IRQ DATA_ON_LRADC ENUTMILEVEL2 ENUTMILEVEL3 ENIRQWAKEUP WAKEUP_IRQ RSVD0 ENAUTOCLR_CLKGATE ENAUTOCLR_PHY_PWD ENDPDMCHG_WKUP ENIDCHG_WKUP ENVBUSCHG_WKUP FSDLL_RST_EN RSVD1 OTG_ID_VALUE HOST_FORCE_LS_SE0 UTMI_SUSPENDM CLKGATE SFTRST

ENOTG_ID_CHG_IRQ : Enable OTG_ID_CHG_IRQ.
bits : 0 - 0 (1 bit)
access : read-write

ENHOSTDISCONDETECT : For host mode, enables high-speed disconnect detector
bits : 1 - 1 (1 bit)
access : read-write

ENIRQHOSTDISCON : Enables interrupt for detection of disconnection to Device when in high-speed host mode
bits : 2 - 2 (1 bit)
access : read-write

HOSTDISCONDETECT_IRQ : Indicates that the device has disconnected in high-speed mode
bits : 3 - 3 (1 bit)
access : read-write

ENDEVPLUGINDETECT : For device mode, enables 200-KOhm pullups for detecting connectivity to the host.
bits : 4 - 4 (1 bit)
access : read-write

DEVPLUGIN_POLARITY : For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in
bits : 5 - 5 (1 bit)
access : read-write

OTG_ID_CHG_IRQ : OTG ID change interrupt. Indicates the value of ID pin changed.
bits : 6 - 6 (1 bit)
access : read-write

ENOTGIDDETECT : Enables circuit to detect resistance of MiniAB ID pin.
bits : 7 - 7 (1 bit)
access : read-write

RESUMEIRQSTICKY : Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it
bits : 8 - 8 (1 bit)
access : read-write

ENIRQRESUMEDETECT : Enables interrupt for detection of a non-J state on the USB line
bits : 9 - 9 (1 bit)
access : read-write

RESUME_IRQ : Indicates that the host is sending a wake-up after suspend
bits : 10 - 10 (1 bit)
access : read-write

ENIRQDEVPLUGIN : Enables interrupt for the detection of connectivity to the USB line.
bits : 11 - 11 (1 bit)
access : read-write

DEVPLUGIN_IRQ : Indicates that the device is connected
bits : 12 - 12 (1 bit)
access : read-write

DATA_ON_LRADC : Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.
bits : 13 - 13 (1 bit)
access : read-write

ENUTMILEVEL2 : Enables UTMI+ Level2. This should be enabled if needs to support LS device
bits : 14 - 14 (1 bit)
access : read-write

ENUTMILEVEL3 : Enables UTMI+ Level3
bits : 15 - 15 (1 bit)
access : read-write

ENIRQWAKEUP : Enables interrupt for the wakeup events.
bits : 16 - 16 (1 bit)
access : read-write

WAKEUP_IRQ : Indicates that there is a wakeup event
bits : 17 - 17 (1 bit)
access : read-write

RSVD0 : Reserved.
bits : 18 - 18 (1 bit)
access : read-only

ENAUTOCLR_CLKGATE : Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended
bits : 19 - 19 (1 bit)
access : read-write

ENAUTOCLR_PHY_PWD : Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended
bits : 20 - 20 (1 bit)
access : read-write

ENDPDMCHG_WKUP : Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended
bits : 21 - 21 (1 bit)
access : read-write

ENIDCHG_WKUP : Enables the feature to wakeup USB if ID is toggled when USB is suspended.
bits : 22 - 22 (1 bit)
access : read-write

ENVBUSCHG_WKUP : Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.
bits : 23 - 23 (1 bit)
access : read-write

FSDLL_RST_EN : Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.
bits : 24 - 24 (1 bit)
access : read-write

RSVD1 : Reserved.
bits : 25 - 26 (2 bit)
access : read-only

OTG_ID_VALUE : Almost same as OTGID_STATUS in USBPHYx_STATUS Register
bits : 27 - 27 (1 bit)
access : read-only

HOST_FORCE_LS_SE0 : Forces the next FS packet that is transmitted to have a EOP with LS timing
bits : 28 - 28 (1 bit)
access : read-write

UTMI_SUSPENDM : Used by the PHY to indicate a powered-down state
bits : 29 - 29 (1 bit)
access : read-only

CLKGATE : Gate UTMI Clocks
bits : 30 - 30 (1 bit)
access : read-write

SFTRST : Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers
bits : 31 - 31 (1 bit)
access : read-write


CTRL_SET

USB PHY General Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_SET CTRL_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENOTG_ID_CHG_IRQ ENHOSTDISCONDETECT ENIRQHOSTDISCON HOSTDISCONDETECT_IRQ ENDEVPLUGINDETECT DEVPLUGIN_POLARITY OTG_ID_CHG_IRQ ENOTGIDDETECT RESUMEIRQSTICKY ENIRQRESUMEDETECT RESUME_IRQ ENIRQDEVPLUGIN DEVPLUGIN_IRQ DATA_ON_LRADC ENUTMILEVEL2 ENUTMILEVEL3 ENIRQWAKEUP WAKEUP_IRQ RSVD0 ENAUTOCLR_CLKGATE ENAUTOCLR_PHY_PWD ENDPDMCHG_WKUP ENIDCHG_WKUP ENVBUSCHG_WKUP FSDLL_RST_EN RSVD1 OTG_ID_VALUE HOST_FORCE_LS_SE0 UTMI_SUSPENDM CLKGATE SFTRST

ENOTG_ID_CHG_IRQ : Enable OTG_ID_CHG_IRQ.
bits : 0 - 0 (1 bit)
access : read-write

ENHOSTDISCONDETECT : For host mode, enables high-speed disconnect detector
bits : 1 - 1 (1 bit)
access : read-write

ENIRQHOSTDISCON : Enables interrupt for detection of disconnection to Device when in high-speed host mode
bits : 2 - 2 (1 bit)
access : read-write

HOSTDISCONDETECT_IRQ : Indicates that the device has disconnected in high-speed mode
bits : 3 - 3 (1 bit)
access : read-write

ENDEVPLUGINDETECT : For device mode, enables 200-KOhm pullups for detecting connectivity to the host.
bits : 4 - 4 (1 bit)
access : read-write

DEVPLUGIN_POLARITY : For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in
bits : 5 - 5 (1 bit)
access : read-write

OTG_ID_CHG_IRQ : OTG ID change interrupt. Indicates the value of ID pin changed.
bits : 6 - 6 (1 bit)
access : read-write

ENOTGIDDETECT : Enables circuit to detect resistance of MiniAB ID pin.
bits : 7 - 7 (1 bit)
access : read-write

RESUMEIRQSTICKY : Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it
bits : 8 - 8 (1 bit)
access : read-write

ENIRQRESUMEDETECT : Enables interrupt for detection of a non-J state on the USB line
bits : 9 - 9 (1 bit)
access : read-write

RESUME_IRQ : Indicates that the host is sending a wake-up after suspend
bits : 10 - 10 (1 bit)
access : read-write

ENIRQDEVPLUGIN : Enables interrupt for the detection of connectivity to the USB line.
bits : 11 - 11 (1 bit)
access : read-write

DEVPLUGIN_IRQ : Indicates that the device is connected
bits : 12 - 12 (1 bit)
access : read-write

DATA_ON_LRADC : Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.
bits : 13 - 13 (1 bit)
access : read-write

ENUTMILEVEL2 : Enables UTMI+ Level2. This should be enabled if needs to support LS device
bits : 14 - 14 (1 bit)
access : read-write

ENUTMILEVEL3 : Enables UTMI+ Level3
bits : 15 - 15 (1 bit)
access : read-write

ENIRQWAKEUP : Enables interrupt for the wakeup events.
bits : 16 - 16 (1 bit)
access : read-write

WAKEUP_IRQ : Indicates that there is a wakeup event
bits : 17 - 17 (1 bit)
access : read-write

RSVD0 : Reserved.
bits : 18 - 18 (1 bit)
access : read-only

ENAUTOCLR_CLKGATE : Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended
bits : 19 - 19 (1 bit)
access : read-write

ENAUTOCLR_PHY_PWD : Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended
bits : 20 - 20 (1 bit)
access : read-write

ENDPDMCHG_WKUP : Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended
bits : 21 - 21 (1 bit)
access : read-write

ENIDCHG_WKUP : Enables the feature to wakeup USB if ID is toggled when USB is suspended.
bits : 22 - 22 (1 bit)
access : read-write

ENVBUSCHG_WKUP : Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.
bits : 23 - 23 (1 bit)
access : read-write

FSDLL_RST_EN : Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.
bits : 24 - 24 (1 bit)
access : read-write

RSVD1 : Reserved.
bits : 25 - 26 (2 bit)
access : read-only

OTG_ID_VALUE : Almost same as OTGID_STATUS in USBPHYx_STATUS Register
bits : 27 - 27 (1 bit)
access : read-only

HOST_FORCE_LS_SE0 : Forces the next FS packet that is transmitted to have a EOP with LS timing
bits : 28 - 28 (1 bit)
access : read-write

UTMI_SUSPENDM : Used by the PHY to indicate a powered-down state
bits : 29 - 29 (1 bit)
access : read-only

CLKGATE : Gate UTMI Clocks
bits : 30 - 30 (1 bit)
access : read-write

SFTRST : Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers
bits : 31 - 31 (1 bit)
access : read-write


CTRL_CLR

USB PHY General Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_CLR CTRL_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENOTG_ID_CHG_IRQ ENHOSTDISCONDETECT ENIRQHOSTDISCON HOSTDISCONDETECT_IRQ ENDEVPLUGINDETECT DEVPLUGIN_POLARITY OTG_ID_CHG_IRQ ENOTGIDDETECT RESUMEIRQSTICKY ENIRQRESUMEDETECT RESUME_IRQ ENIRQDEVPLUGIN DEVPLUGIN_IRQ DATA_ON_LRADC ENUTMILEVEL2 ENUTMILEVEL3 ENIRQWAKEUP WAKEUP_IRQ RSVD0 ENAUTOCLR_CLKGATE ENAUTOCLR_PHY_PWD ENDPDMCHG_WKUP ENIDCHG_WKUP ENVBUSCHG_WKUP FSDLL_RST_EN RSVD1 OTG_ID_VALUE HOST_FORCE_LS_SE0 UTMI_SUSPENDM CLKGATE SFTRST

ENOTG_ID_CHG_IRQ : Enable OTG_ID_CHG_IRQ.
bits : 0 - 0 (1 bit)
access : read-write

ENHOSTDISCONDETECT : For host mode, enables high-speed disconnect detector
bits : 1 - 1 (1 bit)
access : read-write

ENIRQHOSTDISCON : Enables interrupt for detection of disconnection to Device when in high-speed host mode
bits : 2 - 2 (1 bit)
access : read-write

HOSTDISCONDETECT_IRQ : Indicates that the device has disconnected in high-speed mode
bits : 3 - 3 (1 bit)
access : read-write

ENDEVPLUGINDETECT : For device mode, enables 200-KOhm pullups for detecting connectivity to the host.
bits : 4 - 4 (1 bit)
access : read-write

DEVPLUGIN_POLARITY : For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in
bits : 5 - 5 (1 bit)
access : read-write

OTG_ID_CHG_IRQ : OTG ID change interrupt. Indicates the value of ID pin changed.
bits : 6 - 6 (1 bit)
access : read-write

ENOTGIDDETECT : Enables circuit to detect resistance of MiniAB ID pin.
bits : 7 - 7 (1 bit)
access : read-write

RESUMEIRQSTICKY : Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it
bits : 8 - 8 (1 bit)
access : read-write

ENIRQRESUMEDETECT : Enables interrupt for detection of a non-J state on the USB line
bits : 9 - 9 (1 bit)
access : read-write

RESUME_IRQ : Indicates that the host is sending a wake-up after suspend
bits : 10 - 10 (1 bit)
access : read-write

ENIRQDEVPLUGIN : Enables interrupt for the detection of connectivity to the USB line.
bits : 11 - 11 (1 bit)
access : read-write

DEVPLUGIN_IRQ : Indicates that the device is connected
bits : 12 - 12 (1 bit)
access : read-write

DATA_ON_LRADC : Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.
bits : 13 - 13 (1 bit)
access : read-write

ENUTMILEVEL2 : Enables UTMI+ Level2. This should be enabled if needs to support LS device
bits : 14 - 14 (1 bit)
access : read-write

ENUTMILEVEL3 : Enables UTMI+ Level3
bits : 15 - 15 (1 bit)
access : read-write

ENIRQWAKEUP : Enables interrupt for the wakeup events.
bits : 16 - 16 (1 bit)
access : read-write

WAKEUP_IRQ : Indicates that there is a wakeup event
bits : 17 - 17 (1 bit)
access : read-write

RSVD0 : Reserved.
bits : 18 - 18 (1 bit)
access : read-only

ENAUTOCLR_CLKGATE : Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended
bits : 19 - 19 (1 bit)
access : read-write

ENAUTOCLR_PHY_PWD : Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended
bits : 20 - 20 (1 bit)
access : read-write

ENDPDMCHG_WKUP : Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended
bits : 21 - 21 (1 bit)
access : read-write

ENIDCHG_WKUP : Enables the feature to wakeup USB if ID is toggled when USB is suspended.
bits : 22 - 22 (1 bit)
access : read-write

ENVBUSCHG_WKUP : Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.
bits : 23 - 23 (1 bit)
access : read-write

FSDLL_RST_EN : Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.
bits : 24 - 24 (1 bit)
access : read-write

RSVD1 : Reserved.
bits : 25 - 26 (2 bit)
access : read-only

OTG_ID_VALUE : Almost same as OTGID_STATUS in USBPHYx_STATUS Register
bits : 27 - 27 (1 bit)
access : read-only

HOST_FORCE_LS_SE0 : Forces the next FS packet that is transmitted to have a EOP with LS timing
bits : 28 - 28 (1 bit)
access : read-write

UTMI_SUSPENDM : Used by the PHY to indicate a powered-down state
bits : 29 - 29 (1 bit)
access : read-only

CLKGATE : Gate UTMI Clocks
bits : 30 - 30 (1 bit)
access : read-write

SFTRST : Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers
bits : 31 - 31 (1 bit)
access : read-write


CTRL_TOG

USB PHY General Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_TOG CTRL_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENOTG_ID_CHG_IRQ ENHOSTDISCONDETECT ENIRQHOSTDISCON HOSTDISCONDETECT_IRQ ENDEVPLUGINDETECT DEVPLUGIN_POLARITY OTG_ID_CHG_IRQ ENOTGIDDETECT RESUMEIRQSTICKY ENIRQRESUMEDETECT RESUME_IRQ ENIRQDEVPLUGIN DEVPLUGIN_IRQ DATA_ON_LRADC ENUTMILEVEL2 ENUTMILEVEL3 ENIRQWAKEUP WAKEUP_IRQ RSVD0 ENAUTOCLR_CLKGATE ENAUTOCLR_PHY_PWD ENDPDMCHG_WKUP ENIDCHG_WKUP ENVBUSCHG_WKUP FSDLL_RST_EN RSVD1 OTG_ID_VALUE HOST_FORCE_LS_SE0 UTMI_SUSPENDM CLKGATE SFTRST

ENOTG_ID_CHG_IRQ : Enable OTG_ID_CHG_IRQ.
bits : 0 - 0 (1 bit)
access : read-write

ENHOSTDISCONDETECT : For host mode, enables high-speed disconnect detector
bits : 1 - 1 (1 bit)
access : read-write

ENIRQHOSTDISCON : Enables interrupt for detection of disconnection to Device when in high-speed host mode
bits : 2 - 2 (1 bit)
access : read-write

HOSTDISCONDETECT_IRQ : Indicates that the device has disconnected in high-speed mode
bits : 3 - 3 (1 bit)
access : read-write

ENDEVPLUGINDETECT : For device mode, enables 200-KOhm pullups for detecting connectivity to the host.
bits : 4 - 4 (1 bit)
access : read-write

DEVPLUGIN_POLARITY : For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in
bits : 5 - 5 (1 bit)
access : read-write

OTG_ID_CHG_IRQ : OTG ID change interrupt. Indicates the value of ID pin changed.
bits : 6 - 6 (1 bit)
access : read-write

ENOTGIDDETECT : Enables circuit to detect resistance of MiniAB ID pin.
bits : 7 - 7 (1 bit)
access : read-write

RESUMEIRQSTICKY : Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it
bits : 8 - 8 (1 bit)
access : read-write

ENIRQRESUMEDETECT : Enables interrupt for detection of a non-J state on the USB line
bits : 9 - 9 (1 bit)
access : read-write

RESUME_IRQ : Indicates that the host is sending a wake-up after suspend
bits : 10 - 10 (1 bit)
access : read-write

ENIRQDEVPLUGIN : Enables interrupt for the detection of connectivity to the USB line.
bits : 11 - 11 (1 bit)
access : read-write

DEVPLUGIN_IRQ : Indicates that the device is connected
bits : 12 - 12 (1 bit)
access : read-write

DATA_ON_LRADC : Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.
bits : 13 - 13 (1 bit)
access : read-write

ENUTMILEVEL2 : Enables UTMI+ Level2. This should be enabled if needs to support LS device
bits : 14 - 14 (1 bit)
access : read-write

ENUTMILEVEL3 : Enables UTMI+ Level3
bits : 15 - 15 (1 bit)
access : read-write

ENIRQWAKEUP : Enables interrupt for the wakeup events.
bits : 16 - 16 (1 bit)
access : read-write

WAKEUP_IRQ : Indicates that there is a wakeup event
bits : 17 - 17 (1 bit)
access : read-write

RSVD0 : Reserved.
bits : 18 - 18 (1 bit)
access : read-only

ENAUTOCLR_CLKGATE : Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended
bits : 19 - 19 (1 bit)
access : read-write

ENAUTOCLR_PHY_PWD : Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended
bits : 20 - 20 (1 bit)
access : read-write

ENDPDMCHG_WKUP : Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended
bits : 21 - 21 (1 bit)
access : read-write

ENIDCHG_WKUP : Enables the feature to wakeup USB if ID is toggled when USB is suspended.
bits : 22 - 22 (1 bit)
access : read-write

ENVBUSCHG_WKUP : Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.
bits : 23 - 23 (1 bit)
access : read-write

FSDLL_RST_EN : Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.
bits : 24 - 24 (1 bit)
access : read-write

RSVD1 : Reserved.
bits : 25 - 26 (2 bit)
access : read-only

OTG_ID_VALUE : Almost same as OTGID_STATUS in USBPHYx_STATUS Register
bits : 27 - 27 (1 bit)
access : read-only

HOST_FORCE_LS_SE0 : Forces the next FS packet that is transmitted to have a EOP with LS timing
bits : 28 - 28 (1 bit)
access : read-write

UTMI_SUSPENDM : Used by the PHY to indicate a powered-down state
bits : 29 - 29 (1 bit)
access : read-only

CLKGATE : Gate UTMI Clocks
bits : 30 - 30 (1 bit)
access : read-write

SFTRST : Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers
bits : 31 - 31 (1 bit)
access : read-write


PWD_SET

USB PHY Power-Down Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWD_SET PWD_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 TXPWDFS TXPWDIBIAS TXPWDV2I RSVD1 RXPWDENV RXPWD1PT1 RXPWDDIFF RXPWDRX RSVD2

RSVD0 : Reserved.
bits : 0 - 9 (10 bit)
access : read-only

TXPWDFS : 0 = Normal operation
bits : 10 - 10 (1 bit)
access : read-write

TXPWDIBIAS : 0 = Normal operation
bits : 11 - 11 (1 bit)
access : read-write

TXPWDV2I : 0 = Normal operation
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : Reserved.
bits : 13 - 16 (4 bit)
access : read-only

RXPWDENV : 0 = Normal operation
bits : 17 - 17 (1 bit)
access : read-write

RXPWD1PT1 : 0 = Normal operation
bits : 18 - 18 (1 bit)
access : read-write

RXPWDDIFF : 0 = Normal operation
bits : 19 - 19 (1 bit)
access : read-write

RXPWDRX : 0 = Normal operation
bits : 20 - 20 (1 bit)
access : read-write

RSVD2 : Reserved.
bits : 21 - 31 (11 bit)
access : read-only


STATUS

USB PHY Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 HOSTDISCONDETECT_STATUS RSVD1 DEVPLUGIN_STATUS RSVD2 OTGID_STATUS RSVD3 RESUME_STATUS RSVD4

RSVD0 : Reserved.
bits : 0 - 2 (3 bit)
access : read-only

HOSTDISCONDETECT_STATUS : Indicates that the device has disconnected while in high-speed host mode.
bits : 3 - 3 (1 bit)
access : read-only

RSVD1 : Reserved.
bits : 4 - 5 (2 bit)
access : read-only

DEVPLUGIN_STATUS : Indicates that the device has been connected on the USB_DP and USB_DM lines.
bits : 6 - 6 (1 bit)
access : read-only

RSVD2 : Reserved.
bits : 7 - 7 (1 bit)
access : read-only

OTGID_STATUS : Indicates the results of ID pin on MiniAB plug
bits : 8 - 8 (1 bit)
access : read-write

RSVD3 : Reserved.
bits : 9 - 9 (1 bit)
access : read-only

RESUME_STATUS : Indicates that the host is sending a wake-up after suspend and has triggered an interrupt.
bits : 10 - 10 (1 bit)
access : read-only

RSVD4 : Reserved.
bits : 11 - 31 (21 bit)
access : read-only


DEBUG

USB PHY Debug Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG DEBUG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTGIDPIOLOCK DEBUG_INTERFACE_HOLD HSTPULLDOWN ENHSTPULLDOWN RSVD0 TX2RXCOUNT ENTX2RXCOUNT RSVD1 SQUELCHRESETCOUNT RSVD2 ENSQUELCHRESET SQUELCHRESETLENGTH HOST_RESUME_DEBUG CLKGATE RSVD3

OTGIDPIOLOCK : Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value
bits : 0 - 0 (1 bit)
access : read-write

DEBUG_INTERFACE_HOLD : Use holding registers to assist in timing for external UTMI interface.
bits : 1 - 1 (1 bit)
access : read-write

HSTPULLDOWN : Set bit 3 to 1 to pull down 15-KOhm on USB_DP line
bits : 2 - 3 (2 bit)
access : read-write

ENHSTPULLDOWN : Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown
bits : 4 - 5 (2 bit)
access : read-write

RSVD0 : Reserved.
bits : 6 - 7 (2 bit)
access : read-only

TX2RXCOUNT : Delay in between the end of transmit to the beginning of receive
bits : 8 - 11 (4 bit)
access : read-write

ENTX2RXCOUNT : Set this bit to allow a countdown to transition in between TX and RX.
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : Reserved.
bits : 13 - 15 (3 bit)
access : read-only

SQUELCHRESETCOUNT : Delay in between the detection of squelch to the reset of high-speed RX.
bits : 16 - 20 (5 bit)
access : read-write

RSVD2 : Reserved.
bits : 21 - 23 (3 bit)
access : read-only

ENSQUELCHRESET : Set bit to allow squelch to reset high-speed receive.
bits : 24 - 24 (1 bit)
access : read-write

SQUELCHRESETLENGTH : Duration of RESET in terms of the number of 480-MHz cycles.
bits : 25 - 28 (4 bit)
access : read-write

HOST_RESUME_DEBUG : Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.
bits : 29 - 29 (1 bit)
access : read-write

CLKGATE : Gate Test Clocks
bits : 30 - 30 (1 bit)
access : read-write

RSVD3 : Reserved.
bits : 31 - 31 (1 bit)
access : read-only


DEBUG_SET

USB PHY Debug Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG_SET DEBUG_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTGIDPIOLOCK DEBUG_INTERFACE_HOLD HSTPULLDOWN ENHSTPULLDOWN RSVD0 TX2RXCOUNT ENTX2RXCOUNT RSVD1 SQUELCHRESETCOUNT RSVD2 ENSQUELCHRESET SQUELCHRESETLENGTH HOST_RESUME_DEBUG CLKGATE RSVD3

OTGIDPIOLOCK : Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value
bits : 0 - 0 (1 bit)
access : read-write

DEBUG_INTERFACE_HOLD : Use holding registers to assist in timing for external UTMI interface.
bits : 1 - 1 (1 bit)
access : read-write

HSTPULLDOWN : Set bit 3 to 1 to pull down 15-KOhm on USB_DP line
bits : 2 - 3 (2 bit)
access : read-write

ENHSTPULLDOWN : Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown
bits : 4 - 5 (2 bit)
access : read-write

RSVD0 : Reserved.
bits : 6 - 7 (2 bit)
access : read-only

TX2RXCOUNT : Delay in between the end of transmit to the beginning of receive
bits : 8 - 11 (4 bit)
access : read-write

ENTX2RXCOUNT : Set this bit to allow a countdown to transition in between TX and RX.
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : Reserved.
bits : 13 - 15 (3 bit)
access : read-only

SQUELCHRESETCOUNT : Delay in between the detection of squelch to the reset of high-speed RX.
bits : 16 - 20 (5 bit)
access : read-write

RSVD2 : Reserved.
bits : 21 - 23 (3 bit)
access : read-only

ENSQUELCHRESET : Set bit to allow squelch to reset high-speed receive.
bits : 24 - 24 (1 bit)
access : read-write

SQUELCHRESETLENGTH : Duration of RESET in terms of the number of 480-MHz cycles.
bits : 25 - 28 (4 bit)
access : read-write

HOST_RESUME_DEBUG : Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.
bits : 29 - 29 (1 bit)
access : read-write

CLKGATE : Gate Test Clocks
bits : 30 - 30 (1 bit)
access : read-write

RSVD3 : Reserved.
bits : 31 - 31 (1 bit)
access : read-only


DEBUG_CLR

USB PHY Debug Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG_CLR DEBUG_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTGIDPIOLOCK DEBUG_INTERFACE_HOLD HSTPULLDOWN ENHSTPULLDOWN RSVD0 TX2RXCOUNT ENTX2RXCOUNT RSVD1 SQUELCHRESETCOUNT RSVD2 ENSQUELCHRESET SQUELCHRESETLENGTH HOST_RESUME_DEBUG CLKGATE RSVD3

OTGIDPIOLOCK : Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value
bits : 0 - 0 (1 bit)
access : read-write

DEBUG_INTERFACE_HOLD : Use holding registers to assist in timing for external UTMI interface.
bits : 1 - 1 (1 bit)
access : read-write

HSTPULLDOWN : Set bit 3 to 1 to pull down 15-KOhm on USB_DP line
bits : 2 - 3 (2 bit)
access : read-write

ENHSTPULLDOWN : Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown
bits : 4 - 5 (2 bit)
access : read-write

RSVD0 : Reserved.
bits : 6 - 7 (2 bit)
access : read-only

TX2RXCOUNT : Delay in between the end of transmit to the beginning of receive
bits : 8 - 11 (4 bit)
access : read-write

ENTX2RXCOUNT : Set this bit to allow a countdown to transition in between TX and RX.
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : Reserved.
bits : 13 - 15 (3 bit)
access : read-only

SQUELCHRESETCOUNT : Delay in between the detection of squelch to the reset of high-speed RX.
bits : 16 - 20 (5 bit)
access : read-write

RSVD2 : Reserved.
bits : 21 - 23 (3 bit)
access : read-only

ENSQUELCHRESET : Set bit to allow squelch to reset high-speed receive.
bits : 24 - 24 (1 bit)
access : read-write

SQUELCHRESETLENGTH : Duration of RESET in terms of the number of 480-MHz cycles.
bits : 25 - 28 (4 bit)
access : read-write

HOST_RESUME_DEBUG : Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.
bits : 29 - 29 (1 bit)
access : read-write

CLKGATE : Gate Test Clocks
bits : 30 - 30 (1 bit)
access : read-write

RSVD3 : Reserved.
bits : 31 - 31 (1 bit)
access : read-only


DEBUG_TOG

USB PHY Debug Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG_TOG DEBUG_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTGIDPIOLOCK DEBUG_INTERFACE_HOLD HSTPULLDOWN ENHSTPULLDOWN RSVD0 TX2RXCOUNT ENTX2RXCOUNT RSVD1 SQUELCHRESETCOUNT RSVD2 ENSQUELCHRESET SQUELCHRESETLENGTH HOST_RESUME_DEBUG CLKGATE RSVD3

OTGIDPIOLOCK : Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value
bits : 0 - 0 (1 bit)
access : read-write

DEBUG_INTERFACE_HOLD : Use holding registers to assist in timing for external UTMI interface.
bits : 1 - 1 (1 bit)
access : read-write

HSTPULLDOWN : Set bit 3 to 1 to pull down 15-KOhm on USB_DP line
bits : 2 - 3 (2 bit)
access : read-write

ENHSTPULLDOWN : Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown
bits : 4 - 5 (2 bit)
access : read-write

RSVD0 : Reserved.
bits : 6 - 7 (2 bit)
access : read-only

TX2RXCOUNT : Delay in between the end of transmit to the beginning of receive
bits : 8 - 11 (4 bit)
access : read-write

ENTX2RXCOUNT : Set this bit to allow a countdown to transition in between TX and RX.
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : Reserved.
bits : 13 - 15 (3 bit)
access : read-only

SQUELCHRESETCOUNT : Delay in between the detection of squelch to the reset of high-speed RX.
bits : 16 - 20 (5 bit)
access : read-write

RSVD2 : Reserved.
bits : 21 - 23 (3 bit)
access : read-only

ENSQUELCHRESET : Set bit to allow squelch to reset high-speed receive.
bits : 24 - 24 (1 bit)
access : read-write

SQUELCHRESETLENGTH : Duration of RESET in terms of the number of 480-MHz cycles.
bits : 25 - 28 (4 bit)
access : read-write

HOST_RESUME_DEBUG : Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.
bits : 29 - 29 (1 bit)
access : read-write

CLKGATE : Gate Test Clocks
bits : 30 - 30 (1 bit)
access : read-write

RSVD3 : Reserved.
bits : 31 - 31 (1 bit)
access : read-only


DEBUG0_STATUS

UTMI Debug Status Register 0
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEBUG0_STATUS DEBUG0_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOOP_BACK_FAIL_COUNT UTMI_RXERROR_FAIL_COUNT SQUELCH_COUNT

LOOP_BACK_FAIL_COUNT : Running count of the failed pseudo-random generator loopback
bits : 0 - 15 (16 bit)
access : read-only

UTMI_RXERROR_FAIL_COUNT : Running count of the UTMI_RXERROR.
bits : 16 - 25 (10 bit)
access : read-only

SQUELCH_COUNT : Running count of the squelch reset instead of normal end for HS RX.
bits : 26 - 31 (6 bit)
access : read-only


DEBUG1

UTMI Debug Status Register 1
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG1 DEBUG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 ENTAILADJVD RSVD1

RSVD0 : Reserved. Note: This bit should remain clear.
bits : 0 - 12 (13 bit)
access : read-write

ENTAILADJVD : Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%
bits : 13 - 14 (2 bit)
access : read-write

RSVD1 : Reserved.
bits : 15 - 31 (17 bit)
access : read-only


DEBUG1_SET

UTMI Debug Status Register 1
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG1_SET DEBUG1_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 ENTAILADJVD RSVD1

RSVD0 : Reserved. Note: This bit should remain clear.
bits : 0 - 12 (13 bit)
access : read-write

ENTAILADJVD : Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%
bits : 13 - 14 (2 bit)
access : read-write

RSVD1 : Reserved.
bits : 15 - 31 (17 bit)
access : read-only


DEBUG1_CLR

UTMI Debug Status Register 1
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG1_CLR DEBUG1_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 ENTAILADJVD RSVD1

RSVD0 : Reserved. Note: This bit should remain clear.
bits : 0 - 12 (13 bit)
access : read-write

ENTAILADJVD : Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%
bits : 13 - 14 (2 bit)
access : read-write

RSVD1 : Reserved.
bits : 15 - 31 (17 bit)
access : read-only


DEBUG1_TOG

UTMI Debug Status Register 1
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG1_TOG DEBUG1_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 ENTAILADJVD RSVD1

RSVD0 : Reserved. Note: This bit should remain clear.
bits : 0 - 12 (13 bit)
access : read-write

ENTAILADJVD : Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%
bits : 13 - 14 (2 bit)
access : read-write

RSVD1 : Reserved.
bits : 15 - 31 (17 bit)
access : read-only


PWD_CLR

USB PHY Power-Down Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWD_CLR PWD_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 TXPWDFS TXPWDIBIAS TXPWDV2I RSVD1 RXPWDENV RXPWD1PT1 RXPWDDIFF RXPWDRX RSVD2

RSVD0 : Reserved.
bits : 0 - 9 (10 bit)
access : read-only

TXPWDFS : 0 = Normal operation
bits : 10 - 10 (1 bit)
access : read-write

TXPWDIBIAS : 0 = Normal operation
bits : 11 - 11 (1 bit)
access : read-write

TXPWDV2I : 0 = Normal operation
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : Reserved.
bits : 13 - 16 (4 bit)
access : read-only

RXPWDENV : 0 = Normal operation
bits : 17 - 17 (1 bit)
access : read-write

RXPWD1PT1 : 0 = Normal operation
bits : 18 - 18 (1 bit)
access : read-write

RXPWDDIFF : 0 = Normal operation
bits : 19 - 19 (1 bit)
access : read-write

RXPWDRX : 0 = Normal operation
bits : 20 - 20 (1 bit)
access : read-write

RSVD2 : Reserved.
bits : 21 - 31 (11 bit)
access : read-only


VERSION

UTMI RTL Version
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STEP MINOR MAJOR

STEP : Fixed read-only value reflecting the stepping of the RTL version.
bits : 0 - 15 (16 bit)
access : read-only

MINOR : Fixed read-only value reflecting the MINOR field of the RTL version.
bits : 16 - 23 (8 bit)
access : read-only

MAJOR : Fixed read-only value reflecting the MAJOR field of the RTL version.
bits : 24 - 31 (8 bit)
access : read-only


PWD_TOG

USB PHY Power-Down Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWD_TOG PWD_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 TXPWDFS TXPWDIBIAS TXPWDV2I RSVD1 RXPWDENV RXPWD1PT1 RXPWDDIFF RXPWDRX RSVD2

RSVD0 : Reserved.
bits : 0 - 9 (10 bit)
access : read-only

TXPWDFS : 0 = Normal operation
bits : 10 - 10 (1 bit)
access : read-write

TXPWDIBIAS : 0 = Normal operation
bits : 11 - 11 (1 bit)
access : read-write

TXPWDV2I : 0 = Normal operation
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : Reserved.
bits : 13 - 16 (4 bit)
access : read-only

RXPWDENV : 0 = Normal operation
bits : 17 - 17 (1 bit)
access : read-write

RXPWD1PT1 : 0 = Normal operation
bits : 18 - 18 (1 bit)
access : read-write

RXPWDDIFF : 0 = Normal operation
bits : 19 - 19 (1 bit)
access : read-write

RXPWDRX : 0 = Normal operation
bits : 20 - 20 (1 bit)
access : read-write

RSVD2 : Reserved.
bits : 21 - 31 (11 bit)
access : read-only



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