\n
address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected
PGC Mega Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCR : Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PCR_0
Do not switch off power even if pdn_req is asserted.
0x1 : PCR_1
Switch off power when pdn_req is asserted.
End of enumeration elements list.
PGC Mega Power Up Sequence Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW : After a power-up request (pup_req assertion), the PGC waits a number of IPG clocks equal to the value of SW before asserting power toggle on/off signal (switch_b)
bits : 0 - 5 (6 bit)
access : read-write
SW2ISO : After asserting power toggle on/off signal (switch_b), the PGC waits a number of IPG clocks equal to the value of SW2ISO before negating isolation
bits : 8 - 13 (6 bit)
access : read-write
PGC Mega Pull Down Sequence Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISO : After a power-down request (pdn_req assertion), the PGC waits a number of IPG clocks equal to the value of ISO before asserting isolation
bits : 0 - 5 (6 bit)
access : read-write
ISO2SW : After asserting isolation, the PGC waits a number of IPG clocks equal to the value of ISO2SW before negating power toggle on/off signal (switch_b)
bits : 8 - 13 (6 bit)
access : read-write
PGC CPU Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCR : Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PCR_0
Do not switch off power even if pdn_req is asserted.
0x1 : PCR_1
Switch off power when pdn_req is asserted.
End of enumeration elements list.
PGC CPU Power Up Sequence Control Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW : There are two different silicon revisions: 1
bits : 0 - 5 (6 bit)
access : read-write
SW2ISO : There are two different silicon revisions: 1
bits : 8 - 13 (6 bit)
access : read-write
PGC CPU Pull Down Sequence Control Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISO : After a power-down request (pdn_req assertion), the PGC waits a number of 32k clocks equal to the value of ISO before asserting isolation
bits : 0 - 5 (6 bit)
access : read-write
ISO2SW : After asserting isolation, the PGC waits a number of 32k clocks equal to the value of ISO2SW before negating
bits : 8 - 13 (6 bit)
access : read-write
PGC CPU Power Gating Controller Status Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSR : Power status
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PSR_0
The target subsystem was not powered down for the previous power-down request.
0x1 : PSR_1
The target subsystem was powered down for the previous power-down request.
End of enumeration elements list.
PGC Mega Power Gating Controller Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSR : Power status
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PSR_0
The target subsystem was not powered down for the previous power-down request.
0x1 : PSR_1
The target subsystem was powered down for the previous power-down request.
End of enumeration elements list.
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