Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8C4 byte (0x0)
mem_usage : registers
protection : not protected
MMDC Core Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZ : DDR data bus size. This field determines the size of the data bus of the DDR memory
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : DSIZ_0
16-bit data bus
End of enumeration elements list.
BL : Burst Length
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : BL_0
Burst Length 4 is used
0x1 : BL_1
Burst Length 8 is used
End of enumeration elements list.
COL : Column Address Width
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : COL_0
9 bits column
0x1 : COL_1
10 bits column
0x2 : COL_2
11 bits column
0x3 : COL_3
8 bits column
0x4 : COL_4
12 bits column
End of enumeration elements list.
ROW : Row Address Width
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : ROW_0
11 bits Row
0x1 : ROW_1
12 bits Row
0x2 : ROW_2
13 bits Row
0x3 : ROW_3
14 bits Row
0x4 : ROW_4
15 bits Row
0x5 : ROW_5
16 bits Row
End of enumeration elements list.
SDE_1 : MMDC Enable CS1
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SDE_1_0
Disabled
0x1 : SDE_1_1
Enabled
End of enumeration elements list.
SDE_0 : MMDC Enable CS0
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SDE_0_0
Disabled
0x1 : SDE_0_1
Enabled
End of enumeration elements list.
MMDC Core Timing Configuration Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tCWL : CAS Write Latency
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : tCWL_0
2 cycles (DDR2/DDR3) , 1 cycles (LPDDR2/LPDDR3)
0x1 : tCWL_1
3 cycles (DDR2/DDR3) , 2 cycles (LPDDR2/LPDDR3)
0x2 : tCWL_2
4 cycles (DDR2/DDR3) , 3 cycles (LPDDR2/LPDDR3)
0x3 : tCWL_3
5 cycles (DDR2/DDR3) , 4 cycles (LPDDR2/LPDDR3)
0x4 : tCWL_4
6 cycles (DDR2/DDR3) , 5 cycles (LPDDR2/LPDDR3)
0x5 : tCWL_5
7 cycles (DDR2/DDR3) , 6 cycles (LPDDR2/LPDDR3)
0x6 : tCWL_6
8 cycles (DDR2/DDR3) , 7 cycles (LPDDR2/LPDDR3)
End of enumeration elements list.
tMRD : Mode Register Set command cycle (all banks)
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
0 : tMRD_0
1 clock
0x1 : tMRD_1
2 clocks
0x2 : tMRD_2
3 clocks
0xE : tMRD_14
15 clocks
0xF : tMRD_15
16 clocks
End of enumeration elements list.
tWR : WRITE recovery time (same bank)
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : tWR_0
1cycle
0x1 : tWR_1
2cycles
0x2 : tWR_2
3cycles
0x3 : tWR_3
4cycles
0x4 : tWR_4
5cycles
0x5 : tWR_5
6cycles
0x6 : tWR_6
7cycles
0x7 : tWR_7
8 cycles
End of enumeration elements list.
tRPA : Precharge-all command period
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : tRPA_0
Will be equal to: tRP.
0x1 : tRPA_1
Will be equal to: tRP+1.
End of enumeration elements list.
tRAS : Active to Precharge command period (same bank)
bits : 16 - 20 (5 bit)
access : read-write
Enumeration:
0 : tRAS_0
1 clock
0x1 : tRAS_1
2 clocks
0x2 : tRAS_2
3 clocks
0x1E : tRAS_30
31 clocks
End of enumeration elements list.
tRC : Active to Active or Refresh command period (same bank)
bits : 21 - 25 (5 bit)
access : read-write
Enumeration:
0 : tRC_0
1 clock
0x1 : tRC_1
2 clocks
0x2 : tRC_2
3 clocks
0x1E : tRC_30
31 clocks
0x1F : tRC_31
32 clocks
End of enumeration elements list.
tRP : Precharge command period (same bank)
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
0 : tRP_0
1 clock
0x1 : tRP_1
2 clocks
0x2 : tRP_2
3 clocks
0x3 : tRP_3
4 clocks
0x4 : tRP_4
5 clocks
0x5 : tRP_5
6 clocks
0x6 : tRP_6
7 clocks
0x7 : tRP_7
8 clocks
End of enumeration elements list.
tRCD : Active command to internal read or write delay time (same bank)
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
0 : tRCD_0
1 clock
0x1 : tRCD_1
2 clocks
0x2 : tRCD_2
3 clocks
0x3 : tRCD_3
4 clocks
0x4 : tRCD_4
5 clocks
0x5 : tRCD_5
6 clocks
0x6 : tRCD_6
7 clocks
0x7 : tRCD_7
8 clocks
End of enumeration elements list.
MMDC Core Timing Configuration Register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tRRD : Active to Active command period (all banks)
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : tRRD_0
1cycle
0x1 : tRRD_1
2cycles
0x2 : tRRD_2
3cycles
0x3 : tRRD_3
4cycles
0x4 : tRRD_4
5cycles
0x5 : tRRD_5
6cycles
0x6 : tRRD_6
7cycles
End of enumeration elements list.
tWTR : Internal WRITE to READ command delay (same bank)
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : tWTR_0
1cycle
0x1 : tWTR_1
2cycles
0x2 : tWTR_2
3cycles
0x3 : tWTR_3
4cycles
0x4 : tWTR_4
5cycles
0x5 : tWTR_5
6cycles
0x6 : tWTR_6
7cycles
0x7 : tWTR_7
8 cycles
End of enumeration elements list.
tRTP : Internal READ command to Precharge command delay (same bank)
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : tRTP_0
1cycle
0x1 : tRTP_1
2cycles
0x2 : tRTP_2
3cycles
0x3 : tRTP_3
4cycles
0x4 : tRTP_4
5cycles
0x5 : tRTP_5
6cycles
0x6 : tRTP_6
7cycles
0x7 : tRTP_7
8 cycles
End of enumeration elements list.
tDLLK : DLL locking time
bits : 16 - 24 (9 bit)
access : read-write
Enumeration:
0 : tDLLK_0
1 cycle.
0x1 : tDLLK_1
2 cycles.
0x2 : tDLLK_2
3 cycles.
0xC7 : tDLLK_199
200 cycles
0x1FE : tDLLK_510
511 cycles.
0x1FF : tDLLK_511
512 cycles (JEDEC value for DDR3).
End of enumeration elements list.
MMDC Core Miscellaneous Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RST : Software Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RST_0
Do nothing.
0x1 : RST_1
Assert reset to the MMDC.
End of enumeration elements list.
DDR_TYPE : DDR TYPE. This field determines the type of the external DDR device.
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : DDR_TYPE_0
DDR3 device is used.
0x1 : DDR_TYPE_1
LPDDR2 device is used.
End of enumeration elements list.
DDR_4_BANK : Number of banks per DDR device
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DDR_4_BANK_0
8 banks device is being used. (Default)
0x1 : DDR_4_BANK_1
4 banks device is being used
End of enumeration elements list.
RALAT : Read Additional Latency
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : RALAT_0
no additional latency.
0x1 : RALAT_1
1 cycle additional latency.
0x2 : RALAT_2
2 cycles additional latency.
0x3 : RALAT_3
3 cycles additional latency.
0x4 : RALAT_4
4 cycles additional latency.
0x5 : RALAT_5
5 cycles additional latency.
0x6 : RALAT_6
6 cycles additional latency.
0x7 : RALAT_7
7 cycles additional latency.
End of enumeration elements list.
MIF3_MODE : Command prediction working mode
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
0 : MIF3_MODE_0
Disable prediction.
0x1 : MIF3_MODE_1
Enable prediction based on : Valid access on first pipe line stage.
0x2 : MIF3_MODE_2
Enable prediction based on: Valid access on first pipe line stage, Valid access on axi bus.
0x3 : MIF3_MODE_3
Enable prediction based on: Valid access on first pipe line stage, Valid access on axi bus, Next miss access from access queue.
End of enumeration elements list.
LPDDR2_S2 : LPDDR2 S2 device type indication
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : LPDDR2_S2_0
LPDDR2-S4 device is used.
0x1 : LPDDR2_S2_1
LPDDR2-S2 device is used.
End of enumeration elements list.
BI_ON : Bank Interleaving On
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : BI_ON_0
Banks are not interleaved, and address will be decoded as bank-row-column
0x1 : BI_ON_1
Banks are interleaved, and address will be decoded as row-bank-column
End of enumeration elements list.
WALAT : Write Additional latency
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : WALAT_0
No additional latency required.
0x1 : WALAT_1
1 cycle additional delay
0x2 : WALAT_2
2 cycles additional delay
0x3 : WALAT_3
3 cycles additional delay
End of enumeration elements list.
LHD : Latency hiding disable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : LHD_0
Latency hiding on.
0x1 : LHD_1
Latency hiding disable.
End of enumeration elements list.
ADDR_MIRROR : Address mirroring
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : ADDR_MIRROR_0
Address mirroring disabled.
0x1 : ADDR_MIRROR_1
Address mirroring enabled.
End of enumeration elements list.
CALIB_PER_CS : Number of chip-select for calibration process
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : CALIB_PER_CS_0
Calibration is targetted to CS0
0x1 : CALIB_PER_CS_1
Calibration is targetted to CS1
End of enumeration elements list.
CK1_GATING : Gating the secondary DDR clock
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : CK1_GATING_0
MMDC drives two clocks toward the DDR memory
0x1 : CK1_GATING_1
MMDC drives only one clock toward the DDR memory (CK0)
End of enumeration elements list.
CS1_RDY : External status device on CS1
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : CS1_RDY_0
Device in wake-up period.
0x1 : CS1_RDY_1
Device is ready for initialization.
End of enumeration elements list.
CS0_RDY : External status device on CS0
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : CS0_RDY_0
Device in wake-up period.
0x1 : CS0_RDY_1
Device is ready for initialization.
End of enumeration elements list.
MMDC Core Special Command Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_BA : Bank Address
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : CMD_BA_0
bank address 0
0x1 : CMD_BA_1
bank address 1
0x2 : CMD_BA_2
bank address 2
0x7 : CMD_BA_7
bank address 7
End of enumeration elements list.
CMD_CS : Chip Select. This field determines which chip select the command is targeted to
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : CMD_CS_0
to Chip-select 0
0x1 : CMD_CS_1
to Chip-select 1
End of enumeration elements list.
CMD : Command
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : CMD_0
Normal operation
0x2 : CMD_2
Auto-Refresh Command (set correct CMD_CS).
0x3 : CMD_3
Load Mode Register Command DDR2/DDR3, set correct CMD_CS, CMD_BA, CMD_ADDR_LSB, CMD_ADDR_MSB), MRW Command (LPDDR2/LPDDR3, set correct CMD_CS, MR_OP, MR_ADDR)
0x4 : CMD_4
ZQ calibration (DDR2/DDR3, set correct CMD_CS, {CMD_ADDR_MSB,CMD_ADDR_LSB} = 0x400 or 0x0 )
0x5 : CMD_5
Precharge all, only if banks open (set correct CMD_CS).
0x6 : CMD_6
MRR command (LPDDR2/LPDDR3, set correct CMD_CS, MR_ADDR)
End of enumeration elements list.
WL_EN : DQS pads direction
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : WL_EN_0
Exit write leveling mode or stay in normal mode.
0x1 : WL_EN_1
Write leveling entry command was sent.
End of enumeration elements list.
MRR_READ_DATA_VALID : MRR read data valid
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : MRR_READ_DATA_VALID_0
Cleared upon the assertion of MRR command
0x1 : MRR_READ_DATA_VALID_1
Set after MRR data is valid and stored at MDMRR register.
End of enumeration elements list.
CON_ACK : Configuration acknowledge
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : CON_ACK_0
Configuration of MMDC registers is forbidden.
0x1 : CON_ACK_1
Configuration of MMDC registers is permitted.
End of enumeration elements list.
CON_REQ : Configuration request
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : CON_REQ_0
No request to configure MMDC.
0x1 : CON_REQ_1
A request to configure MMDC is valid
End of enumeration elements list.
CMD_ADDR_LSB_MR_ADDR : Command/Address LSB
bits : 16 - 23 (8 bit)
access : read-write
CMD_ADDR_MSB_MR_OP : Command/Address MSB
bits : 24 - 31 (8 bit)
access : read-write
MMDC Core Refresh Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START_REF : Manual start of refresh cycle
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START_REF_0
Do nothing.
0x1 : START_REF_1
Start a refresh cycle.
End of enumeration elements list.
REFR : Refresh Rate
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
0 : REFR_0
1 refresh
0x1 : REFR_1
2 refreshes
0x2 : REFR_2
3 refreshes
0x3 : REFR_3
4 refreshes
0x4 : REFR_4
5 refreshes
0x5 : REFR_5
6 refreshes
0x6 : REFR_6
7 refreshes
0x7 : REFR_7
8 refreshes
End of enumeration elements list.
REF_SEL : Refresh Selector. This bit selects the source of the clock that will trigger each refresh cycle:
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : REF_SEL_0
Periodic refresh cycles will be triggered in frequency of 64KHz.
0x1 : REF_SEL_1
Periodic refresh cycles will be triggered in frequency of 32KHz.
0x2 : REF_SEL_2
Periodic refresh cycles will be triggered every amount of cycles that are configured in REF_CNT field.
0x3 : REF_SEL_3
No refresh cycles will be triggered.
End of enumeration elements list.
REF_CNT : Refresh Counter at DDR clock period If REF_SEL equals '2' a refresh cycle will begin every amount of DDR cycles configured in this field
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0x1 : REF_CNT_1
1 cycle.
0xFFFE : REF_CNT_65534
65534 cycles.
0xFFFF : REF_CNT_65535
65535 cycles.
End of enumeration elements list.
MMDC Core Read/Write Command Delay Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTR_DIFF : Read to read delay for different chip-select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : RTR_DIFF_0
0 cycle
0x1 : RTR_DIFF_1
1 cycle
0x2 : RTR_DIFF_2
2 cycles (Default)
0x3 : RTR_DIFF_3
3 cycles
0x4 : RTR_DIFF_4
4 cycles
0x5 : RTR_DIFF_5
5 cycles
0x6 : RTR_DIFF_6
6 cycles
0x7 : RTR_DIFF_7
7 cycles
End of enumeration elements list.
RTW_DIFF : Read to write delay for different chip-select
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : RTW_DIFF_0
0 cycle
0x1 : RTW_DIFF_1
1 cycle
0x2 : RTW_DIFF_2
2 cycles (Default)
0x3 : RTW_DIFF_3
3 cycles
0x4 : RTW_DIFF_4
4 cycles
0x5 : RTW_DIFF_5
5 cycles
0x6 : RTW_DIFF_6
6 cycles
0x7 : RTW_DIFF_7
7 cycles
End of enumeration elements list.
WTW_DIFF : Write to write delay for different chip-select
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : WTW_DIFF_0
0 cycle
0x1 : WTW_DIFF_1
1 cycle
0x2 : WTW_DIFF_2
2 cycles
0x3 : WTW_DIFF_3
3 cycles (Default)
0x4 : WTW_DIFF_4
4 cycles
0x5 : WTW_DIFF_5
5 cycles
0x6 : WTW_DIFF_6
6 cycles
0x7 : WTW_DIFF_7
7 cycles
End of enumeration elements list.
WTR_DIFF : Write to read delay for different chip-select
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : WTR_DIFF_0
0 cycle
0x1 : WTR_DIFF_1
1 cycle
0x2 : WTR_DIFF_2
2 cycles
0x3 : WTR_DIFF_3
3 cycles (Default)
0x4 : WTR_DIFF_4
4 cycles
0x5 : WTR_DIFF_5
5 cycles
0x6 : WTR_DIFF_6
6 cycles
0x7 : WTR_DIFF_7
7 cycles
End of enumeration elements list.
RTW_SAME : Read to write delay for the same chip-select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : RTW_SAME_0
0 cycle
0x1 : RTW_SAME_1
1 cycle
0x2 : RTW_SAME_2
2 cycles (Default)
0x3 : RTW_SAME_3
3 cycles
0x4 : RTW_SAME_4
4 cycles
0x5 : RTW_SAME_5
5 cycles
0x6 : RTW_SAME_6
6 cycles
0x7 : RTW_SAME_7
7 cycles
End of enumeration elements list.
tDAI : Device auto initialization period.(maximum) This field is relevant only to LPDDR2 mode
bits : 16 - 28 (13 bit)
access : read-write
Enumeration:
0 : tDAI_0
1 cycle
0xF9F : tDAI_3999
4000 cycles (Default, JEDEC value for LPDDR2, gives 10us at 400MHz clock).
0x1FFF : tDAI_8191
8192 cycles
End of enumeration elements list.
MMDC Core Out of Reset Delays Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RST_to_CKE : DDR3: Time from SDE enable to CKE rise
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x3 : RST_to_CKE_3
1 cycles
0x10 : RST_to_CKE_16
14 cycles (JEDEC value for LPDDR2) - total of 200 us
0x23 : RST_to_CKE_35
33 cycles (JEDEC value for DDR3) - total of 500 us
0x3E : RST_to_CKE_62
60 cycles
0x3F : RST_to_CKE_63
61 cycles
End of enumeration elements list.
SDE_to_RST : DDR3 mode: Time from SDE enable until DDR reset# is high
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0x3 : SDE_to_RST_3
1 cycles
0x4 : SDE_to_RST_4
2 cycles
0x10 : SDE_to_RST_16
14 cycles (JEDEC value for DDR3) - total of 200 us
0x3E : SDE_to_RST_62
60 cycles
0x3F : SDE_to_RST_63
61 cycles
End of enumeration elements list.
tXPR : DDR2/DDR3: CKE HIGH to a valid command
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0x1 : tXPR_1
2 cycles
0x2 : tXPR_2
3 cycles
0xFE : tXPR_254
255 cycles
0xFF : tXPR_255
256 cycles
End of enumeration elements list.
MMDC Core MRR Data Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MRR_READ_DATA0 : MRR DATA that arrived on DQ[7:0]
bits : 0 - 7 (8 bit)
access : read-only
MRR_READ_DATA1 : MRR DATA that arrived on DQ[15:8]
bits : 8 - 15 (8 bit)
access : read-only
MMDC Core Timing Configuration Register 3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tRPab_LP : Precharge (all banks) command period. This field is valid only for LPDDR2 memories
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : tRPab_LP_0
1 clock
0x1 : tRPab_LP_1
2 clocks
0x2 : tRPab_LP_2
3 clocks
0xE : tRPab_LP_14
15 clocks
End of enumeration elements list.
tRPpb_LP : Precharge (per bank) command period (same bank). This field is valid only for LPDDR2 memories
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : tRPpb_LP_0
1 clock
0x1 : tRPpb_LP_1
2 clocks
0x2 : tRPpb_LP_2
3 clocks
0xE : tRPpb_LP_14
15 clocks
End of enumeration elements list.
tRCD_LP : Active command to internal read or write delay time (same bank)
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : tRCD_LP_0
1 clock
0x1 : tRCD_LP_1
2 clocks
0x2 : tRCD_LP_2
3 clocks
0xE : tRCD_LP_14
15 clocks
End of enumeration elements list.
RC_LP : Active to Active or Refresh command period (same bank)
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : RC_LP_0
1 clock
0x1 : RC_LP_1
2 clocks
0x2 : RC_LP_2
3 clocks
0x3E : RC_LP_62
63 clocks
End of enumeration elements list.
MMDC Core MR4 Derating Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPDATE_DE_REQ : Update Derated Values Request
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : UPDATE_DE_REQ_0
Do nothing.
0x1 : UPDATE_DE_REQ_1
Request to update the following values: tRRD, tRCD, tRP, tRC, tRAS and refresh related fields(MDREF register): REF_CNT, REF_SEL, REFR
End of enumeration elements list.
UPDATE_DE_ACK : Update Derated Values Acknowledge
bits : 1 - 1 (1 bit)
access : read-only
tRCD_DE : tRCD derating value.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : tRCD_DE_0
Original tRCD is used.
0x1 : tRCD_DE_1
tRCD is derated in 1 cycle.
End of enumeration elements list.
tRC_DE : tRC derating value.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : tRC_DE_0
Original tRC is used.
0x1 : tRC_DE_1
tRC is derated in 1 cycle.
End of enumeration elements list.
tRAS_DE : tRAS derating value.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : tRAS_DE_0
Original tRAS is used.
0x1 : tRAS_DE_1
tRAS is derated in 1 cycle.
End of enumeration elements list.
tRP_DE : tRP derating value.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : tRP_DE_0
Original tRP is used.
0x1 : tRP_DE_1
tRP is derated in 1 cycle.
End of enumeration elements list.
tRRD_DE : tRRD derating value.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : tRRD_DE_0
Original tRRD is used.
0x1 : tRRD_DE_1
tRRD is derated in 1 cycle.
End of enumeration elements list.
MMDC Core Power Down Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tCKSRE : Valid clock cycles after self-refresh entry
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : tCKSRE_0
0 cycle
0x1 : tCKSRE_1
1 cycles
0x6 : tCKSRE_6
6 cycles
0x7 : tCKSRE_7
7 cycles
End of enumeration elements list.
tCKSRX : Valid clock cycles before self-refresh exit
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : tCKSRX_0
0 cycle
0x1 : tCKSRX_1
1 cycles
0x6 : tCKSRX_6
6 cycles
0x7 : tCKSRX_7
7 cycles
End of enumeration elements list.
BOTH_CS_PD : Parallel power down entry to both chip selects
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : BOTH_CS_PD_0
Each chip select can enter power down independently according to its configuration.
0x1 : BOTH_CS_PD_1
Chip selects can enter power down only if the amount of idle cycles of both chip selects was obtained.
End of enumeration elements list.
SLOW_PD : Slow/fast power down
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SLOW_PD_0
Fast mode.
0x1 : SLOW_PD_1
Slow mode.
End of enumeration elements list.
PWDT_0 : Power Down Timer - Chip Select 0
bits : 8 - 11 (4 bit)
access : read-write
PWDT_1 : Power Down Timer - Chip Select 1
bits : 12 - 15 (4 bit)
access : read-write
tCKE : CKE minimum pulse width. This field determines the minimum pulse width of CKE.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : tCKE_0
1 cycle
0x1 : tCKE_1
2 cycles
0x6 : tCKE_6
7 cycles
0x7 : tCKE_7
8 cycles
End of enumeration elements list.
PRCT_0 : Precharge Timer - Chip Select 0
bits : 24 - 26 (3 bit)
access : read-write
PRCT_1 : Precharge Timer - Chip Select 1
bits : 28 - 30 (3 bit)
access : read-write
MMDC Core Address Space Partition Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CS0_END : CS0_END
bits : 0 - 6 (7 bit)
access : read-write
MMDC Core AXI Reordering Control Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARCR_GUARD : ARCR Guard
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : ARCR_GUARD_0
15 (default)
0x1 : ARCR_GUARD_1
16
0xF : ARCR_GUARD_15
30
End of enumeration elements list.
ARCR_DYN_MAX : ARCR Dynamic Maximum
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : ARCR_DYN_MAX_0
0
0x1 : ARCR_DYN_MAX_1
1
0xF : ARCR_DYN_MAX_15
15 (default)
End of enumeration elements list.
ARCR_DYN_JMP : ARCR Dynamic Jump
bits : 8 - 11 (4 bit)
access : read-write
ARCR_ACC_HIT : ARCR Access Hit Rate
bits : 16 - 18 (3 bit)
access : read-write
ARCR_PAG_HIT : ARCR Page Hit Rate
bits : 20 - 22 (3 bit)
access : read-write
ARCR_RCH_EN : This bit defines whether Real time channel is activated and bypassed all other pending accesses, So accesses with QoS=='F' will be granted the highest priority in the optimization/reordering mechanism Default value is 0x1 - encoding 1 (Enabled)
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : ARCR_RCH_EN_0
normal prioritization, no bypassing
0x1 : ARCR_RCH_EN_1
accesses with QoS=='F' bypass the arbitration
End of enumeration elements list.
ARCR_REO_DIS : no description available
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : ARCR_REO_DIS_0
MMDC reordering controls only enabled
0x1 : ARCR_REO_DIS_1
MMDC reordering controls only disabled
End of enumeration elements list.
ARCR_ARB_REO_DIS : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : ARCR_ARB_REO_DIS_0
MMDC arbitration and reordering controls enabled
0x1 : ARCR_ARB_REO_DIS_1
MMDC arbitration and reordering controls disabled
End of enumeration elements list.
ARCR_EXC_ERR_EN : This bit defines whether exclusive read/write access violation of AXI 6
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : ARCR_EXC_ERR_EN_0
violation of AXI exclusive rules (6.2.4) result in OKAY response (rresp/bresp=2'b00)
0x1 : ARCR_EXC_ERR_EN_1
violation of AXI exclusive rules (6.2.4) result in SLAVE Error response (rresp/bresp=2'b10)
End of enumeration elements list.
ARCR_SEC_ERR_EN : This bit defines whether security read/write access violation result in SLV Error response or in OKAY response Default value is 0x1 - encoding 1(response is SLV Error, rresp/bresp=2'b10)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ARCR_SEC_ERR_EN_0
security violation results in OKAY response (rresp/bresp=2'b00)
0x1 : ARCR_SEC_ERR_EN_1
security violation results in SLAVE Error response (rresp/bresp=2'b10)
End of enumeration elements list.
ARCR_SEC_ERR_LOCK : Once set, this bit locks ARCR_SEC_ERR_EN and prevents from its updating
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : ARCR_SEC_ERR_LOCK_0
ARCR_SEC_ERR_EN is unlocked, so can be updated any moment
0x1 : ARCR_SEC_ERR_LOCK_1
ARCR_SEC_ERR_EN is locked, so it can't be updated
End of enumeration elements list.
MMDC Core Power Saving Control and Status Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSD : Automatic Power Saving Disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PSD_0
power saving enabled
0x1 : PSD_1
power saving disabled (default)
End of enumeration elements list.
PSS : Power Saving Status
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : PSS_0
not in power saving
0x1 : PSS_1
power saving
End of enumeration elements list.
RIS : Read Idle Status. This read only bit indicates whether read request buffer is idle (empty) or not.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : RIS_0
idle
0x1 : RIS_1
not idle
End of enumeration elements list.
WIS : Write Idle Status
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : WIS_0
idle
0x1 : WIS_1
not idle
End of enumeration elements list.
PST : Automatic Power saving timer
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
0x1 : PST_1
timer is configured to 64 clock cycles.
0x2 : PST_2
timer is configured to 128 clock cycles.
0x10 : PST_16
(Default)- 1024 clock cycles.
0xFF : PST_255
timer clock is configured to 16320 clock cycles.
End of enumeration elements list.
LPMD : General LPMD request
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : LPMD_0
no lpmd request
0x1 : LPMD_1
lpmd request
End of enumeration elements list.
DVFS : General DVFS request
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DVFS_0
no dvfs request
0x1 : DVFS_1
dvfs request
End of enumeration elements list.
LPACK : General low-power acknowledge
bits : 24 - 24 (1 bit)
access : read-only
DVACK : General DVFS acknowledge
bits : 25 - 25 (1 bit)
access : read-only
MMDC Core Exclusive ID Monitor Register0
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXC_ID_MONITOR0 : This field defines ID for Exclusive monitor#0. Default value is 0x0000
bits : 0 - 15 (16 bit)
access : read-write
EXC_ID_MONITOR1 : This field defines ID for Exclusive monitor#1. Default value is 0x0020
bits : 16 - 31 (16 bit)
access : read-write
MMDC Core Exclusive ID Monitor Register1
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXC_ID_MONITOR2 : This field defines ID for Exclusive monitor#2. Default value is 0x0040
bits : 0 - 15 (16 bit)
access : read-write
EXC_ID_MONITOR3 : This field defines ID for Exclusive monitor#3. Default value is 0x0060
bits : 16 - 31 (16 bit)
access : read-write
MMDC Core Debug and Profiling Control Register 0
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_EN : Debug and Profiling Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DBG_EN_0
disable
0x1 : DBG_EN_1
enable
End of enumeration elements list.
DBG_RST : Debug and Profiling Reset. Reset all debug and profiling counters and components.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DBG_RST_0
no reset
0x1 : DBG_RST_1
reset
End of enumeration elements list.
PRF_FRZ : Profiling freeze
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PRF_FRZ_0
profiling counters are not frozen
0x1 : PRF_FRZ_1
profiling counters are frozen
End of enumeration elements list.
CYC_OVF : Total Profiling Cycles Count Overflow
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : CYC_OVF_0
no overflow
0x1 : CYC_OVF_1
overflow
End of enumeration elements list.
SBS_EN : Step By Step debug Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SBS_EN_0
disable
0x1 : SBS_EN_1
enable
End of enumeration elements list.
SBS : Step By Step trigger
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SBS_0
No access will be launched toward the DDR
0x1 : SBS_1
Launch AXI pending access toward the DDR
End of enumeration elements list.
MMDC Core Debug and Profiling Control Register 1
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRF_AXI_ID : Profiling AXI ID
bits : 0 - 15 (16 bit)
access : read-write
PRF_AXI_IDMASK : Profiling AXI ID Mask. AXI ID bits which masked by this value are chosen for profiling.
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : PRF_AXI_IDMASK_0
AXI ID specific bit is ignored (don't care)
0x1 : PRF_AXI_IDMASK_1
AXI ID specific bit is chosen for profiling
End of enumeration elements list.
MMDC Core Debug and Profiling Status Register 0
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CYC_COUNT : Total Profiling cycle Count
bits : 0 - 31 (32 bit)
access : read-only
MMDC Core Debug and Profiling Status Register 1
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY_COUNT : Profiling Busy Cycles Count
bits : 0 - 31 (32 bit)
access : read-only
MMDC Core Debug and Profiling Status Register 2
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD_ACC_COUNT : Profiling Read Access Count
bits : 0 - 31 (32 bit)
access : read-only
MMDC Core Debug and Profiling Status Register 3
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WR_ACC_COUNT : Profiling Write Access Count
bits : 0 - 31 (32 bit)
access : read-only
MMDC Core Debug and Profiling Status Register 4
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD_BYTES_COUNT : Profiling Read Bytes Count
bits : 0 - 31 (32 bit)
access : read-only
MMDC Core Debug and Profiling Status Register 5
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WR_BYTES_COUNT : Profiling Write Bytes Count
bits : 0 - 31 (32 bit)
access : read-only
MMDC Core Step By Step Address Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SBS_ADDR : Step By Step Address
bits : 0 - 31 (32 bit)
access : read-only
MMDC Core Step By Step Address Attributes Register
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SBS_VLD : Step By Step Valid
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : SBS_VLD_0
not valid
0x1 : SBS_VLD_1
valid
End of enumeration elements list.
SBS_TYPE : Step By Step Request Type
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : SBS_TYPE_0
write
0x1 : SBS_TYPE_1
read
End of enumeration elements list.
SBS_LOCK : Step By Step Lock
bits : 2 - 3 (2 bit)
access : read-only
SBS_PROT : Step By Step Protection
bits : 4 - 6 (3 bit)
access : read-only
SBS_SIZE : Step By Step Size
bits : 7 - 9 (3 bit)
access : read-only
Enumeration:
0 : SBS_SIZE_0
8 bits
0x1 : SBS_SIZE_1
16 bits
0x2 : SBS_SIZE_2
32 bits
0x3 : SBS_SIZE_3
64 bits
0x4 : SBS_SIZE_4
128bits
End of enumeration elements list.
SBS_BURST : Step By Step Burst
bits : 10 - 11 (2 bit)
access : read-only
Enumeration:
0 : SBS_BURST_0
FIXED
0x1 : SBS_BURST_1
INCR burst
0x2 : SBS_BURST_2
WRAP burst
End of enumeration elements list.
SBS_BUFF : Step By Step Buffered
bits : 12 - 12 (1 bit)
access : read-only
SBS_LEN : Step By Step Length
bits : 13 - 15 (3 bit)
access : read-only
Enumeration:
0 : SBS_LEN_0
burst of length 1
0x1 : SBS_LEN_1
burst of length 2
0x7 : SBS_LEN_7
burst of length 8
End of enumeration elements list.
SBS_AXI_ID : Step By Step AXI ID
bits : 16 - 31 (16 bit)
access : read-only
MMDC Core General Purpose Register
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GP31_GP0 : General purpose read/write bits.
bits : 0 - 31 (32 bit)
access : read-write
MMDC Core ODT Timing Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tODT_idle_off : ODT turn off latency
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : tODT_idle_off_0
0 cycle (turned off at the earliest possible time)
0x1 : tODT_idle_off_1
1 cycle
0x2 : tODT_idle_off_2
2 cycles
0x1E : tODT_idle_off_30
30 cycles
0x1F : tODT_idle_off_31
31 cycles
End of enumeration elements list.
tODTLon : ODT turn on latency
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : tODTLon_0
- 0x1 Reserved
0x2 : tODTLon_2
2 cycles
0x3 : tODTLon_3
3 cycles
0x4 : tODTLon_4
4 cycles
0x5 : tODTLon_5
5 cycles
0x6 : tODTLon_6
6 cycles
End of enumeration elements list.
tAXPD : Asynchronous ODT to power down exit delay
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : tAXPD_0
1 clock
0x1 : tAXPD_1
2 clocks
0x2 : tAXPD_2
3 clocks
0xE : tAXPD_14
15 clocks
0xF : tAXPD_15
16 clocks
End of enumeration elements list.
tANPD : Asynchronous ODT to power down entry delay
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0 : tANPD_0
1 clock
0x1 : tANPD_1
2 clocks
0x2 : tANPD_2
3 clocks
0xE : tANPD_14
15 clocks
0xF : tANPD_15
16 clocks
End of enumeration elements list.
tAONPD : Asynchronous RTT turn-on delay (power down with DLL frozen)
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : tAONPD_0
1 cycle
0x1 : tAONPD_1
2 cycles
0x6 : tAONPD_6
7 cycles
0x7 : tAONPD_7
8 cycles
End of enumeration elements list.
tAOFPD : Asynchronous RTT turn-off delay (power down with DLL frozen)
bits : 27 - 29 (3 bit)
access : read-write
Enumeration:
0 : tAOFPD_0
1 cycle
0x1 : tAOFPD_1
2 cycles
0x6 : tAOFPD_6
7 cycles
0x7 : tAOFPD_7
8 cycles
End of enumeration elements list.
MMDC PHY ZQ HW control register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZQ_MODE : ZQ calibration mode:
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ZQ_MODE_0
No ZQ calibration is issued. (Default)
0x1 : ZQ_MODE_1
ZQ calibration is issued to i.MX ZQ calibration pad together with ZQ long command to the external DDR device only when exiting self refresh.
0x2 : ZQ_MODE_2
ZQ calibration command long/short is issued only to the external DDR device periodically and when exiting self refresh
0x3 : ZQ_MODE_3
ZQ calibration is issued to i.MX ZQ calibration pad together with ZQ calibration command long/short to the external DDR device periodically and when exiting self refresh
End of enumeration elements list.
ZQ_HW_PER : ZQ periodic calibration time
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : ZQ_HW_PER_0
ZQ calibration is performed every 1 ms.
0x1 : ZQ_HW_PER_1
ZQ calibration is performed every 2 ms.
0x2 : ZQ_HW_PER_2
ZQ calibration is performed every 4 ms.
0xA : ZQ_HW_PER_10
ZQ calibration is performed every 1 sec.
0xE : ZQ_HW_PER_14
ZQ calibration is performed every 16 sec.
0xF : ZQ_HW_PER_15
ZQ calibration is performed every 32 sec.
End of enumeration elements list.
ZQ_HW_PU_RES : ZQ automatic calibration pull-up result
bits : 6 - 10 (5 bit)
access : read-only
Enumeration:
0 : ZQ_HW_PU_RES_0
Min. resistance.
0x1F : ZQ_HW_PU_RES_31
Max. resistance.
End of enumeration elements list.
ZQ_HW_PD_RES : ZQ HW calibration pull-down result
bits : 11 - 15 (5 bit)
access : read-only
Enumeration:
0 : ZQ_HW_PD_RES_0
Max. resistance.
0x1F : ZQ_HW_PD_RES_31
Min. resistance.
End of enumeration elements list.
ZQ_HW_FOR : Force ZQ automatic calibration process with the i
bits : 16 - 16 (1 bit)
access : read-write
TZQ_INIT : Device ZQ long/init time
bits : 17 - 19 (3 bit)
access : read-write
Enumeration:
0x2 : TZQ_INIT_2
128 cycles
0x3 : TZQ_INIT_3
256 cycles
0x4 : TZQ_INIT_4
512 cycles - Default (JEDEC value for DDR3)
0x5 : TZQ_INIT_5
1024 cycles
End of enumeration elements list.
TZQ_OPER : Device ZQ long/oper time
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0x2 : TZQ_OPER_2
128 cycles
0x3 : TZQ_OPER_3
256 cycles - Default (JEDEC value for DDR3)
0x4 : TZQ_OPER_4
512 cycles
0x5 : TZQ_OPER_5
1024 cycles
End of enumeration elements list.
TZQ_CS : Device ZQ short time
bits : 23 - 25 (3 bit)
access : read-write
Enumeration:
0x2 : TZQ_CS_2
128 cycles (Default)
0x3 : TZQ_CS_3
256 cycles
0x4 : TZQ_CS_4
512 cycles
0x5 : TZQ_CS_5
1024 cycles
End of enumeration elements list.
ZQ_EARLY_COMPARATOR_EN_TIMER : ZQ early comparator enable timer
bits : 27 - 31 (5 bit)
access : read-write
Enumeration:
0 : ZQ_EARLY_COMPARATOR_EN_TIMER_0
- 0x6 Reserved
0x7 : ZQ_EARLY_COMPARATOR_EN_TIMER_7
8 cycles
0x14 : ZQ_EARLY_COMPARATOR_EN_TIMER_20
21 cycles (Default)
0x1E : ZQ_EARLY_COMPARATOR_EN_TIMER_30
31 cycles
0x1F : ZQ_EARLY_COMPARATOR_EN_TIMER_31
32 cycles
End of enumeration elements list.
MMDC PHY ZQ SW control register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZQ_SW_FOR : ZQ SW calibration enable
bits : 0 - 0 (1 bit)
access : read-write
ZQ_SW_RES : ZQ software calibration result. This bit reflects the ZQ calibration voltage comparator value.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : ZQ_SW_RES_0
Current ZQ calibration voltage is less than VDD/2.
0x1 : ZQ_SW_RES_1
Current ZQ calibration voltage is more than VDD/2
End of enumeration elements list.
ZQ_SW_PU_VAL : ZQ software pull-up resistence
bits : 2 - 6 (5 bit)
access : read-write
Enumeration:
0 : ZQ_SW_PU_VAL_0
Min. resistance.
0x1F : ZQ_SW_PU_VAL_31
Max. resistance.
End of enumeration elements list.
ZQ_SW_PD_VAL : ZQ software pull-down resistence
bits : 7 - 11 (5 bit)
access : read-write
Enumeration:
0 : ZQ_SW_PD_VAL_0
Max. resistance.
0x1F : ZQ_SW_PD_VAL_31
Min. resistance.
End of enumeration elements list.
ZQ_SW_PD : ZQ software PU/PD calibration. This bit determines the calibration stage (PU or PD).
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : ZQ_SW_PD_0
PU resistor calibration
0x1 : ZQ_SW_PD_1
PD resistor calibration
End of enumeration elements list.
USE_ZQ_SW_VAL : Use SW ZQ configured value for I/O pads resistor controls
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : USE_ZQ_SW_VAL_0
Fields ZQ_HW_PD_VAL & ZQ_HW_PU_VAL will be driven to I/O pads resistor controls.
0x1 : USE_ZQ_SW_VAL_1
Fields ZQ_SW_PD_VAL & ZQ_SW_PU_VAL will be driven to I/O pads resistor controls.
End of enumeration elements list.
ZQ_CMP_OUT_SMP : Defines the amount of cycles between driving the ZQ signals to the ZQ pad and till sampling the comparator enable output while performing ZQ calibration process with the i
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ZQ_CMP_OUT_SMP_0
7 cycles
0x1 : ZQ_CMP_OUT_SMP_1
15 cycles
0x2 : ZQ_CMP_OUT_SMP_2
23 cycles
0x3 : ZQ_CMP_OUT_SMP_3
31 cycles
End of enumeration elements list.
MMDC PHY Write Leveling Configuration and Error Status Register
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HW_WL_EN : Write-Leveling HW (automatic) enable
bits : 0 - 0 (1 bit)
access : read-write
SW_WL_EN : Write-Leveling SW enable
bits : 1 - 1 (1 bit)
access : read-write
SW_WL_CNT_EN : SW write-leveling count down enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SW_WL_CNT_EN_0
MMDC doesn't count 25+15 cycles before issuing write-leveling DQS.
0x1 : SW_WL_CNT_EN_1
MMDC counts 25+15 cycles before issuing write-leveling DQS.
End of enumeration elements list.
WL_SW_RES0 : Byte0 write-leveling software result
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : WL_SW_RES0_0
DQS0 sampled low CK during SW write-leveling.
0x1 : WL_SW_RES0_1
DQS0 sampled high CK during SW write-leveling.
End of enumeration elements list.
WL_SW_RES1 : Byte1 write-leveling software result
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : WL_SW_RES1_0
DQS1 sampled low CK during SW write-leveling.
0x1 : WL_SW_RES1_1
DQS1 sampled high CK during SW write-leveling.
End of enumeration elements list.
WL_HW_ERR0 : Byte0 write-leveling HW calibration error
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : WL_HW_ERR0_0
No error was found on byte0 during write-leveling HW calibration.
0x1 : WL_HW_ERR0_1
An error was found on byte0 during write-leveling HW calibration.
End of enumeration elements list.
WL_HW_ERR1 : Byte1 write-leveling HW calibration error
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : WL_HW_ERR1_0
No error was found on byte1 during write-leveling HW calibration.
0x1 : WL_HW_ERR1_1
An error was found on byte1 during write-leveling HW calibration.
End of enumeration elements list.
MMDC PHY Write Leveling Delay Control Register 0
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WL_DL_ABS_OFFSET0 : Absolute write-leveling delay offset for Byte 0
bits : 0 - 6 (7 bit)
access : read-write
WL_HC_DEL0 : Write leveling half cycle delay for Byte 0
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : WL_HC_DEL0_0
No delay is added.
0x1 : WL_HC_DEL0_1
Half cycle delay is added.
End of enumeration elements list.
WL_CYC_DEL0 : Write leveling cycle delay for Byte 0
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
0 : WL_CYC_DEL0_0
No delay is added.
0x1 : WL_CYC_DEL0_1
1 cycle delay is added.
0x2 : WL_CYC_DEL0_2
2 cycles delay is added.
End of enumeration elements list.
WL_DL_ABS_OFFSET1 : Absolute write-leveling delay offset for Byte 1
bits : 16 - 22 (7 bit)
access : read-write
WL_HC_DEL1 : Write leveling half cycle delay for Byte 1
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : WL_HC_DEL1_0
No delay is added.
0x1 : WL_HC_DEL1_1
Half cycle delay is added.
End of enumeration elements list.
WL_CYC_DEL1 : Write leveling cycle delay for Byte 1
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0 : WL_CYC_DEL1_0
No delay is added.
0x1 : WL_CYC_DEL1_1
1 cycle delay is added.
0x2 : WL_CYC_DEL1_2
2 cycles delay is added.
End of enumeration elements list.
MMDC PHY Write Leveling delay-line Status Register
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WL_DL_UNIT_NUM0 : This field reflects the number of delay units that are actually used by write leveling delay-line 0
bits : 0 - 6 (7 bit)
access : read-only
WL_DL_UNIT_NUM1 : This field reflects the number of delay units that are actually used by write leveling delay-line 1
bits : 8 - 14 (7 bit)
access : read-only
MMDC PHY ODT control register
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ODT_WR_PAS_EN : Inactive write CS ODT enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ODT_WR_PAS_EN_0
Inactive CS ODT pin is disabled during write accesses to other CS.
0x1 : ODT_WR_PAS_EN_1
Inactive CS ODT pin is enabled during write accesses to other CS.
End of enumeration elements list.
ODT_WR_ACT_EN : Active write CS ODT enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ODT_WR_ACT_EN_0
Active CS ODT pin is disabled during write access.
0x1 : ODT_WR_ACT_EN_1
Active CS ODT pin is enabled during write access.
End of enumeration elements list.
ODT_RD_PAS_EN : Inactive read CS ODT enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ODT_RD_PAS_EN_0
Inactive CS ODT pin is disabled during read accesses to other CS.
0x1 : ODT_RD_PAS_EN_1
Inactive CS ODT pin is enabled during read accesses to other CS.
End of enumeration elements list.
ODT_RD_ACT_EN : Active read CS ODT enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : ODT_RD_ACT_EN_0
Active CS ODT pin is disabled during read access.
0x1 : ODT_RD_ACT_EN_1
Active CS ODT pin is enabled during read access.
End of enumeration elements list.
ODT0_INT_RES : On chip ODT byte0 resistor - This field determines the Rtt_Nom of the on chip ODT byte0 resistor during read accesses
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : ODT0_INT_RES_0
Rtt_Nom Disabled.
0x1 : ODT0_INT_RES_1
Rtt_Nom 120 Ohm
0x2 : ODT0_INT_RES_2
Rtt_Nom 60 Ohm
0x3 : ODT0_INT_RES_3
Rtt_Nom 40 Ohm
0x4 : ODT0_INT_RES_4
Rtt_Nom 30 Ohm
0x5 : ODT0_INT_RES_5
Rtt_Nom 24 Ohm
0x6 : ODT0_INT_RES_6
Rtt_Nom 20 Ohm
0x7 : ODT0_INT_RES_7
Rtt_Nom 17 Ohm
End of enumeration elements list.
ODT1_INT_RES : On chip ODT byte1 resistor - This field determines the Rtt_Nom of the on chip ODT byte1 resistor during read accesses
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : ODT1_INT_RES_0
Rtt_Nom Disabled.
0x1 : ODT1_INT_RES_1
Rtt_Nom 120 Ohm
0x2 : ODT1_INT_RES_2
Rtt_Nom 60 Ohm
0x3 : ODT1_INT_RES_3
Rtt_Nom 40 Ohm
0x4 : ODT1_INT_RES_4
Rtt_Nom 30 Ohm
0x5 : ODT1_INT_RES_5
Rtt_Nom 24 Ohm
0x6 : ODT1_INT_RES_6
Rtt_Nom 20 Ohm
0x7 : ODT1_INT_RES_7
Rtt_Nom 17 Ohm
End of enumeration elements list.
MMDC PHY Read DQ Byte0 Delay Register
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_dq0_del : Read dqs0 to dq0 delay fine-tuning
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : rd_dq0_del_0
No change in dq0 delay
0x1 : rd_dq0_del_1
Add dq0 delay of 1 delay unit
0x2 : rd_dq0_del_2
Add dq0 delay of 2 delay units.
0x3 : rd_dq0_del_3
Add dq0 delay of 3 delay units.
0x4 : rd_dq0_del_4
Add dq0 delay of 4 delay units.
0x5 : rd_dq0_del_5
Add dq0 delay of 5 delay units.
0x6 : rd_dq0_del_6
Add dq0 delay of 6 delay units.
0x7 : rd_dq0_del_7
Add dq0 delay of 7 delay units.
End of enumeration elements list.
rd_dq1_del : Read dqs0 to dq1 delay fine-tuning
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : rd_dq1_del_0
No change in dq1 delay
0x1 : rd_dq1_del_1
Add dq1 delay of 1 delay unit
0x2 : rd_dq1_del_2
Add dq1 delay of 2 delay units.
0x3 : rd_dq1_del_3
Add dq1 delay of 3 delay units.
0x4 : rd_dq1_del_4
Add dq1 delay of 4 delay units.
0x5 : rd_dq1_del_5
Add dq1 delay of 5 delay units.
0x6 : rd_dq1_del_6
Add dq1 delay of 6 delay units.
0x7 : rd_dq1_del_7
Add dq1 delay of 7 delay units.
End of enumeration elements list.
rd_dq2_del : Read dqs0 to dq2 delay fine-tuning
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : rd_dq2_del_0
No change in dq2 delay
0x1 : rd_dq2_del_1
Add dq2 delay of 1 delay unit
0x2 : rd_dq2_del_2
Add dq2 delay of 2 delay units.
0x3 : rd_dq2_del_3
Add dq2 delay of 3 delay units.
0x4 : rd_dq2_del_4
Add dq2 delay of 4 delay units.
0x5 : rd_dq2_del_5
Add dq2 delay of 5 delay units.
0x6 : rd_dq2_del_6
Add dq2 delay of 6 delay units.
0x7 : rd_dq2_del_7
Add dq2 delay of 7 delay units.
End of enumeration elements list.
rd_dq3_del : Read dqs0 to dq3 delay fine-tuning
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : rd_dq3_del_0
No change in dq3 delay
0x1 : rd_dq3_del_1
Add dq3 delay of 1 delay unit
0x2 : rd_dq3_del_2
Add dq3 delay of 2 delay units.
0x3 : rd_dq3_del_3
Add dq3 delay of 3 delay units.
0x4 : rd_dq3_del_4
Add dq3 delay of 4 delay units.
0x5 : rd_dq3_del_5
Add dq3 delay of 5 delay units.
0x6 : rd_dq3_del_6
Add dq3 delay of 6 delay units.
0x7 : rd_dq3_del_7
Add dq3 delay of 7 delay units.
End of enumeration elements list.
rd_dq4_del : Read dqs0 to dq4 delay fine-tuning
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : rd_dq4_del_0
No change in dq4 delay
0x1 : rd_dq4_del_1
Add dq4 delay of 1 delay unit
0x2 : rd_dq4_del_2
Add dq4 delay of 2 delay units.
0x3 : rd_dq4_del_3
Add dq4 delay of 3 delay units.
0x4 : rd_dq4_del_4
Add dq4 delay of 4 delay units.
0x5 : rd_dq4_del_5
Add dq4 delay of 5 delay units.
0x6 : rd_dq4_del_6
Add dq4 delay of 6 delay units.
0x7 : rd_dq4_del_7
Add dq4 delay of 7 delay units.
End of enumeration elements list.
rd_dq5_del : Read dqs0 to dq5 delay fine-tuning
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : rd_dq5_del_0
No change in dq5 delay
0x1 : rd_dq5_del_1
Add dq5 delay of 1 delay unit
0x2 : rd_dq5_del_2
Add dq5 delay of 2 delay units.
0x3 : rd_dq5_del_3
Add dq5 delay of 3 delay units.
0x4 : rd_dq5_del_4
Add dq5 delay of 4 delay units.
0x5 : rd_dq5_del_5
Add dq5 delay of 5 delay units.
0x6 : rd_dq5_del_6
Add dq5 delay of 6 delay units.
0x7 : rd_dq5_del_7
Add dq5 delay of 7 delay units.
End of enumeration elements list.
rd_dq6_del : Read dqs0 to dq6 delay fine-tuning
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : rd_dq6_del_0
No change in dq6 delay
0x1 : rd_dq6_del_1
Add dq6 delay of 1 delay unit
0x2 : rd_dq6_del_2
Add dq6 delay of 2 delay units.
0x3 : rd_dq6_del_3
Add dq6 delay of 3 delay units.
0x4 : rd_dq6_del_4
Add dq6 delay of 4 delay units.
0x5 : rd_dq6_del_5
Add dq6 delay of 5 delay units.
0x6 : rd_dq6_del_6
Add dq6 delay of 6 delay units.
0x7 : rd_dq6_del_7
Add dq6 delay of 7 delay units.
End of enumeration elements list.
rd_dq7_del : Read dqs0 to dq7 delay fine-tuning
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
0 : rd_dq7_del_0
No change in dq7 delay
0x1 : rd_dq7_del_1
Add dq7 delay of 1 delay unit
0x2 : rd_dq7_del_2
Add dq7 delay of 2 delay units.
0x3 : rd_dq7_del_3
Add dq7 delay of 3 delay units.
0x4 : rd_dq7_del_4
Add dq7 delay of 4 delay units.
0x5 : rd_dq7_del_5
Add dq7 delay of 5 delay units.
0x6 : rd_dq7_del_6
Add dq7 delay of 6 delay units.
0x7 : rd_dq7_del_7
Add dq7 delay of 7 delay units.
End of enumeration elements list.
MMDC PHY Read DQ Byte1 Delay Register
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_dq8_del : Read dqs1 to dq8 delay fine-tuning
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : rd_dq8_del_0
No change in dq8 delay
0x1 : rd_dq8_del_1
Add dq8 delay of 1 delay unit
0x2 : rd_dq8_del_2
Add dq8 delay of 2 delay units.
0x3 : rd_dq8_del_3
Add dq8 delay of 3 delay units.
0x4 : rd_dq8_del_4
Add dq8 delay of 4 delay units.
0x5 : rd_dq8_del_5
Add dq8 delay of 5 delay units.
0x6 : rd_dq8_del_6
Add dq8 delay of 6 delay units.
0x7 : rd_dq8_del_7
Add dq8 delay of 7 delay units.
End of enumeration elements list.
rd_dq9_del : Read dqs1 to dq9 delay fine-tuning
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : rd_dq9_del_0
No change in dq9 delay
0x1 : rd_dq9_del_1
Add dq9 delay of 1 delay unit
0x2 : rd_dq9_del_2
Add dq9 delay of 2 delay units.
0x3 : rd_dq9_del_3
Add dq9 delay of 3 delay units.
0x4 : rd_dq9_del_4
Add dq9 delay of 4 delay units.
0x5 : rd_dq9_del_5
Add dq9 delay of 5 delay units.
0x6 : rd_dq9_del_6
Add dq9 delay of 6 delay units.
0x7 : rd_dq9_del_7
Add dq9 delay of 7 delay units.
End of enumeration elements list.
rd_dq10_del : Read dqs1 to dq10 delay fine-tuning
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : rd_dq10_del_0
No change in dq10 delay
0x1 : rd_dq10_del_1
Add dq10 delay of 1 delay unit
0x2 : rd_dq10_del_2
Add dq10 delay of 2 delay units.
0x3 : rd_dq10_del_3
Add dq10 delay of 3 delay units.
0x4 : rd_dq10_del_4
Add dq10 delay of 4 delay units.
0x5 : rd_dq10_del_5
Add dq10 delay of 5 delay unit
0x6 : rd_dq10_del_6
Add dq10 delay of 6 delay units.
0x7 : rd_dq10_del_7
Add dq10 delay of 7 delay units.
End of enumeration elements list.
rd_dq11_del : Read dqs1 to dq11 delay fine-tuning
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : rd_dq11_del_0
No change in dq11 delay
0x1 : rd_dq11_del_1
Add dq11 delay of 1 delay unit
0x2 : rd_dq11_del_2
Add dq11 delay of 2 delay units.
0x3 : rd_dq11_del_3
Add dq11 delay of 3 delay units.
0x4 : rd_dq11_del_4
Add dq11 delay of 4 delay units.
0x5 : rd_dq11_del_5
Add dq11 delay of 5 delay units.
0x6 : rd_dq11_del_6
Add dq11 delay of 6 delay units.
0x7 : rd_dq11_del_7
Add dq11 delay of 7 delay units.
End of enumeration elements list.
rd_dq12_del : Read dqs1 to dq12 delay fine-tuning
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : rd_dq12_del_0
No change in dq12 delay
0x1 : rd_dq12_del_1
Add dq12 delay of 1 delay unit
0x2 : rd_dq12_del_2
Add dq12 delay of 2 delay units.
0x3 : rd_dq12_del_3
Add dq12 delay of 3 delay units.
0x4 : rd_dq12_del_4
Add dq12 delay of 4 delay units.
0x5 : rd_dq12_del_5
Add dq12 delay of 5 delay units.
0x6 : rd_dq12_del_6
Add dq12 delay of 6 delay units.
0x7 : rd_dq12_del_7
Add dq12 delay of 7 delay units.
End of enumeration elements list.
rd_dq13_del : Read dqs1 to dq13 delay fine-tuning
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : rd_dq13_del_0
No change in dq13 delay
0x1 : rd_dq13_del_1
Add dq13 delay of 1 delay unit
0x2 : rd_dq13_del_2
Add dq13 delay of 2 delay units.
0x3 : rd_dq13_del_3
Add dq13 delay of 3 delay units.
0x4 : rd_dq13_del_4
Add dq13 delay of 4 delay units.
0x5 : rd_dq13_del_5
Add dq13 delay of 5 delay units.
0x6 : rd_dq13_del_6
Add dq13 delay of 6 delay units.
0x7 : rd_dq13_del_7
Add dq13 delay of 7 delay units.
End of enumeration elements list.
rd_dq14_del : Read dqs1 to dq14 delay fine-tuning
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : rd_dq14_del_0
No change in dq14 delay
0x1 : rd_dq14_del_1
Add dq14 delay of 1 delay unit
0x2 : rd_dq14_del_2
Add dq14 delay of 2 delay units.
0x3 : rd_dq14_del_3
Add dq14 delay of 3 delay units.
0x4 : rd_dq14_del_4
Add dq14 delay of 4 delay units.
0x5 : rd_dq14_del_5
Add dq14 delay of 5 delay units.
0x6 : rd_dq14_del_6
Add dq14 delay of 6 delay units.
0x7 : rd_dq14_del_7
Add dq14 delay of 7 delay units.
End of enumeration elements list.
rd_dq15_del : Read dqs1 to dq15 delay fine-tuning
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
0 : rd_dq15_del_0
No change in dq15 delay
0x1 : rd_dq15_del_1
Add dq15 delay of 1 delay unit
0x2 : rd_dq15_del_2
Add dq15 delay of 2 delay units.
0x3 : rd_dq15_del_3
Add dq15 delay of 3 delay units.
0x4 : rd_dq15_del_4
Add dq15 delay of 4 delay units.
0x5 : rd_dq15_del_5
Add dq15 delay of 5 delay units.
0x6 : rd_dq15_del_6
Add dq15 delay of 6 delay units.
0x7 : rd_dq15_del_7
Add dq15 delay of 7 delay units.
End of enumeration elements list.
MMDC PHY Write DQ Byte0 Delay Register
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wr_dq0_del : Write dq0 delay fine-tuning
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : wr_dq0_del_0
No change in dq0 delay
0x1 : wr_dq0_del_1
Add dq0 delay of 1 delay unit.
0x2 : wr_dq0_del_2
Add dq0 delay of 2 delay units.
0x3 : wr_dq0_del_3
Add dq0 delay of 3 delay units.
End of enumeration elements list.
wr_dq1_del : Write dq1 delay fine-tuning
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : wr_dq1_del_0
No change in dq1 delay
0x1 : wr_dq1_del_1
Add dq1 delay of 1 delay unit.
0x2 : wr_dq1_del_2
Add dq1 delay of 2 delay units.
0x3 : wr_dq1_del_3
Add dq1 delay of 3 delay units.
End of enumeration elements list.
wr_dq2_del : Write dq2 delay fine-tuning
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : wr_dq2_del_0
No change in dq2 delay
0x1 : wr_dq2_del_1
Add dq2 delay of 1 delay unit.
0x2 : wr_dq2_del_2
Add dq2 delay of 2 delay units.
0x3 : wr_dq2_del_3
Add dq2 delay of 3 delay units.
End of enumeration elements list.
wr_dq3_del : Write dq3 delay fine-tuning
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : wr_dq3_del_0
No change in dq3 delay
0x1 : wr_dq3_del_1
Add dq3 delay of 1 delay unit.
0x2 : wr_dq3_del_2
Add dq3 delay of 2 delay units.
0x3 : wr_dq3_del_3
Add dq3 delay of 3 delay units.
End of enumeration elements list.
wr_dq4_del : Write dq4 delay fine-tuning
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : wr_dq4_del_0
No change in dq4 delay
0x1 : wr_dq4_del_1
Add dq4 delay of 1 delay unit..
0x2 : wr_dq4_del_2
Add dq4 delay of 2 delay units.
0x3 : wr_dq4_del_3
Add dq4 delay of 3 delay units.
End of enumeration elements list.
wr_dq5_del : Write dq5 delay fine-tuning
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : wr_dq5_del_0
No change in dq5 delay
0x1 : wr_dq5_del_1
Add dq5 delay of 1 delay unit.
0x2 : wr_dq5_del_2
Add dq5 delay of 2 delay units.
0x3 : wr_dq5_del_3
Add dq5 delay of 3 delay units.
End of enumeration elements list.
wr_dq6_del : Write dq6 delay fine-tuning
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : wr_dq6_del_0
No change in dq6 delay
0x1 : wr_dq6_del_1
Add dq6 delay of 1 delay unit.
0x2 : wr_dq6_del_2
Add dq6 delay of 2 delay units.
0x3 : wr_dq6_del_3
Add dq6 delay of 3 delay units.
End of enumeration elements list.
wr_dq7_del : Write dq7 delay fine-tuning
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : wr_dq7_del_0
No change in dq7 delay
0x1 : wr_dq7_del_1
Add dq7 delay of 1 delay unit.
0x2 : wr_dq7_del_2
Add dq7 delay of 2 delay units.
0x3 : wr_dq7_del_3
Add dq7 delay of 3 delay units.
End of enumeration elements list.
wr_dm0_del : Write dm0 delay fine-tuning
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : wr_dm0_del_0
No change in dm0 delay
0x1 : wr_dm0_del_1
Add dm0 delay of 1 delay unit.
0x2 : wr_dm0_del_2
Add dm0 delay of 2 delay units.
0x3 : wr_dm0_del_3
Add dm0 delay of 3 delay units.
End of enumeration elements list.
MMDC PHY Write DQ Byte1 Delay Register
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wr_dq8_del : Write dq8 delay fine-tuning
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : wr_dq8_del_0
No change in dq8 delay
0x1 : wr_dq8_del_1
Add dq8 delay of 1 delay unit.
0x2 : wr_dq8_del_2
Add dq8 delay of 2 delay units.
0x3 : wr_dq8_del_3
Add dq8 delay of 3 delay units.
End of enumeration elements list.
wr_dq9_del : Write dq9 delay fine-tuning
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : wr_dq9_del_0
No change in dq9 delay
0x1 : wr_dq9_del_1
Add dq9 delay of 1 delay unit.
0x2 : wr_dq9_del_2
Add dq9 delay of 2 delay units.
0x3 : wr_dq9_del_3
Add dq9 delay of 3 delay units.
End of enumeration elements list.
wr_dq10_del : Write dq10 delay fine-tuning
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : wr_dq10_del_0
No change in dq10 delay
0x1 : wr_dq10_del_1
Add dq10 delay of 1 delay unit.
0x2 : wr_dq10_del_2
Add dq10 delay of 2 delay units.
0x3 : wr_dq10_del_3
Add dq10 delay of 3 delay units.
End of enumeration elements list.
wr_dq11_del : Write dq11 delay fine-tuning
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : wr_dq11_del_0
No change in dq11 delay
0x1 : wr_dq11_del_1
Add dq11 delay of 1 delay unit.
0x2 : wr_dq11_del_2
Add dq11 delay of 2 delay units.
0x3 : wr_dq11_del_3
Add dq11 delay of 3 delay units.
End of enumeration elements list.
wr_dq12_del : Write dq12 delay fine-tuning
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : wr_dq12_del_0
No change in dq12 delay
0x1 : wr_dq12_del_1
Add dq12 delay of 1 delay unit.
0x2 : wr_dq12_del_2
Add dq12 delay of 2 delay units.
0x3 : wr_dq12_del_3
Add dq12 delay of 3 delay units.
End of enumeration elements list.
wr_dq13_del : Write dq13 delay fine-tuning
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : wr_dq13_del_0
No change in dq13 delay
0x1 : wr_dq13_del_1
Add dq13 delay of 1 delay unit.
0x2 : wr_dq13_del_2
Add dq13 delay of 2 delay units.
0x3 : wr_dq13_del_3
Add dq13 delay of 3 delay units.
End of enumeration elements list.
wr_dq14_del : Write dq14 delay fine-tuning
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : wr_dq14_del_0
No change in dq14 delay
0x1 : wr_dq14_del_1
Add dq14 delay of 1 delay unit.
0x2 : wr_dq14_del_2
Add dq14 delay of 2 delay units.
0x3 : wr_dq14_del_3
Add dq14 delay of 3 delay units.
End of enumeration elements list.
wr_dq15_del : Write dq15 delay fine-tuning
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : wr_dq15_del_0
No change in dq15 delay
0x1 : wr_dq15_del_1
Add dq15 delay of 1 delay unit.
0x2 : wr_dq15_del_2
Add dq15 delay of 2 delay units.
0x3 : wr_dq15_del_3
Add dq15 delay of 3 delay units.
End of enumeration elements list.
wr_dm1_del : Write dm1 delay fine-tuning
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : wr_dm1_del_0
No change in dm1 delay
0x1 : wr_dm1_del_1
Add dm1 delay of 1 delay unit.
0x2 : wr_dm1_del_2
Add dm1 delay of 2 delay units.
0x3 : wr_dm1_del_3
Add dm1 delay of 3 delay units.
End of enumeration elements list.
MMDC PHY Write DQ Byte2 Delay Register
address_offset : 0x834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wr_dq16_del : Write dq16 delay fine tuning
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : wr_dq16_del_0
No change in dq16 delay
0x1 : wr_dq16_del_1
Add dq16 delay of 1 delay unit.
0x2 : wr_dq16_del_2
Add dq16 delay of 2 delay units.
0x3 : wr_dq16_del_3
Add dq16 delay of 3 delay units.
End of enumeration elements list.
wr_dq17_del : Write dq17 delay fine tuning
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : wr_dq17_del_0
No change in dq17 delay
0x1 : wr_dq17_del_1
Add dq17 delay of 1 delay unit.
0x2 : wr_dq17_del_2
Add dq17 delay of 2 delay units.
0x3 : wr_dq17_del_3
Add dq17 delay of 3 delay units.
End of enumeration elements list.
wr_dq18_del : Write dq18 delay fine tuning
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : wr_dq18_del_0
No change in dq18 delay
0x1 : wr_dq18_del_1
Add dq18 delay of 1 delay unit.
0x2 : wr_dq18_del_2
Add dq18 delay of 2 delay units.
0x3 : wr_dq18_del_3
Add dq18 delay of 3 delay units.
End of enumeration elements list.
wr_dq19_del : Write dq19 delay fine tuning
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : wr_dq19_del_0
No change in dq19 delay
0x1 : wr_dq19_del_1
Add dq19 delay of 1 delay unit.
0x2 : wr_dq19_del_2
Add dq19 delay of 2 delay units.
0x3 : wr_dq19_del_3
Add dq19 delay of 3 delay units.
End of enumeration elements list.
wr_dq20_del : Write dq20 delay fine tuning
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : wr_dq20_del_0
No change in dq20 delay
0x1 : wr_dq20_del_1
Add dq20 delay of 1 delay unit.
0x2 : wr_dq20_del_2
Add dq20 delay of 2 delay units.
0x3 : wr_dq20_del_3
Add dq20 delay of 3 delay units.
End of enumeration elements list.
wr_dq21_del : Write dq21 delay fine tuning
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : wr_dq21_del_0
No change in dq21 delay
0x1 : wr_dq21_del_1
Add dq21 delay of 1 delay unit.
0x2 : wr_dq21_del_2
Add dq21 delay of 2 delay units.
0x3 : wr_dq21_del_3
Add dq21 delay of 3 delay units.
End of enumeration elements list.
wr_dq22_del : Write dq22 delay fine tuning
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : wr_dq22_del_0
No change in dq22 delay
0x1 : wr_dq22_del_1
Add dq22 delay of 1 delay unit.
0x2 : wr_dq22_del_2
Add dq22 delay of 2 delay units.
0x3 : wr_dq22_del_3
Add dq22 delay of 3 delay units.
End of enumeration elements list.
wr_dq23_del : Write dq23 delay fine tuning
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : wr_dq23_del_0
No change in dq23 delay
0x1 : wr_dq23_del_1
Add dq23 delay of 1 delay unit.
0x2 : wr_dq23_del_2
Add dq23 delay of 2 delay units.
0x3 : wr_dq23_del_3
Add dq23 delay of 3 delay units.
End of enumeration elements list.
wr_dm2_del : Write dm2 delay fine-tuning
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : wr_dm2_del_0
No change in dm2 delay
0x1 : wr_dm2_del_1
Add dm2 delay of 1 delay unit.
0x2 : wr_dm2_del_2
Add dm2 delay of 2 delay units.
0x3 : wr_dm2_del_3
Add dm2 delay of 3 delay units.
End of enumeration elements list.
MMDC PHY Write DQ Byte3 Delay Register
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wr_dq24_del : Write dq24 delay fine tuning
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : wr_dq24_del_0
No change in dq24 delay
0x1 : wr_dq24_del_1
Add dq24 delay of 1 delay unit.
0x2 : wr_dq24_del_2
Add dq24 delay of 2 delay units.
0x3 : wr_dq24_del_3
Add dq24 delay of 3 delay units.
End of enumeration elements list.
wr_dq25_del : Write dq25 delay fine tuning
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : wr_dq25_del_0
No change in dq25 delay
0x1 : wr_dq25_del_1
Add dq25 delay of 1 delay unit.
0x2 : wr_dq25_del_2
Add dq25 delay of 2 delay units.
0x3 : wr_dq25_del_3
Add dq25 delay of 3 delay units.
End of enumeration elements list.
wr_dq26_del : Write dq26 delay fine tuning
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : wr_dq26_del_0
No change in dq26 delay
0x1 : wr_dq26_del_1
Add dq26 delay of 1 delay unit.
0x2 : wr_dq26_del_2
Add dq26 delay of 2 delay units.
0x3 : wr_dq26_del_3
Add dq26 delay of 3 delay units.
End of enumeration elements list.
wr_dq27_del : Write dq27 delay fine tuning
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : wr_dq27_del_0
No change in dq27 delay
0x1 : wr_dq27_del_1
Add dq27 delay of 1 delay unit.
0x2 : wr_dq27_del_2
Add dq27 delay of 2 delay units.
0x3 : wr_dq27_del_3
Add dq27 delay of 3 delay units.
End of enumeration elements list.
wr_dq28_del : Write dq28 delay fine tuning
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : wr_dq28_del_0
No change in dq28 delay
0x1 : wr_dq28_del_1
Add dq28 delay of 1 delay unit.
0x2 : wr_dq28_del_2
Add dq28 delay of 2 delay units.
0x3 : wr_dq28_del_3
Add dq28 delay of 3 delay units.
End of enumeration elements list.
wr_dq29_del : Write dq29 delay fine tuning
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : wr_dq29_del_0
No change in dq29 delay
0x1 : wr_dq29_del_1
Add dq29 delay of 1 delay unit.
0x2 : wr_dq29_del_2
Add dq29 delay of 2 delay units.
0x3 : wr_dq29_del_3
Add dq29 delay of 3 delay units.
End of enumeration elements list.
wr_dq30_del : Write dq30 delay fine tuning
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : wr_dq30_del_0
No change in dq30 delay
0x1 : wr_dq30_del_1
Add dq30 delay of 1 delay unit.
0x2 : wr_dq30_del_2
Add dq30 delay of 2 delay units.
0x3 : wr_dq30_del_3
Add dq30 delay of 3 delay units.
End of enumeration elements list.
wr_dq31_del : Write dq31 delay fine tuning
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : wr_dq31_del_0
No change in dq31 delay
0x1 : wr_dq31_del_1
Add dq31 delay of 1 delay unit.
0x2 : wr_dq31_del_2
Add dq31 delay of 2 delay units.
0x3 : wr_dq31_del_3
Add dq31 delay of 3 delay units.
End of enumeration elements list.
wr_dm3_del : Write dm3 delay fine tuning
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : wr_dm3_del_0
No change in dm3 delay
0x1 : wr_dm3_del_1
Add dm3 delay of 1 delay unit.
0x2 : wr_dm3_del_2
Add dm3 delay of 2 delay units.
0x3 : wr_dm3_del_3
Add dm3 delay of 3 delay units.
End of enumeration elements list.
MMDC PHY Read DQS Gating Control Register 0
address_offset : 0x83C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DG_DL_ABS_OFFSET0 : Absolute read DQS gating delay offset for Byte0
bits : 0 - 6 (7 bit)
access : read-write
DG_HC_DEL0 : Read DQS gating half cycles delay for Byte0
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : DG_HC_DEL0_0
0 cycles delay.
0x1 : DG_HC_DEL0_1
Half cycle delay.
0x2 : DG_HC_DEL0_2
1 cycle delay
0xD : DG_HC_DEL0_13
6.5 cycles delay
End of enumeration elements list.
HW_DG_ERR : HW DQS gating error
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : HW_DG_ERR_0
No error was found during the DQS gating HW calibration process.
0x1 : HW_DG_ERR_1
An error was found during the DQS gating HW calibration process.
End of enumeration elements list.
DG_DL_ABS_OFFSET1 : Absolute read DQS gating delay offset for Byte1
bits : 16 - 22 (7 bit)
access : read-write
DG_EXT_UP : DG extend upper boundary
bits : 23 - 23 (1 bit)
access : read-write
DG_HC_DEL1 : Read DQS gating half cycles delay for Byte1
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : DG_HC_DEL1_0
0 cycles delay.
0x1 : DG_HC_DEL1_1
Half cycle delay.
0x2 : DG_HC_DEL1_2
1 cycle delay
0xD : DG_HC_DEL1_13
6.5 cycles delay
End of enumeration elements list.
HW_DG_EN : Enable automatic read DQS gating calibration
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : HW_DG_EN_0
Disable automatic read DQS gating calibration
0x1 : HW_DG_EN_1
Start automatic read DQS gating calibration
End of enumeration elements list.
DG_DIS : Read DQS gating disable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DG_DIS_0
Read DQS gating mechanism is enabled
0x1 : DG_DIS_1
Read DQS gating mechanism is disabled
End of enumeration elements list.
DG_CMP_CYC : Read DQS gating sample cycle
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DG_CMP_CYC_0
MMDC waits 16 DDR cycles
0x1 : DG_CMP_CYC_1
MMDC waits 32 DDR cycles
End of enumeration elements list.
RST_RD_FIFO : Reset Read Data FIFO and associated pointers
bits : 31 - 31 (1 bit)
access : read-write
MMDC PHY Read DQS Gating delay-line Status Register
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DG_DL_UNIT_NUM0 : This field reflects the number of delay units that are actually used by read DQS gating delay-line 0
bits : 0 - 6 (7 bit)
access : read-only
DG_DL_UNIT_NUM1 : This field reflects the number of delay units that are actually used by read DQS gating delay-line 1
bits : 8 - 14 (7 bit)
access : read-only
MMDC PHY Read delay-lines Configuration Register
address_offset : 0x848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_DL_ABS_OFFSET0 : Absolute read delay offset for Byte0
bits : 0 - 6 (7 bit)
access : read-write
RD_DL_ABS_OFFSET1 : Absolute read delay offset for Byte1
bits : 8 - 14 (7 bit)
access : read-write
MMDC PHY Read delay-lines Status Register
address_offset : 0x84C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD_DL_UNIT_NUM0 : This field reflects the number of delay units that are actually used by read delay-line 0.
bits : 0 - 6 (7 bit)
access : read-only
RD_DL_UNIT_NUM1 : This field reflects the number of delay units that are actually used by read delay-line 1.
bits : 8 - 14 (7 bit)
access : read-only
MMDC PHY Write delay-lines Configuration Register
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR_DL_ABS_OFFSET0 : Absolute write delay offset for Byte0
bits : 0 - 6 (7 bit)
access : read-write
WR_DL_ABS_OFFSET1 : Absolute write delay offset for Byte1
bits : 8 - 14 (7 bit)
access : read-write
MMDC PHY Write delay-lines Status Register
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WR_DL_UNIT_NUM0 : This field reflects the number of delay units that are actually used by write delay-line 0.
bits : 0 - 6 (7 bit)
access : read-only
WR_DL_UNIT_NUM1 : This field reflects the number of delay units that are actually used by write delay-line 1.
bits : 8 - 14 (7 bit)
access : read-only
MMDC PHY CK Control Register
address_offset : 0x858 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDclk0_del : DDR clock0 delay fine tuning
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : SDclk0_del_0
No change in DDR clock0 delay
0x1 : SDclk0_del_1
Add DDR clock0 delay of 1 delay unit.
0x2 : SDclk0_del_2
Add DDR clock0 delay of 2 delay units.
0x3 : SDclk0_del_3
Add DDR clock0 delay of 3 delay units.
End of enumeration elements list.
SDCLK1_del : DDR clock1 delay fine tuning
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : SDCLK1_del_0
No change in DDR clock delay
0x1 : SDCLK1_del_1
Add DDR clock delay of 1 delay unit.
0x2 : SDCLK1_del_2
Add DDR clock delay of 2 delay units.
0x3 : SDCLK1_del_3
Add DDR clock delay of 3 delay units.
End of enumeration elements list.
MMDC ZQ LPDDR2 HW Control Register
address_offset : 0x85C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZQ_LP2_HW_ZQINIT : This register defines the period in cycles that it takes the memory device to perform a Init ZQ calibration
bits : 0 - 8 (9 bit)
access : read-write
Enumeration:
0x37 : ZQ_LP2_HW_ZQINIT_55
112 cycles
0x38 : ZQ_LP2_HW_ZQINIT_56
114 cycles
0x109 : ZQ_LP2_HW_ZQINIT_265
532 cycles (Default, JEDEC value, tZQINIT, for LPDDR2, 1us @ clock frequency 533MHz)
0x1FE : ZQ_LP2_HW_ZQINIT_510
1022 cycles
0x1FF : ZQ_LP2_HW_ZQINIT_511
1024 cycles
End of enumeration elements list.
ZQ_LP2_HW_ZQCL : This register defines the period in cycles that it takes the memory device to perform a long ZQ calibration
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0x37 : ZQ_LP2_HW_ZQCL_55
112 cycles
0x38 : ZQ_LP2_HW_ZQCL_56
114 cycles
0x5F : ZQ_LP2_HW_ZQCL_95
192 cycles (Default, JEDEC value, tZQCL, for LPDDR2, 360ns @ clock frequency 533MHz)
0xFE : ZQ_LP2_HW_ZQCL_254
510 cycles
0xFF : ZQ_LP2_HW_ZQCL_255
512 cycles
End of enumeration elements list.
ZQ_LP2_HW_ZQCS : This register defines the period in cycles that it takes the memory device to perform a short ZQ calibration
bits : 24 - 30 (7 bit)
access : read-write
Enumeration:
0x1B : ZQ_LP2_HW_ZQCS_27
112 cycles (default)
0x1C : ZQ_LP2_HW_ZQCS_28
116 cycles
0x7E : ZQ_LP2_HW_ZQCS_126
508 cycles
0x7F : ZQ_LP2_HW_ZQCS_127
512 cycles
End of enumeration elements list.
MMDC PHY Read Delay HW Calibration Control Register
address_offset : 0x860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HW_RD_DL_ERR0 : Automatic (HW) read calibration error of Byte0
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : HW_RD_DL_ERR0_0
No error was found in read delay-line 0 during the automatic (HW) read calibration process of read delay-line 0.
0x1 : HW_RD_DL_ERR0_1
An error was found in read delay-line 0 during the automatic (HW) read calibration process of read delay-line 0.
End of enumeration elements list.
HW_RD_DL_ERR1 : Automatic (HW) read calibration error of Byte1
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : HW_RD_DL_ERR1_0
No error was found in read delay-line 1 during the automatic (HW) read calibration process of read delay-line 1.
0x1 : HW_RD_DL_ERR1_1
An error was found in read delay-line 1 during the automatic (HW) read calibration process of read delay-line 1.
End of enumeration elements list.
HW_RD_DL_EN : Enable automatic (HW) read calibration
bits : 4 - 4 (1 bit)
access : read-write
HW_RD_DL_CMP_CYC : Automatic (HW) read sample cycle
bits : 5 - 5 (1 bit)
access : read-write
MMDC PHY Write Delay HW Calibration Control Register
address_offset : 0x864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HW_WR_DL_ERR0 : Automatic (HW) write calibration error of Byte0
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : HW_WR_DL_ERR0_0
No error was found during the automatic (HW) write calibration process of write delay-line 0.
0x1 : HW_WR_DL_ERR0_1
An error was found during the automatic (HW) write calibration process of write delay-line 0.
End of enumeration elements list.
HW_WR_DL_ERR1 : Automatic (HW) write calibration error of Byte1
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : HW_WR_DL_ERR1_0
No error was found during the automatic (HW) write calibration process of write delay-line 1.
0x1 : HW_WR_DL_ERR1_1
An error was found during the automatic (HW) write calibration process of write delay-line 1.
End of enumeration elements list.
HW_WR_DL_EN : Enable automatic (HW) write calibration
bits : 4 - 4 (1 bit)
access : read-write
HW_WR_DL_CMP_CYC : Write sample cycle
bits : 5 - 5 (1 bit)
access : read-write
MMDC PHY Read Delay HW Calibration Status Register 0
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HW_RD_DL_LOW0 : Automatic (HW) read calibration result of the lower boundary of Byte0
bits : 0 - 6 (7 bit)
access : read-only
HW_RD_DL_UP0 : Automatic (HW) read calibration result of the upper boundary of Byte0
bits : 8 - 14 (7 bit)
access : read-only
HW_RD_DL_LOW1 : Automatic (HW) read calibration result of the lower boundary of Byte1
bits : 16 - 22 (7 bit)
access : read-only
HW_RD_DL_UP1 : Automatic (HW) read calibration result of the upper boundary of Byte1
bits : 24 - 30 (7 bit)
access : read-only
MMDC PHY Write Delay HW Calibration Status Register 0
address_offset : 0x870 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HW_WR_DL_LOW0 : Automatic (HW) write calibration result of the lower boundary of Byte0
bits : 0 - 6 (7 bit)
access : read-only
HW_WR_DL_UP0 : Automatic (HW) write calibration result of the upper boundary of Byte0
bits : 8 - 14 (7 bit)
access : read-only
HW_WR_DL_LOW1 : Automatic (HW) write calibration result of the lower boundary of Byte1
bits : 16 - 22 (7 bit)
access : read-only
HW_WR_DL_UP1 : Automatic (HW) write automatic (HW) write calibration result of the upper boundary of Byte1
bits : 24 - 30 (7 bit)
access : read-only
MMDC PHY Write Leveling HW Error Register
address_offset : 0x878 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HW_WL0_DQ : HW write-leveling calibration result of Byte0
bits : 0 - 7 (8 bit)
access : read-only
HW_WL1_DQ : HW write-leveling calibration result of Byte1
bits : 8 - 15 (8 bit)
access : read-only
MMDC PHY Read DQS Gating HW Status Register 0
address_offset : 0x87C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HW_DG_LOW0 : HW DQS gating calibration result of the lower boundary of Byte0
bits : 0 - 10 (11 bit)
access : read-only
HW_DG_UP0 : HW DQS gating calibration result of the upper boundary of Byte0
bits : 16 - 26 (11 bit)
access : read-only
MMDC PHY Read DQS Gating HW Status Register 1
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HW_DG_LOW1 : HW DQS gating calibration result of the lower boundary of Byte1
bits : 0 - 10 (11 bit)
access : read-only
HW_DG_UP1 : HW DQS gating calibration result of the upper boundary of Byte1
bits : 16 - 26 (11 bit)
access : read-only
MMDC PHY Pre-defined Compare Register 1
address_offset : 0x88C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDV1 : MMDC Pre defined compare value2
bits : 0 - 15 (16 bit)
access : read-write
PDV2 : MMDC Pre defined compare value2
bits : 16 - 31 (16 bit)
access : read-write
MMDC PHY Pre-defined Compare and CA delay-line Configuration Register
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPR_CMP : MPR(DDR3)/ DQ calibration (LPDDR2/LPDDR3) compare enable
bits : 0 - 0 (1 bit)
access : read-write
MPR_FULL_CMP : MPR(DDR3)/ DQ calibration (LPDDR2/LPDDR3) full compare enable
bits : 1 - 1 (1 bit)
access : read-write
READ_LEVEL_PATTERN : MPR(DDR3)/ DQ calibration (LPDDR2/LPDDR3) read compare pattern
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : READ_LEVEL_PATTERN_0
Compare with read pattern 1010
0x1 : READ_LEVEL_PATTERN_1
Compare with read pattern 0011 (Used only in LPDDR2/LPDDR3 mode)
End of enumeration elements list.
ZQ_OFFSET_EN : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : ZQ_OFFSET_EN_0
Hardware ZQ offset disabled
0x1 : ZQ_OFFSET_EN_1
Hardware ZQ offset enabled
End of enumeration elements list.
ZQ_PD_OFFSET : Programmable offset from -7 to 7 added to the MMDC_MPZQHWCTRL[ZQ_HW_PD_RES] field when ZQ_OFFSET_EN is enabled
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : ZQ_PD_OFFSET_0
+0
0x1 : ZQ_PD_OFFSET_1
+1
0x2 : ZQ_PD_OFFSET_2
+2
0x3 : ZQ_PD_OFFSET_3
+3
0x4 : ZQ_PD_OFFSET_4
+4
0x5 : ZQ_PD_OFFSET_5
+5
0x6 : ZQ_PD_OFFSET_6
+6
0x7 : ZQ_PD_OFFSET_7
+7
0x8 : ZQ_PD_OFFSET_8
-0
0x9 : ZQ_PD_OFFSET_9
-1
0xA : ZQ_PD_OFFSET_10
-2
0xB : ZQ_PD_OFFSET_11
-3
0xC : ZQ_PD_OFFSET_12
-4
0xD : ZQ_PD_OFFSET_13
-5
0xE : ZQ_PD_OFFSET_14
-6
0xF : ZQ_PD_OFFSET_15
-7
End of enumeration elements list.
ZQ_PU_OFFSET : Programmable offset from -7 to 7 added to the MMDC_MPZQHWCTRL[ZQ_HW_PU_RES] field when ZQ_OFFSET_EN is enabled
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : ZQ_PU_OFFSET_0
+0
0x1 : ZQ_PU_OFFSET_1
+1
0x2 : ZQ_PU_OFFSET_2
+2
0x3 : ZQ_PU_OFFSET_3
+3
0x4 : ZQ_PU_OFFSET_4
+4
0x5 : ZQ_PU_OFFSET_5
+5
0x6 : ZQ_PU_OFFSET_6
+6
0x7 : ZQ_PU_OFFSET_7
+7
0x8 : ZQ_PU_OFFSET_8
-0
0x9 : ZQ_PU_OFFSET_9
-1
0xA : ZQ_PU_OFFSET_10
-2
0xB : ZQ_PU_OFFSET_11
-3
0xC : ZQ_PU_OFFSET_12
-4
0xD : ZQ_PU_OFFSET_13
-5
0xE : ZQ_PU_OFFSET_14
-6
0xF : ZQ_PU_OFFSET_15
-7
End of enumeration elements list.
CA_DL_ABS_OFFSET : Absolute CA (Command/Address of LPDDRR2) offset
bits : 16 - 22 (7 bit)
access : read-write
PHY_CA_DL_UNIT : This field reflects the number of delay units that are actually used by CA(Command/Address of LPDDR2) delay-line
bits : 24 - 30 (7 bit)
access : read-only
MMDC PHY SW Dummy Access Register
address_offset : 0x894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_DUMMY_WR : SW dummy write
bits : 0 - 0 (1 bit)
access : read-write
SW_DUMMY_RD : SW dummy read
bits : 1 - 1 (1 bit)
access : read-write
SW_DUM_CMP0 : SW dummy read byte0 compare results
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : SW_DUM_CMP0_0
Dummy read fail
0x1 : SW_DUM_CMP0_1
Dummy read pass
End of enumeration elements list.
SW_DUM_CMP1 : SW dummy read byte1 compare results
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : SW_DUM_CMP1_0
Dummy read fail
0x1 : SW_DUM_CMP1_1
Dummy read pass
End of enumeration elements list.
MMDC PHY SW Dummy Read Data Register 0
address_offset : 0x898 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUM_RD0 : Dummy read data0
bits : 0 - 31 (32 bit)
access : read-only
MMDC PHY SW Dummy Read Data Register 1
address_offset : 0x89C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUM_RD1 : Dummy read data1
bits : 0 - 31 (32 bit)
access : read-only
MMDC PHY SW Dummy Read Data Register 2
address_offset : 0x8A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUM_RD2 : Dummy read data2
bits : 0 - 31 (32 bit)
access : read-only
MMDC PHY SW Dummy Read Data Register 3
address_offset : 0x8A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUM_RD3 : Dummy read data3
bits : 0 - 31 (32 bit)
access : read-only
MMDC PHY SW Dummy Read Data Register 4
address_offset : 0x8A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUM_RD4 : Dummy read data4
bits : 0 - 31 (32 bit)
access : read-only
MMDC PHY SW Dummy Read Data Register 5
address_offset : 0x8AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUM_RD5 : Dummy read data5
bits : 0 - 31 (32 bit)
access : read-only
MMDC PHY SW Dummy Read Data Register 6
address_offset : 0x8B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUM_RD6 : Dummy read data6
bits : 0 - 31 (32 bit)
access : read-only
MMDC PHY SW Dummy Read Data Register 7
address_offset : 0x8B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUM_RD7 : Dummy read data7
bits : 0 - 31 (32 bit)
access : read-only
MMDC PHY Measure Unit Register
address_offset : 0x8B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MU_BYP_VAL : Number of delay units for measurement bypass
bits : 0 - 9 (10 bit)
access : read-write
MU_BYP_EN : Measure unit bypass enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : MU_BYP_EN_0
The delay-lines use delay units as indicated at MU_UNIT_DEL_NUM.
0x1 : MU_BYP_EN_1
The delay-lines use delay units as indicated at MU_BYPASS_VAL.
End of enumeration elements list.
FRC_MSR : Force measurement on delay-lines
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : FRC_MSR_0
No measurement is performed
0x1 : FRC_MSR_1
Perform measurement process
End of enumeration elements list.
MU_UNIT_DEL_NUM : Number of delay units measured per cycle
bits : 16 - 25 (10 bit)
access : read-only
MMDC Write CA delay-line controller
address_offset : 0x8BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR_CA0_DEL : CA(Command/Address LPDDR2 bus) bit 0 delay fine tuning
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : WR_CA0_DEL_0
No change in CA0 delay
0x1 : WR_CA0_DEL_1
Add CA0 delay of 1 delay unit
0x2 : WR_CA0_DEL_2
Add CA0 delay of 2 delay units.
0x3 : WR_CA0_DEL_3
Add CA0 delay of 3 delay units.
End of enumeration elements list.
WR_CA1_DEL : CA (Command/Address LPDDR2 bus) bit 1 delay fine tuning
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : WR_CA1_DEL_0
No change in CA1 delay
0x1 : WR_CA1_DEL_1
Add CA1 delay of 1 delay unit
0x2 : WR_CA1_DEL_2
Add CA1 delay of 2 delay units.
0x3 : WR_CA1_DEL_3
Add CA1 delay of 3 delay units.
End of enumeration elements list.
WR_CA2_DEL : CA (Command/Address LPDDR2 bus) bit 2 delay fine tuning
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : WR_CA2_DEL_0
No change in CA2 delay
0x1 : WR_CA2_DEL_1
Add CA2 delay of 1 delay unit
0x2 : WR_CA2_DEL_2
Add CA2 delay of 2 delay units.
0x3 : WR_CA2_DEL_3
Add CA2 delay of 3 delay units.
End of enumeration elements list.
WR_CA3_DEL : CA (Command/Address LPDDR2 bus) bit 3 delay fine tuning
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : WR_CA3_DEL_0
No change in CA3 delay
0x1 : WR_CA3_DEL_1
Add CA3 delay of 1 delay unit
0x2 : WR_CA3_DEL_2
Add CA3 delay of 2 delay units.
0x3 : WR_CA3_DEL_3
Add CA3 delay of 3 delay units.
End of enumeration elements list.
WR_CA4_DEL : CA (Command/Address LPDDR2 bus) bit 4 delay fine tuning
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : WR_CA4_DEL_0
No change in CA4 delay
0x1 : WR_CA4_DEL_1
Add CA4 delay of 1 delay unit
0x2 : WR_CA4_DEL_2
Add CA4 delay of 2 delay units.
0x3 : WR_CA4_DEL_3
Add CA4 delay of 3 delay units.
End of enumeration elements list.
WR_CA5_DEL : CA (Command/Address LPDDR2 bus) bit 5 delay fine tuning
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : WR_CA5_DEL_0
No change in CA5 delay
0x1 : WR_CA5_DEL_1
Add CA5 delay of 1 delay unit
0x2 : WR_CA5_DEL_2
Add CA5 delay of 2 delay units.
0x3 : WR_CA5_DEL_3
Add CA5 delay of 3 delay units.
End of enumeration elements list.
WR_CA6_DEL : CA (Command/Address LPDDR2 bus) bit 6 delay fine tuning
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : WR_CA6_DEL_0
No change in CA6 delay
0x1 : WR_CA6_DEL_1
Add CA6 delay of 1 delay unit
0x2 : WR_CA6_DEL_2
Add CA6 delay of 2 delay units.
0x3 : WR_CA6_DEL_3
Add CA6 delay of 3 delay units.
End of enumeration elements list.
WR_CA7_DEL : CA (Command/Address LPDDR2 bus) bit 7 delay fine tuning
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : WR_CA7_DEL_0
No change in CA7 delay
0x1 : WR_CA7_DEL_1
Add CA7 delay of 1 delay unit
0x2 : WR_CA7_DEL_2
Add CA7 delay of 2 delay units.
0x3 : WR_CA7_DEL_3
Add CA7 delay of 3 delay units.
End of enumeration elements list.
WR_CA8_DEL : CA (Command/Address LPDDR2 bus) bit 8 delay fine tuning
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : WR_CA8_DEL_0
No change in CA8 delay
0x1 : WR_CA8_DEL_1
Add CA8 delay of 1 delay unit
0x2 : WR_CA8_DEL_2
Add CA8 delay of 2 delay units.
0x3 : WR_CA8_DEL_3
Add CA8 delay of 3 delay units.
End of enumeration elements list.
WR_CA9_DEL : CA (Command/Address LPDDR2 bus) bit 9 delay fine tuning
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : WR_CA9_DEL_0
No change in CA9 delay
0x1 : WR_CA9_DEL_1
Add CA9 delay of 1 delay unit
0x2 : WR_CA9_DEL_2
Add CA9 delay of 2 delay units.
0x3 : WR_CA9_DEL_3
Add CA9 delay of 3 delay units.
End of enumeration elements list.
MMDC Duty Cycle Control Register
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR_DQS0_FT_DCC : Write DQS duty cycle fine tuning control of Byte0
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x1 : WR_DQS0_FT_DCC_1
51.5% low 48.5% high
0x2 : WR_DQS0_FT_DCC_2
50% duty cycle (default)
0x4 : WR_DQS0_FT_DCC_4
48.5% low 51.5% high
End of enumeration elements list.
WR_DQS1_FT_DCC : Write DQS duty cycle fine tuning control of Byte1
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0x1 : WR_DQS1_FT_DCC_1
51.5% low 48.5% high
0x2 : WR_DQS1_FT_DCC_2
50% duty cycle (default)
0x4 : WR_DQS1_FT_DCC_4
48.5% low 51.5% high
End of enumeration elements list.
CK_FT0_DCC : Primary duty cycle fine tuning control of DDR clock
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x1 : CK_FT0_DCC_1
48.5% low 51.5% high
0x2 : CK_FT0_DCC_2
50% duty cycle (default)
0x4 : CK_FT0_DCC_4
51.5% low 48.5% high
End of enumeration elements list.
CK_FT1_DCC : Secondary duty cycle fine tuning control of DDR clock
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x1 : CK_FT1_DCC_1
48.5% low 51.5% high
0x2 : CK_FT1_DCC_2
50% duty cycle (default)
0x4 : CK_FT1_DCC_4
51.5% low 48.5% high
End of enumeration elements list.
RD_DQS0_FT_DCC : Read DQS duty cycle fine tuning control of Byte0
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0x1 : RD_DQS0_FT_DCC_1
51.5% low 48.5% high
0x2 : RD_DQS0_FT_DCC_2
50% duty cycle (default)
0x4 : RD_DQS0_FT_DCC_4
48.5% low 51.5% high
End of enumeration elements list.
RD_DQS1_FT_DCC : Read DQS duty cycle fine tuning control of Byte1
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
0x1 : RD_DQS1_FT_DCC_1
51.5% low 48.5% high
0x2 : RD_DQS1_FT_DCC_2
50% duty cycle (default)
0x4 : RD_DQS1_FT_DCC_4
48.5% low 51.5% high
End of enumeration elements list.
MMDC Core Timing Configuration Register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tCL : CAS Read Latency
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : tCL_0
3 cycles
0x1 : tCL_1
4 cycles
0x2 : tCL_2
5 cycles
0x3 : tCL_3
6 cycles
0x4 : tCL_4
7 cycles
0x5 : tCL_5
8 cycles
0x6 : tCL_6
9 cycles
0x7 : tCL_7
10 cycles
0x8 : tCL_8
11 cycles
0x9 : tCL_9
- 0xF Reserved
End of enumeration elements list.
tFAW : Four Active Window (all banks)
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : tFAW_0
1 clock
0x1 : tFAW_1
2 clocks
0x2 : tFAW_2
3 clocks
0x1E : tFAW_30
31 clocks
0x1F : tFAW_31
32 clocks
End of enumeration elements list.
tXPDLL : Exit precharge power down with DLL frozen to commands requiring DLL
bits : 9 - 12 (4 bit)
access : read-write
Enumeration:
0 : tXPDLL_0
1 clock
0x1 : tXPDLL_1
2 clocks
0x2 : tXPDLL_2
3 clocks
0xE : tXPDLL_14
15 clocks
0xF : tXPDLL_15
16 clocks
End of enumeration elements list.
tXP : Exit power down with DLL-on to any valid command
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : tXP_0
1 cycle
0x1 : tXP_1
2 cycles
0x6 : tXP_6
7 cycles
0x7 : tXP_7
8 cycles
End of enumeration elements list.
tXS : Exit self refresh to non READ command
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : tXS_0
- 0x15 reserved
0x16 : tXS_22
23 clocks
0x17 : tXS_23
24 clocks
0xFE : tXS_254
255 clocks
0xFF : tXS_255
256 clocks
End of enumeration elements list.
tRFC : Refresh command to Active or Refresh command time
bits : 24 - 31 (8 bit)
access : read-write
Enumeration:
0 : tRFC_0
1 clock
0x1 : tRFC_1
2 clocks
0x2 : tRFC_2
3 clocks
0xFE : tRFC_254
255 clocks
0xFF : tRFC_255
256 clocks
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.