\n
address_offset : 0x0 Bytes (0x0)
size : 0x434 byte (0x0)
mem_usage : registers
protection : not protected
DCP control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL_INTERRUPT_ENABLE : Per-channel interrupt enable bit
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x1 : CH0
no description available
0x2 : CH1
no description available
0x4 : CH2
no description available
0x8 : CH3
no description available
End of enumeration elements list.
ENABLE_CONTEXT_SWITCHING : Enable automatic context switching for the channels
bits : 21 - 21 (1 bit)
access : read-write
ENABLE_CONTEXT_CACHING : The software must set this bit to enable the caching of contexts between the operations
bits : 22 - 22 (1 bit)
access : read-write
GATHER_RESIDUAL_WRITES : The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations
bits : 23 - 23 (1 bit)
access : read-write
PRESENT_SHA : Indicates whether the SHA1/SHA2 functions are present.
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : Absent
no description available
0x1 : Present
no description available
End of enumeration elements list.
PRESENT_CRYPTO : Indicates whether the crypto (cipher/hash) functions are present.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : Absent
no description available
0x1 : Present
no description available
End of enumeration elements list.
CLKGATE : This bit must be set to zero for a normal operation
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : Set this bit to zero to enable a normal DCP operation
bits : 31 - 31 (1 bit)
access : read-write
DCP status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ : Indicates which channels have pending interrupt requests
bits : 0 - 3 (4 bit)
access : read-write
READY_CHANNELS : Indicates which channels are ready to proceed with a transfer (the active channel is also included)
bits : 16 - 23 (8 bit)
access : read-only
Enumeration:
0x1 : CH0
no description available
0x2 : CH1
no description available
0x4 : CH2
no description available
0x8 : CH3
no description available
End of enumeration elements list.
CUR_CHANNEL : Current (active) channel (encoded)
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : None
no description available
0x1 : CH0
no description available
0x2 : CH1
no description available
0x3 : CH2
no description available
0x4 : CH3
no description available
End of enumeration elements list.
OTP_KEY_READY : When set, it indicates that the OTP key is shifted from the fuse block and is ready for use.
bits : 28 - 28 (1 bit)
access : read-only
DCP channel 0 command pointer address register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Pointer to the descriptor structure to be processed for channel 0.
bits : 0 - 31 (32 bit)
access : read-write
DCP channel 0 semaphore register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT : The value written to this field is added to the semaphore count in an atomic way such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
VALUE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
DCP channel 0 status register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH_MISMATCH : This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit
bits : 1 - 1 (1 bit)
access : read-write
ERROR_SETUP : This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)
bits : 2 - 2 (1 bit)
access : read-write
ERROR_PACKET : This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload
bits : 3 - 3 (1 bit)
access : read-write
ERROR_SRC : This bit indicates that a bus error occurred when reading from the source buffer
bits : 4 - 4 (1 bit)
access : read-write
ERROR_DST : This bit indicates that a bus error occurred when storing to the destination buffer
bits : 5 - 5 (1 bit)
access : read-write
ERROR_PAGEFAULT : This bit indicates that a page fault occurred while converting a virtual address to a physical address
bits : 6 - 6 (1 bit)
access : read-write
ERROR_CODE : Indicates the additional error codes for some of the error conditions
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0x1 : NEXT_CHAIN_IS_0
Error signalled because the next pointer is 0x00000000
0x2 : NO_CHAIN
Error signalled because the semaphore is non-zero and neither chain bit is set
0x3 : CONTEXT_ERROR
Error signalled because an error is reported reading/writing the context buffer
0x4 : PAYLOAD_ERROR
Error signalled because an error is reported reading/writing the payload
0x5 : INVALID_MODE
Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
End of enumeration elements list.
TAG : Indicates the tag from the last completed packet in the command structure
bits : 24 - 31 (8 bit)
access : read-only
DCP channel 0 options register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECOVERY_TIMER : This field indicates the recovery time for the channel
bits : 0 - 15 (16 bit)
access : read-write
DCP channel 1 command pointer address register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Pointer to the descriptor structure to be processed for channel 1.
bits : 0 - 31 (32 bit)
access : read-write
DCP channel 1 semaphore register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT : The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and the DCP hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
VALUE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
DCP channel 1 status register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH_MISMATCH : This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit
bits : 1 - 1 (1 bit)
access : read-write
ERROR_SETUP : This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)
bits : 2 - 2 (1 bit)
access : read-write
ERROR_PACKET : This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod
bits : 3 - 3 (1 bit)
access : read-write
ERROR_SRC : This bit indicates that a bus error occurred when reading from the source buffer
bits : 4 - 4 (1 bit)
access : read-write
ERROR_DST : This bit indicates that a bus error occurred when storing to the destination buffer
bits : 5 - 5 (1 bit)
access : read-write
ERROR_PAGEFAULT : This bit indicates that a page fault occurred while converting a virtual address to a physical address
bits : 6 - 6 (1 bit)
access : read-write
ERROR_CODE : Indicates the additional error codes for some of the error conditions.
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0x1 : NEXT_CHAIN_IS_0
Error is signalled because the next pointer is 0x00000000.
0x2 : NO_CHAIN
Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
0x3 : CONTEXT_ERROR
Error is signalled because an error was reported when reading/writing the context buffer.
0x4 : PAYLOAD_ERROR
Error is signalled because an error was reported when reading/writing the payload.
0x5 : INVALID_MODE
Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
End of enumeration elements list.
TAG : Indicates the tag from the last completed packet in the command structure.
bits : 24 - 31 (8 bit)
access : read-only
DCP channel 1 options register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECOVERY_TIMER : This field indicates the recovery time for the channel
bits : 0 - 15 (16 bit)
access : read-write
DCP channel 2 command pointer address register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Pointer to the descriptor structure to be processed for channel 2.
bits : 0 - 31 (32 bit)
access : read-write
DCP channel 2 semaphore register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT : The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
VALUE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
DCP channel 2 status register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH_MISMATCH : This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit
bits : 1 - 1 (1 bit)
access : read-write
ERROR_SETUP : This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)
bits : 2 - 2 (1 bit)
access : read-write
ERROR_PACKET : This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod
bits : 3 - 3 (1 bit)
access : read-write
ERROR_SRC : This bit indicates that a bus error occurred when reading from the source buffer
bits : 4 - 4 (1 bit)
access : read-write
ERROR_DST : This bit indicates that a bus error occurred when storing to the destination buffer
bits : 5 - 5 (1 bit)
access : read-write
ERROR_PAGEFAULT : This bit indicates that a page fault occurred while converting a virtual address to a physical address
bits : 6 - 6 (1 bit)
access : read-write
ERROR_CODE : Indicates additional error codes for some of the error conditions.
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0x1 : NEXT_CHAIN_IS_0
Error is signalled because the next pointer is 0x00000000.
0x2 : NO_CHAIN
Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
0x3 : CONTEXT_ERROR
Error is signalled because an error was reported while reading/writing the context buffer.
0x4 : PAYLOAD_ERROR
Error is signalled because an error was reported while reading/writing the payload.
0x5 : INVALID_MODE
Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
End of enumeration elements list.
TAG : Indicates the tag from the last completed packet in the command structure.
bits : 24 - 31 (8 bit)
access : read-only
DCP channel 2 options register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECOVERY_TIMER : This field indicates the recovery time for the channel
bits : 0 - 15 (16 bit)
access : read-write
DCP channel 3 command pointer address register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Pointer to the descriptor structure to be processed for channel 3.
bits : 0 - 31 (32 bit)
access : read-write
DCP channel 3 semaphore register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT : The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
VALUE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
DCP channel 3 status register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH_MISMATCH : This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit
bits : 1 - 1 (1 bit)
access : read-write
ERROR_SETUP : This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)
bits : 2 - 2 (1 bit)
access : read-write
ERROR_PACKET : This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod
bits : 3 - 3 (1 bit)
access : read-write
ERROR_SRC : This bit indicates that a bus error occurred when reading from the source buffer
bits : 4 - 4 (1 bit)
access : read-write
ERROR_DST : This bit indicates that a bus error occurred when storing to the destination buffer
bits : 5 - 5 (1 bit)
access : read-write
ERROR_PAGEFAULT : This bit indicates that a page fault occurred while converting a virtual address to a physical address
bits : 6 - 6 (1 bit)
access : read-write
ERROR_CODE : Indicates additional error codes for some of the error conditions.
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0x1 : NEXT_CHAIN_IS_0
Error is signalled because the next pointer is 0x00000000.
0x2 : NO_CHAIN
Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
0x3 : CONTEXT_ERROR
Error is signalled because an error was reported while reading/writing the context buffer.
0x4 : PAYLOAD_ERROR
Error is signalled because an error was reported while reading/writing the payload.
0x5 : INVALID_MODE
Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
End of enumeration elements list.
TAG : Indicates the tag from the last completed packet in the command structure.
bits : 24 - 31 (8 bit)
access : read-only
DCP channel 3 options register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECOVERY_TIMER : This field indicates the recovery time for the channel
bits : 0 - 15 (16 bit)
access : read-write
DCP channel control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_CHANNEL : Setting a bit in this field enables the DMA channel associated with it
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x1 : CH0
no description available
0x2 : CH1
no description available
0x4 : CH2
no description available
0x8 : CH3
no description available
End of enumeration elements list.
HIGH_PRIORITY_CHANNEL : Setting a bit in this field causes the corresponding channel to have high-priority arbitration
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
0x1 : CH0
no description available
0x2 : CH1
no description available
0x4 : CH2
no description available
0x8 : CH3
no description available
End of enumeration elements list.
CH0_IRQ_MERGED : Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt
bits : 16 - 16 (1 bit)
access : read-write
DCP capability 0 register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUM_KEYS : Encoded value indicating the number of key-storage locations implemented in the design
bits : 0 - 7 (8 bit)
access : read-only
NUM_CHANNELS : Encoded value indicating the number of channels implemented in the design
bits : 8 - 11 (4 bit)
access : read-only
DISABLE_UNIQUE_KEY : Write to a 1 to disable the per-device unique key
bits : 29 - 29 (1 bit)
access : read-write
DISABLE_DECRYPT : Write to 1 to disable the decryption
bits : 31 - 31 (1 bit)
access : read-write
DCP capability 1 register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CIPHER_ALGORITHMS : One-hot field indicating which cipher algorithms are available
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0x1 : AES128
no description available
End of enumeration elements list.
HASH_ALGORITHMS : One-hot field indicating which hashing features are implemented in the hardware
bits : 16 - 31 (16 bit)
access : read-only
Enumeration:
0x1 : SHA1
no description available
0x2 : CRC32
no description available
0x4 : SHA256
no description available
End of enumeration elements list.
DCP debug select register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDEX : Selects a value to read via the debug data register.
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x1 : CONTROL
no description available
0x10 : OTPKEY0
no description available
0x11 : OTPKEY1
no description available
0x12 : OTPKEY2
no description available
0x13 : OTPKEY3
no description available
End of enumeration elements list.
DCP debug data register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Debug data
bits : 0 - 31 (32 bit)
access : read-only
DCP page table register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Page table enable control
bits : 0 - 0 (1 bit)
access : read-write
FLUSH : Page table flush control. To flush the TLB, write this bit to 1 and then back to 0.
bits : 1 - 1 (1 bit)
access : read-write
BASE : Page table base address
bits : 2 - 31 (30 bit)
access : read-write
DCP version register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STEP : Fixed read-only value reflecting the stepping of the version of the design implementation.
bits : 0 - 15 (16 bit)
access : read-only
MINOR : Fixed read-only value reflecting the MINOR version of the design implementation.
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Fixed read-only value reflecting the MAJOR version of the design implementation.
bits : 24 - 31 (8 bit)
access : read-only
DCP context buffer pointer
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Context pointer address
bits : 0 - 31 (32 bit)
access : read-write
DCP key index
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBWORD : Key subword pointer
bits : 0 - 1 (2 bit)
access : read-write
INDEX : Key index pointer. The valid indices are 0-[number_keys].
bits : 4 - 5 (2 bit)
access : read-write
DCP key data
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Word 0 data for the key. This is the least-significant word.
bits : 0 - 31 (32 bit)
access : read-write
DCP work packet 0 status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : Next pointer register
bits : 0 - 31 (32 bit)
access : read-only
DCP work packet 1 status register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTERRUPT : Reflects whether the channel must issue an interrupt upon the completion of the packet.
bits : 0 - 0 (1 bit)
access : read-only
DECR_SEMAPHORE : Reflects whether the channel's semaphore must be decremented at the end of the current operation
bits : 1 - 1 (1 bit)
access : read-only
CHAIN : Reflects whether the next command pointer register must be loaded into the channel's current descriptor pointer
bits : 2 - 2 (1 bit)
access : read-only
CHAIN_CONTIGUOUS : Reflects whether the next packet's address is located following this packet's payload.
bits : 3 - 3 (1 bit)
access : read-only
ENABLE_MEMCOPY : Reflects whether the selected hashing function should be enabled for this operation.
bits : 4 - 4 (1 bit)
access : read-only
ENABLE_CIPHER : Reflects whether the selected cipher function must be enabled for this operation.
bits : 5 - 5 (1 bit)
access : read-only
ENABLE_HASH : Reflects whether the selected hashing function must be enabled for this operation.
bits : 6 - 6 (1 bit)
access : read-only
ENABLE_BLIT : Reflects whether the DCP must perform a blit operation
bits : 7 - 7 (1 bit)
access : read-only
CIPHER_ENCRYPT : When the cipher block is enabled, this bit indicates whether the operation is encryption or decryption
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : DECRYPT
no description available
0x1 : ENCRYPT
no description available
End of enumeration elements list.
CIPHER_INIT : Reflects whether the cipher block must load the initialization vector from the payload for this operation
bits : 9 - 9 (1 bit)
access : read-only
OTP_KEY : Reflects whether a hardware-based key must be used
bits : 10 - 10 (1 bit)
access : read-only
PAYLOAD_KEY : When set, it indicates the payload contains the key
bits : 11 - 11 (1 bit)
access : read-only
HASH_INIT : Reflects whether the current hashing block is the initial block in the hashing operation, so the hash registers must be initialized before the operation
bits : 12 - 12 (1 bit)
access : read-only
HASH_TERM : Reflects whether the current hashing block is the final block in the hashing operation, so the hash padding must be applied by the hardware
bits : 13 - 13 (1 bit)
access : read-only
CHECK_HASH : Reflects whether the calculated hash value must be compared to the hash provided in the payload.
bits : 14 - 14 (1 bit)
access : read-only
HASH_OUTPUT : When the hashing is enabled, this bit controls whether the input or output data is hashed.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : INPUT
no description available
0x1 : OUTPUT
no description available
End of enumeration elements list.
CONSTANT_FILL : When this bit is set (MEMCOPY and BLIT modes only), the DCP simply fills the destination buffer with the value found in the source address field
bits : 16 - 16 (1 bit)
access : read-only
TEST_SEMA_IRQ : This bit is used to test the channel semaphore transition to 0. FOR TEST USE ONLY!
bits : 17 - 17 (1 bit)
access : read-only
KEY_BYTESWAP : Reflects whether the DCP engine swaps the key bytes (big-endian key).
bits : 18 - 18 (1 bit)
access : read-only
KEY_WORDSWAP : Reflects whether the DCP engine swaps the key words (big-endian key).
bits : 19 - 19 (1 bit)
access : read-only
INPUT_BYTESWAP : Reflects whether the DCP engine byteswaps the input data (big-endian data).
bits : 20 - 20 (1 bit)
access : read-only
INPUT_WORDSWAP : Reflects whether the DCP engine wordswaps the input data (big-endian data).
bits : 21 - 21 (1 bit)
access : read-only
OUTPUT_BYTESWAP : Reflects whether the DCP engine byteswaps the output data (big-endian data).
bits : 22 - 22 (1 bit)
access : read-only
OUTPUT_WORDSWAP : Reflects whether the DCP engine wordswaps the output data (big-endian data).
bits : 23 - 23 (1 bit)
access : read-only
TAG : Packet Tag
bits : 24 - 31 (8 bit)
access : read-only
DCP work packet 2 status register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CIPHER_SELECT : Cipher selection field
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
0 : AES128
no description available
End of enumeration elements list.
CIPHER_MODE : Cipher mode selection field. Reflects the mode of operation for the cipher operations.
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
0 : ECB
no description available
0x1 : CBC
no description available
End of enumeration elements list.
KEY_SELECT : Key selection field
bits : 8 - 15 (8 bit)
access : read-only
Enumeration:
0 : KEY0
no description available
0x1 : KEY1
no description available
0x2 : KEY2
no description available
0x3 : KEY3
no description available
0xFE : UNIQUE_KEY
no description available
0xFF : OTP_KEY
no description available
End of enumeration elements list.
HASH_SELECT : Hash Selection Field
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0 : SHA1
no description available
0x1 : CRC32
no description available
0x2 : SHA256
no description available
End of enumeration elements list.
CIPHER_CFG : Cipher configuration bits. Optional configuration bits are required for the ciphers.
bits : 24 - 31 (8 bit)
access : read-only
DCP work packet 3 status register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : Source buffer address pointer
bits : 0 - 31 (32 bit)
access : read-only
DCP work packet 4 status register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : Destination buffer address pointer
bits : 0 - 31 (32 bit)
access : read-only
DCP work packet 5 status register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Byte count register. This value is the working value and updates as the operation proceeds.
bits : 0 - 31 (32 bit)
access : read-only
DCP work packet 6 status register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : This regiser reflects the payload pointer for the current control packet.
bits : 0 - 31 (32 bit)
access : read-only
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