Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
ESAI Transmit Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ETDR : ESAI Transmit Data Register
bits : 0 - 31 (32 bit)
access : write-only
Transmit FIFO Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFE : Transmit FIFO Enable. This bit enables the use of the Transmit FIFO.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TFE_0
Transmit FIFO disabled.
0x1 : TFE_1
Transmit FIFO enabled.
End of enumeration elements list.
TFR : Transmit FIFO Reset. This bit resets the Transmit FIFO pointers.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TFR_0
Transmit FIFO not reset.
0x1 : TFR_1
Transmit FIFO reset.
End of enumeration elements list.
TE0 : Transmitter #0 FIFO Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : TE0_0
Transmitter #0 is not using the Transmit FIFO.
0x1 : TE0_1
Transmitter #0 is using the Transmit FIFO.
End of enumeration elements list.
TE1 : Transmitter #1 FIFO Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TE1_0
Transmitter #1 is not using the Transmit FIFO.
0x1 : TE1_1
Transmitter #1 is using the Transmit FIFO.
End of enumeration elements list.
TE2 : Transmitter #2 FIFO Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : TE2_0
Transmitter #2 is not using the Transmit FIFO.
0x1 : TE2_1
Transmitter #2 is using the Transmit FIFO.
End of enumeration elements list.
TE3 : Transmitter #3 FIFO Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : TE3_0
Transmitter #3 is not using the Transmit FIFO.
0x1 : TE3_1
Transmitter #3 is using the Transmit FIFO.
End of enumeration elements list.
TE4 : Transmitter #4 FIFO Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : TE4_0
Transmitter #4 is not using the Transmit FIFO.
0x1 : TE4_1
Transmitter #4 is using the Transmit FIFO.
End of enumeration elements list.
TE5 : Transmitter #5 FIFO Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : TE5_0
Transmitter #5 is not using the Transmit FIFO.
0x1 : TE5_1
Transmitter #5 is using the Transmit FIFO.
End of enumeration elements list.
TFWM : Transmit FIFO Watermark
bits : 8 - 15 (8 bit)
access : read-write
TWA : Transmit Word Alignment
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : TWA_0
MSB of data is bit 31. Data bits 7-0 are ignored when passed to transmit shift register.
0x1 : TWA_1
MSB of data is bit 27. Data bits 3-0 are ignored when passed to transmit shift register.
0x2 : TWA_2
MSB of data is bit 23.
0x3 : TWA_3
MSB of data is bit 19. Bottom 4 bits of transmit shift register are zeroed.
0x4 : TWA_4
MSB of data is bit 15. Bottom 8 bits of transmit shift register are zeroed.
0x5 : TWA_5
MSB of data is bit 11. Bottom 12 bits of transmit shift register are zeroed.
0x6 : TWA_6
MSB of data is bit 7. Bottom 16 bits of transmit shift register are zeroed.
0x7 : TWA_7
MSB of data is bit 3. Bottom 20 bits of transmit shift register are zeroed.
End of enumeration elements list.
TIEN : Transmitter Initialization Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : TIEN_0
Transmit Data Registers are not initialized from the FIFO once the Transmit FIFO is enabled. Software must manually initialize the Transmit Data Registers separately.
0x1 : TIEN_1
Transmit Data Registers are initialized from the FIFO once the Transmit FIFO is enabled.
End of enumeration elements list.
TAENB : Tx FIFO Align Enable
bits : 20 - 20 (1 bit)
access : read-write
TFIN : Tx FIFO Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write
Transmit Data Register n
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXn : Stores the data to be transmitted and is automatically transferred to the transmit shift registers
bits : 0 - 23 (24 bit)
access : write-only
Transmit FIFO Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TFCNT : Transmit FIFO Counter. These bits indicate the number of data words stored in the Transmit FIFO.
bits : 0 - 7 (8 bit)
access : read-only
NTFI : Next Transmitter FIFO In. Indicates which transmitter receives the next word written to the FIFO.
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
0 : NTFI_0
Transmitter #0 receives next word written to the Transmit FIFO.
0x1 : NTFI_1
Transmitter #1 receives next word written to the Transmit FIFO.
0x2 : NTFI_2
Transmitter #2 receives next word written to the Transmit FIFO.
0x3 : NTFI_3
Transmitter #3 receives next word written to the Transmit FIFO.
0x4 : NTFI_4
Transmitter #4 receives next word written to the Transmit FIFO.
0x5 : NTFI_5
Transmitter #5 receives next word written to the Transmit FIFO.
End of enumeration elements list.
NTFO : Next Transmitter FIFO Out
bits : 12 - 14 (3 bit)
access : read-only
Enumeration:
0 : NTFO_0
Transmitter #0 receives next word from the Transmit FIFO.
0x1 : NTFO_1
Transmitter #1 receives next word from the Transmit FIFO.
0x2 : NTFO_2
Transmitter #2 receives next word from the Transmit FIFO.
0x3 : NTFO_3
Transmitter #3 receives next word from the Transmit FIFO.
0x4 : NTFO_4
Transmitter #4 receives next word from the Transmit FIFO.
0x5 : NTFO_5
Transmitter #5 receives next word from the Transmit FIFO.
End of enumeration elements list.
Receive Data Register n
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXn : Accept data from the receive shift registers when they become full See ESAI Receive Shift Registers
bits : 0 - 23 (24 bit)
access : read-only
Receive FIFO Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFE : Receive FIFO Enable. This bit enables the use of the Receive FIFO.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RFE_0
Receive FIFO disabled.
0x1 : RFE_1
Receive FIFO enabled.
End of enumeration elements list.
RFR : Receive FIFO Reset. This bit resets the Receive FIFO pointers.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RFR_0
Receive FIFO not reset.
0x1 : RFR_1
Receive FIFO reset.
End of enumeration elements list.
RE0 : Receiver #0 FIFO Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : RE0_0
Receiver #0 is not using the Receive FIFO.
0x1 : RE0_1
Receiver #0 is using the Receive FIFO.
End of enumeration elements list.
RE1 : Receiver #1 FIFO Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RE1_0
Receiver #1 is not using the Receive FIFO.
0x1 : RE1_1
Receiver #1 is using the Receive FIFO.
End of enumeration elements list.
RE2 : Receiver #2 FIFO Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : RE2_0
Receiver #2 is not using the Receive FIFO.
0x1 : RE2_1
Receiver #2 is using the Receive FIFO.
End of enumeration elements list.
RE3 : Receiver #3 FIFO Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : RE3_0
Receiver #3 is not using the Receive FIFO.
0x1 : RE3_1
Receiver #3 is using the Receive FIFO.
End of enumeration elements list.
RFWM : Receive FIFO Watermark
bits : 8 - 15 (8 bit)
access : read-write
RWA : Receive Word Alignment
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : RWA_0
MSB of data is at bit 31. Data bits 7-0 are zeroed.
0x1 : RWA_1
MSB of data is at bit 27. Data bits 3-0 are zeroed.
0x2 : RWA_2
MSB of data is at bit 23.
0x3 : RWA_3
MSB of data is at bit 19. Data bits 3-0 from receive shift register are ignored.
0x4 : RWA_4
MSB of data is at bit 15. Data bits 7-0 from receive shift register are ignored.
0x5 : RWA_5
MSB of data is at bit 11. Data bits 11-0 from receive shift register are ignored.
0x6 : RWA_6
MSB of data is at bit 7. Data bits 15-0 from receive shift register are ignored.
0x7 : RWA_7
MSB of data is at bit 3. Data bits 19-0 from receive shift register are ignored.
End of enumeration elements list.
REXT : Receive Extension
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : REXT_0
Receive data is zero extended.
0x1 : REXT_1
Receive data is sign extended.
End of enumeration elements list.
RAENB : Rx FIFO Align Enable
bits : 20 - 20 (1 bit)
access : read-write
RFIN : Rx FIFO Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write
Transmit Data Register n
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXn : Stores the data to be transmitted and is automatically transferred to the transmit shift registers
bits : 0 - 23 (24 bit)
access : write-only
Receive FIFO Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFCNT : Receive FIFO Counter. These bits indicate the number of data words stored in the Receive FIFO.
bits : 0 - 7 (8 bit)
access : read-only
NRFO : Next Receiver FIFO Out. Indicates which receiver returns the top word of the Receive FIFO.
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : NRFO_0
Receiver #0 returns next word from the Receive FIFO.
0x1 : NRFO_1
Receiver #1 returns next word from the Receive FIFO.
0x2 : NRFO_2
Receiver #2 returns next word from the Receive FIFO.
0x3 : NRFO_3
Receiver #3 returns next word from the Receive FIFO.
End of enumeration elements list.
NRFI : Next Receiver FIFO In
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0 : NRFI_0
Receiver #0 returns next word to the Receive FIFO.
0x1 : NRFI_1
Receiver #1 returns next word to the Receive FIFO.
0x2 : NRFI_2
Receiver #2 returns next word to the Receive FIFO.
0x3 : NRFI_3
Receiver #3 returns next word to the Receive FIFO.
End of enumeration elements list.
Receive Data Register n
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXn : Accept data from the receive shift registers when they become full See ESAI Receive Shift Registers
bits : 0 - 23 (24 bit)
access : read-only
Transmit Data Register n
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXn : Stores the data to be transmitted and is automatically transferred to the transmit shift registers
bits : 0 - 23 (24 bit)
access : write-only
Receive Data Register n
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXn : Accept data from the receive shift registers when they become full See ESAI Receive Shift Registers
bits : 0 - 23 (24 bit)
access : read-only
Transmit Data Register n
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXn : Stores the data to be transmitted and is automatically transferred to the transmit shift registers
bits : 0 - 23 (24 bit)
access : write-only
Transmit Data Register n
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXn : Stores the data to be transmitted and is automatically transferred to the transmit shift registers
bits : 0 - 23 (24 bit)
access : write-only
Receive Data Register n
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXn : Accept data from the receive shift registers when they become full See ESAI Receive Shift Registers
bits : 0 - 23 (24 bit)
access : read-only
Transmit Data Register n
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXn : Stores the data to be transmitted and is automatically transferred to the transmit shift registers
bits : 0 - 23 (24 bit)
access : write-only
ESAI Receive Data Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERDR : ESAI Receive Data Register
bits : 0 - 31 (32 bit)
access : read-only
ESAI Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ESAIEN : ESAI Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ESAIEN_0
ESAI disabled.
0x1 : ESAIEN_1
ESAI enabled.
End of enumeration elements list.
ERST : ESAI Reset. Reset the ESAI core logic (including configuration registers) but not the ESAI FIFOs.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ERST_0
ESAI not reset.
0x1 : ERST_1
ESAI reset.
End of enumeration elements list.
ERO : EXTAL Receiver Out. Drive the EXTAL input on the High Frequency Receiver Clock pin.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : ERO_0
HCKR pin has normal function.
0x1 : ERO_1
EXTAL driven onto HCKR pin.
End of enumeration elements list.
ERI : EXTAL Receiver In
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : ERI_0
HCKR pin has normal function.
0x1 : ERI_1
EXTAL muxed into HCKR input.
End of enumeration elements list.
ETO : EXTAL Transmitter Out. Drive the EXTAL input on the High Frequency Transmitter Clock pin.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : ETO_0
HCKT pin has normal function.
0x1 : ETO_1
EXTAL driven onto HCKT pin.
End of enumeration elements list.
ETI : EXTAL Transmitter In
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : ETI_0
HCKT pin has normal function.
0x1 : ETI_1
EXTAL muxed into HCKT input.
End of enumeration elements list.
ESAI Transmit Slot Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSR : The write-only Transmit Slot Register (ESAI_TSR) is effectively a null data register that is used when the data is not to be transmitted in the available transmit time slot
bits : 0 - 23 (24 bit)
access : write-only
ESAI Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD : Receive Data.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : RD_0
RD is not the highest priority active interrupt.
0x1 : RD_1
RD is the highest priority active interrupt.
End of enumeration elements list.
RED : Receive Even Data.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : RED_0
RED is not the highest priority active interrupt.
0x1 : RED_1
RED is the highest priority active interrupt.
End of enumeration elements list.
RDE : Receive Data Exception.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : RDE_0
RDE is not the highest priority active interrupt.
0x1 : RDE_1
RDE is the highest priority active interrupt.
End of enumeration elements list.
RLS : Receive Last Slot
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : RLS_0
RLS is not the highest priority active interrupt.
0x1 : RLS_1
RLS is the highest priority active interrupt.
End of enumeration elements list.
TD : Transmit Data.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : TD_0
TD is not the highest priority active interrupt.
0x1 : TD_1
TD is the highest priority active interrupt.
End of enumeration elements list.
TED : Transmit Even Data.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : TED_0
TED is not the highest priority active interrupt.
0x1 : TED_1
TED is the highest priority active interrupt.
End of enumeration elements list.
TDE : Transmit Data Exception.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : TDE_0
TDE is not the highest priority active interrupt.
0x1 : TDE_1
TDE is the highest priority active interrupt.
End of enumeration elements list.
TLS : Transmit Last Slot
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : TLS_0
TLS is not the highest priority active interrupt.
0x1 : TLS_1
TLS is the highest priority active interrupt.
End of enumeration elements list.
TFE : Transmit FIFO Empty
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : TFE_0
Number of empty slots in Transmit FIFO less than Transmit FIFO watermark.
0x1 : TFE_1
Number of empty slots in Transmit FIFO is equal to or greater than Transmit FIFO watermark.
End of enumeration elements list.
RFF : Receive FIFO Full
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : RFF_0
Number of words in Receive FIFO less than Receive FIFO watermark.
0x1 : RFF_1
Number of words in Receive FIFO is equal to or greater than Receive FIFO watermark.
End of enumeration elements list.
TINIT : Transmit Initialization
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : TINIT_0
Transmitter has finished initializing the Transmit Data Registers (or Transmit FIFO is not enabled or Transmit Initialization is not enabled).
0x1 : TINIT_1
Transmitter has not finished initializing the Transmit Data Registers.
End of enumeration elements list.
Serial Audio Interface Status Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IF0 : ESAI_SAISR Serial Input Flag 0
bits : 0 - 0 (1 bit)
access : read-only
IF1 : ESAI_SAISR Serial Inout Flag 1
bits : 1 - 1 (1 bit)
access : read-only
IF2 : ESAI_SAISR Serial Input Flag 2
bits : 2 - 2 (1 bit)
access : read-only
RFS : ESAI_SAISR Receive Frame Sync Flag
bits : 6 - 6 (1 bit)
access : read-only
ROE : ESAI_SAISR Receive Overrun Error Flag
bits : 7 - 7 (1 bit)
access : read-only
RDF : ESAI_SAISR Receive Data Register Full
bits : 8 - 8 (1 bit)
access : read-only
REDF : ESAI_SAISR Receive Even-Data Register Full
bits : 9 - 9 (1 bit)
access : read-only
RODF : ESAI_SAISR Receive Odd-Data Register Full
bits : 10 - 10 (1 bit)
access : read-only
TFS : ESAI_SAISR Transmit Frame Sync Flag
bits : 13 - 13 (1 bit)
access : read-only
TUE : ESAI_SAISR Transmit Underrun Error Flag
bits : 14 - 14 (1 bit)
access : read-only
TDE : ESAI_SAISR Transmit Data Register Empty
bits : 15 - 15 (1 bit)
access : read-only
TEDE : ESAI_SAISR Transmit Even-DataRegister Empty
bits : 16 - 16 (1 bit)
access : read-only
TODFE : ESAI_SAISR Transmit Odd-Data Register Empty
bits : 17 - 17 (1 bit)
access : read-only
Serial Audio Interface Control Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OF0 : ESAI_SAICR Serial Output Flag 0
bits : 0 - 0 (1 bit)
access : read-write
OF1 : ESAI_SAICR Serial Output Flag 1
bits : 1 - 1 (1 bit)
access : read-write
OF2 : ESAI_SAICR Serial Output Flag 2
bits : 2 - 2 (1 bit)
access : read-write
SYN : ESAI_SAICR Synchronous Mode Selection
bits : 6 - 6 (1 bit)
access : read-write
TEBE : ESAI_SAICR Transmit External Buffer Enable
bits : 7 - 7 (1 bit)
access : read-write
ALC : ESAI_SAICR Alignment Control
bits : 8 - 8 (1 bit)
access : read-write
Transmit Control Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TE0 : ESAI_TCR ESAI Transmit 0 Enable
bits : 0 - 0 (1 bit)
access : read-write
TE1 : ESAI_TCR ESAI Transmit 1 Enable
bits : 1 - 1 (1 bit)
access : read-write
TE2 : ESAI_TCR ESAI Transmit 2 Enable
bits : 2 - 2 (1 bit)
access : read-write
TE3 : ESAI_TCR ESAI Transmit 3 Enable
bits : 3 - 3 (1 bit)
access : read-write
TE4 : ESAI_TCR ESAI Transmit 4 Enable
bits : 4 - 4 (1 bit)
access : read-write
TE5 : ESAI_TCR ESAI Transmit 5 Enable
bits : 5 - 5 (1 bit)
access : read-write
TSHFD : ESAI_TCR Transmit Shift Direction
bits : 6 - 6 (1 bit)
access : read-write
TWA : ESAI_TCR Transmit Word Alignment Control
bits : 7 - 7 (1 bit)
access : read-write
TMOD : ESAI_TCR Transmit Network Mode Control (TMOD1-TMOD0)
bits : 8 - 9 (2 bit)
access : read-write
TSWS : ESAI_TCR Tx Slot and Word Length Select (TSWS4-TSWS0)
bits : 10 - 14 (5 bit)
access : read-write
TFSL : ESAI_TCR Transmit Frame Sync Length
bits : 15 - 15 (1 bit)
access : read-write
TFSR : ESAI_TCR Transmit Frame Sync Relative Timing
bits : 16 - 16 (1 bit)
access : read-write
PADC : ESAI_TCR Transmit Zero Padding Control
bits : 17 - 17 (1 bit)
access : read-write
TPR : ESAI_TCR Transmit Section Personal Reset
bits : 19 - 19 (1 bit)
access : read-write
TEIE : ESAI_TCR Transmit Exception Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write
TEDIE : ESAI_TCR Transmit Even Slot Data Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write
TIE : ESAI_TCR Transmit Interrupt Enable
bits : 22 - 22 (1 bit)
access : read-write
TLIE : ESAI_TCR Transmit Last Slot Interrupt Enable
bits : 23 - 23 (1 bit)
access : read-write
Transmit Clock Control Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPM : ESAI_TCCR Transmit Prescale Modulus Select
bits : 0 - 7 (8 bit)
access : read-write
TPSR : ESAI_TCCR Transmit Prescaler Range
bits : 8 - 8 (1 bit)
access : read-write
TDC : ESAI_TCCR Tx Frame Rate Divider Control
bits : 9 - 13 (5 bit)
access : read-write
TFP : ESAI_TCCR Tx High Frequency Clock Divider
bits : 14 - 17 (4 bit)
access : read-write
TCKP : ESAI_TCCR Transmit Clock Polarity
bits : 18 - 18 (1 bit)
access : read-write
TFSP : ESAI_TCCR Transmit Frame Sync Polarity
bits : 19 - 19 (1 bit)
access : read-write
THCKP : ESAI_TCCR Transmit High Frequency Clock Polarity The Transmitter High Frequency Clock Polarity (THCKP) bit controls the polarity of the HCKT
bits : 20 - 20 (1 bit)
access : read-write
TCKD : ESAI_TCCR Transmit Clock Source Direction
bits : 21 - 21 (1 bit)
access : read-write
TFSD : ESAI_TCCR Transmit Frame Sync Signal Direction
bits : 22 - 22 (1 bit)
access : read-write
THCKD : ESAI_TCCR Transmit High Frequency Clock Direction
bits : 23 - 23 (1 bit)
access : read-write
Receive Control Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RE0 : ESAI_RCR ESAI Receiver 0 Enable
bits : 0 - 0 (1 bit)
access : read-write
RE1 : ESAI_RCR ESAI Receiver 1 Enable
bits : 1 - 1 (1 bit)
access : read-write
RE2 : ESAI_RCR ESAI Receiver 2 Enable
bits : 2 - 2 (1 bit)
access : read-write
RE3 : ESAI_RCR ESAI Receiver 3 Enable
bits : 3 - 3 (1 bit)
access : read-write
RSHFD : ESAI_RCR Receiver Shift Direction
bits : 6 - 6 (1 bit)
access : read-write
RWA : ESAI_RCR Receiver Word Alignment Control
bits : 7 - 7 (1 bit)
access : read-write
RMOD : ESAI_RCR Receiver Network Mode Control
bits : 8 - 9 (2 bit)
access : read-write
RSWS : ESAI_RCR Receiver Slot and Word Select
bits : 10 - 14 (5 bit)
access : read-write
RFSL : ESAI_RCR Receiver Frame Sync Length
bits : 15 - 15 (1 bit)
access : read-write
RFSR : ESAI_RCR Receiver Frame Sync Relative Timing
bits : 16 - 16 (1 bit)
access : read-write
RPR : ESAI_RCR Receiver Section Personal Reset
bits : 19 - 19 (1 bit)
access : read-write
REIE : ESAI_RCR Receive Exception Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write
REDIE : ESAI_RCR Receive Even Slot Data Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write
RIE : ESAI_RCR Receive Interrupt Enable
bits : 22 - 22 (1 bit)
access : read-write
RLIE : ESAI_RCR Receive Last Slot Interrupt Enable
bits : 23 - 23 (1 bit)
access : read-write
Receive Clock Control Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RPM : ESAI_RCCR Receiver Prescale Modulus Select
bits : 0 - 7 (8 bit)
access : read-write
RPSR : ESAI_RCCR Receiver Prescaler Range
bits : 8 - 8 (1 bit)
access : read-write
RDC : ESAI_RCCR Rx Frame Rate Divider Control
bits : 9 - 13 (5 bit)
access : read-write
RFP : ESAI_RCCR Rx High Frequency Clock Divider
bits : 14 - 17 (4 bit)
access : read-write
RCKP : The Receiver Clock Polarity (RCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in
bits : 18 - 18 (1 bit)
access : read-write
RFSP : ESAI_RCCR Receiver Frame Sync Polarity
bits : 19 - 19 (1 bit)
access : read-write
RHCKP : ESAI_RCCR Receiver High Frequency Clock Polarity
bits : 20 - 20 (1 bit)
access : read-write
RCKD : ESAI_RCCR Receiver Clock Source Direction
bits : 21 - 21 (1 bit)
access : read-write
RFSD : ESAI_RCCR Receiver Frame Sync Signal Direction
bits : 22 - 22 (1 bit)
access : read-write
RHCKD : ESAI_RCCR Receiver High Frequency Clock Direction
bits : 23 - 23 (1 bit)
access : read-write
Transmit Slot Mask Register A
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TS : Lower 16 bits of TS
bits : 0 - 15 (16 bit)
access : read-write
Transmit Slot Mask Register B
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TS : When bit number N in ESAI_TSMB is cleared, all the transmit data pins of the enabled transmitters are tri-stated during transmit time slot number N
bits : 0 - 15 (16 bit)
access : read-write
Receive Slot Mask Register A
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RS : When bit number N in the ESAI_RSMA register is cleared, the data from the enabled receivers input pins are shifted into their receive shift registers during slot number N
bits : 0 - 15 (16 bit)
access : read-write
Receive Slot Mask Register B
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RS : When bit number N in the ESAI_RSMB register is cleared, the data from the enabled receivers input pins are shifted into their receive shift registers during slot number N
bits : 0 - 15 (16 bit)
access : read-write
Port C Direction Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDC : See .
bits : 0 - 11 (12 bit)
access : read-write
Port C Control Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC : See .
bits : 0 - 11 (12 bit)
access : read-write
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