Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x170 byte (0x0)
mem_usage : registers
protection : not protected
Regulator 1P1 Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : Control bit to enable the regulator output.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : Control bit to enable the brownout circuitry in the regulator.
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator.
bits : 2 - 2 (1 bit)
access : read-write
ENABLE_PULLDOWN : Control bit to enable the pull-down circuitry in the regulator
bits : 3 - 3 (1 bit)
access : read-write
BO_OFFSET : Control bits to adjust the regulator brownout offset voltage in 25mV steps
bits : 4 - 6 (3 bit)
access : read-write
OUTPUT_TRG : Control bits to adjust the regulator output voltage
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0x4 : OUTPUT_TRG_4
0.8V
0x10 : OUTPUT_TRG_16
1.1V
End of enumeration elements list.
BO_VDD1P1 : Status bit that signals when a brownout is detected on the regulator output.
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD1P1 : Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target
bits : 17 - 17 (1 bit)
access : read-only
ENABLE_WEAK_LINREG : Enables the weak 1p1 regulator
bits : 18 - 18 (1 bit)
access : read-write
SELREF_WEAK_LINREG : Selects the source for the reference voltage of the weak 1p1 regulator.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SELREF_WEAK_LINREG_0
Weak-linreg output tracks low-power-bandgap voltage
0x1 : SELREF_WEAK_LINREG_1
Weak-linreg output tracks VDD_SOC_CAP voltage
End of enumeration elements list.
Regulator 3P0 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : Control bit to enable the brownout circuitry in the regulator.
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator.
bits : 2 - 2 (1 bit)
access : read-write
BO_OFFSET : Control bits to adjust the regulator brownout offset voltage in 25mV steps
bits : 4 - 6 (3 bit)
access : read-write
VBUS_SEL : Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : USB_OTG1_VBUS
Utilize VBUS OTG1 for power
0x1 : USB_OTG2_VBUS
Utilize VBUS OTG2 power
End of enumeration elements list.
OUTPUT_TRG : Control bits to adjust the regulator output voltage
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0 : OUTPUT_TRG_0
2.625V
0xF : OUTPUT_TRG_15
3.000V
0x1F : OUTPUT_TRG_31
3.400V
End of enumeration elements list.
BO_VDD3P0 : Status bit that signals when a brownout is detected on the regulator output.
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD3P0 : Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target
bits : 17 - 17 (1 bit)
access : read-only
Low Power Control Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC_OSC_EN : RC Osc. enable control.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RC_OSC_EN_0
Use XTAL OSC to source the 24MHz clock
0x1 : RC_OSC_EN_1
Use RC OSC
End of enumeration elements list.
RC_OSC_PROG : RC osc. tuning values.
bits : 1 - 3 (3 bit)
access : read-write
OSC_SEL : Select the source for the 24MHz clock.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : OSC_SEL_0
XTAL OSC
0x1 : OSC_SEL_1
RC OSC
End of enumeration elements list.
LPBG_SEL : Bandgap select. Not related to oscillator.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : LPBG_SEL_0
Normal power bandgap
0x1 : LPBG_SEL_1
Low power bandgap
End of enumeration elements list.
LPBG_TEST : Low power bandgap test bit. Not related to oscillator.
bits : 6 - 6 (1 bit)
access : read-write
REFTOP_IBIAS_OFF : Low power reftop ibias disable. Not related to oscillator.
bits : 7 - 7 (1 bit)
access : read-write
L1_PWRGATE : L1 power gate control. Used as software override. Not related to oscillator.
bits : 8 - 8 (1 bit)
access : read-write
L2_PWRGATE : L2 power gate control. Used as software override. Not related to oscillator.
bits : 9 - 9 (1 bit)
access : read-write
CPU_PWRGATE : CPU power gate control. Used as software override. Test purpose only Not related to oscillator.
bits : 10 - 10 (1 bit)
access : read-write
DISPLAY_PWRGATE : Display logic power gate control. Used as software override. Not related to oscillator.
bits : 11 - 11 (1 bit)
access : read-write
RCOSC_CG_OVERRIDE : For debug purposes only
bits : 13 - 13 (1 bit)
access : read-write
XTALOSC_PWRUP_DELAY : Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : XTALOSC_PWRUP_DELAY_0
0.25ms
0x1 : XTALOSC_PWRUP_DELAY_1
0.5ms
0x2 : XTALOSC_PWRUP_DELAY_2
1ms
0x3 : XTALOSC_PWRUP_DELAY_3
2ms
End of enumeration elements list.
XTALOSC_PWRUP_STAT : Status of the 24MHz xtal oscillator.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : XTALOSC_PWRUP_STAT_0
Not stable
0x1 : XTALOSC_PWRUP_STAT_1
Stable and ready to use
End of enumeration elements list.
MIX_PWRGATE : Display power gate control. Used as software mask. Set to zero to force ungated.
bits : 17 - 17 (1 bit)
access : read-write
Low Power Control Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC_OSC_EN : RC Osc. enable control. Not related to PMU.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RC_OSC_EN_0
Use XTAL OSC to source the 24MHz clock
0x1 : RC_OSC_EN_1
Use RC OSC
End of enumeration elements list.
RC_OSC_PROG : RC osc. tuning values. Not related to PMU.
bits : 1 - 3 (3 bit)
access : read-write
OSC_SEL : Select the source for the 24MHz clock. Not related to PMU.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : OSC_SEL_0
XTAL OSC
0x1 : OSC_SEL_1
RC OSC
End of enumeration elements list.
LPBG_SEL : Bandgap select.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : LPBG_SEL_0
Normal power bandgap
0x1 : LPBG_SEL_1
Low power bandgap
End of enumeration elements list.
LPBG_TEST : Low power bandgap test bit.
bits : 6 - 6 (1 bit)
access : read-write
REFTOP_IBIAS_OFF : Low power reftop ibias disable.
bits : 7 - 7 (1 bit)
access : read-write
L1_PWRGATE : L1 power gate control. Used as software override.
bits : 8 - 8 (1 bit)
access : read-write
L2_PWRGATE : L2 power gate control. Used as software override.
bits : 9 - 9 (1 bit)
access : read-write
CPU_PWRGATE : CPU power gate control. Used as software override.Test purpose only
bits : 10 - 10 (1 bit)
access : read-write
DISPLAY_PWRGATE : Display logic power gate control. Used as software override.
bits : 11 - 11 (1 bit)
access : read-write
RCOSC_CG_OVERRIDE : For debug purposes only
bits : 13 - 13 (1 bit)
access : read-write
XTALOSC_PWRUP_DELAY : Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : XTALOSC_PWRUP_DELAY_0
0.25ms
0x1 : XTALOSC_PWRUP_DELAY_1
0.5ms
0x2 : XTALOSC_PWRUP_DELAY_2
1ms
0x3 : XTALOSC_PWRUP_DELAY_3
2ms
End of enumeration elements list.
XTALOSC_PWRUP_STAT : Status of the 24MHz xtal oscillator. Not related to PMU.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : XTALOSC_PWRUP_STAT_0
Not stable
0x1 : XTALOSC_PWRUP_STAT_1
Stable and ready to use
End of enumeration elements list.
MIX_PWRGATE : Display power gate control. Used as software mask. Set to zero to force ungated.
bits : 17 - 17 (1 bit)
access : read-write
Low Power Control Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC_OSC_EN : RC Osc. enable control. Not related to PMU.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RC_OSC_EN_0
Use XTAL OSC to source the 24MHz clock
0x1 : RC_OSC_EN_1
Use RC OSC
End of enumeration elements list.
RC_OSC_PROG : RC osc. tuning values. Not related to PMU.
bits : 1 - 3 (3 bit)
access : read-write
OSC_SEL : Select the source for the 24MHz clock. Not related to PMU.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : OSC_SEL_0
XTAL OSC
0x1 : OSC_SEL_1
RC OSC
End of enumeration elements list.
LPBG_SEL : Bandgap select.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : LPBG_SEL_0
Normal power bandgap
0x1 : LPBG_SEL_1
Low power bandgap
End of enumeration elements list.
LPBG_TEST : Low power bandgap test bit.
bits : 6 - 6 (1 bit)
access : read-write
REFTOP_IBIAS_OFF : Low power reftop ibias disable.
bits : 7 - 7 (1 bit)
access : read-write
L1_PWRGATE : L1 power gate control. Used as software override.
bits : 8 - 8 (1 bit)
access : read-write
L2_PWRGATE : L2 power gate control. Used as software override.
bits : 9 - 9 (1 bit)
access : read-write
CPU_PWRGATE : CPU power gate control. Used as software override.Test purpose only
bits : 10 - 10 (1 bit)
access : read-write
DISPLAY_PWRGATE : Display logic power gate control. Used as software override.
bits : 11 - 11 (1 bit)
access : read-write
RCOSC_CG_OVERRIDE : For debug purposes only
bits : 13 - 13 (1 bit)
access : read-write
XTALOSC_PWRUP_DELAY : Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : XTALOSC_PWRUP_DELAY_0
0.25ms
0x1 : XTALOSC_PWRUP_DELAY_1
0.5ms
0x2 : XTALOSC_PWRUP_DELAY_2
1ms
0x3 : XTALOSC_PWRUP_DELAY_3
2ms
End of enumeration elements list.
XTALOSC_PWRUP_STAT : Status of the 24MHz xtal oscillator. Not related to PMU.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : XTALOSC_PWRUP_STAT_0
Not stable
0x1 : XTALOSC_PWRUP_STAT_1
Stable and ready to use
End of enumeration elements list.
MIX_PWRGATE : Display power gate control. Used as software mask. Set to zero to force ungated.
bits : 17 - 17 (1 bit)
access : read-write
Low Power Control Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC_OSC_EN : RC Osc. enable control. Not related to PMU.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RC_OSC_EN_0
Use XTAL OSC to source the 24MHz clock
0x1 : RC_OSC_EN_1
Use RC OSC
End of enumeration elements list.
RC_OSC_PROG : RC osc. tuning values. Not related to PMU.
bits : 1 - 3 (3 bit)
access : read-write
OSC_SEL : Select the source for the 24MHz clock. Not related to PMU.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : OSC_SEL_0
XTAL OSC
0x1 : OSC_SEL_1
RC OSC
End of enumeration elements list.
LPBG_SEL : Bandgap select.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : LPBG_SEL_0
Normal power bandgap
0x1 : LPBG_SEL_1
Low power bandgap
End of enumeration elements list.
LPBG_TEST : Low power bandgap test bit.
bits : 6 - 6 (1 bit)
access : read-write
REFTOP_IBIAS_OFF : Low power reftop ibias disable.
bits : 7 - 7 (1 bit)
access : read-write
L1_PWRGATE : L1 power gate control. Used as software override.
bits : 8 - 8 (1 bit)
access : read-write
L2_PWRGATE : L2 power gate control. Used as software override.
bits : 9 - 9 (1 bit)
access : read-write
CPU_PWRGATE : CPU power gate control. Used as software override.Test purpose only
bits : 10 - 10 (1 bit)
access : read-write
DISPLAY_PWRGATE : Display logic power gate control. Used as software override.
bits : 11 - 11 (1 bit)
access : read-write
RCOSC_CG_OVERRIDE : For debug purposes only
bits : 13 - 13 (1 bit)
access : read-write
XTALOSC_PWRUP_DELAY : Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : XTALOSC_PWRUP_DELAY_0
0.25ms
0x1 : XTALOSC_PWRUP_DELAY_1
0.5ms
0x2 : XTALOSC_PWRUP_DELAY_2
1ms
0x3 : XTALOSC_PWRUP_DELAY_3
2ms
End of enumeration elements list.
XTALOSC_PWRUP_STAT : Status of the 24MHz xtal oscillator. Not related to PMU.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : XTALOSC_PWRUP_STAT_0
Not stable
0x1 : XTALOSC_PWRUP_STAT_1
Stable and ready to use
End of enumeration elements list.
MIX_PWRGATE : Display power gate control. Used as software mask. Set to zero to force ungated.
bits : 17 - 17 (1 bit)
access : read-write
Regulator 2P5 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : Control bit to enable the regulator output.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : Control bit to enable the brownout circuitry in the regulator.
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator.
bits : 2 - 2 (1 bit)
access : read-write
ENABLE_PULLDOWN : Control bit to enable the pull-down circuitry in the regulator
bits : 3 - 3 (1 bit)
access : read-write
BO_OFFSET : Control bits to adjust the regulator brownout offset voltage in 25mV steps
bits : 4 - 6 (3 bit)
access : read-write
OUTPUT_TRG : Control bits to adjust the regulator output voltage
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0 : OUTPUT_TRG_0
2.10V
0x10 : OUTPUT_TRG_16
2.50V
0x1F : OUTPUT_TRG_31
2.875V
End of enumeration elements list.
BO_VDD2P5 : Status bit that signals when a brownout is detected on the regulator output.
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD2P5 : Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target
bits : 17 - 17 (1 bit)
access : read-only
ENABLE_WEAK_LINREG : Enables the weak 2p5 regulator
bits : 18 - 18 (1 bit)
access : read-write
Digital Regulator Core Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG0_TARG : This field defines the target voltage for the ARM core power domain
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : REG0_TARG_0
Power gated off
0x1 : REG0_TARG_1
Target core voltage = 0.725V
0x2 : REG0_TARG_2
Target core voltage = 0.750V
0x3 : REG0_TARG_3
Target core voltage = 0.775V
0x10 : REG0_TARG_16
Target core voltage = 1.100V
0x1E : REG0_TARG_30
Target core voltage = 1.450V
0x1F : REG0_TARG_31
Power FET switched full on. No regulation.
End of enumeration elements list.
REG2_TARG : This field defines the target voltage for the SOC power domain
bits : 18 - 22 (5 bit)
access : read-write
Enumeration:
0 : REG2_TARG_0
Power gated off
0x1 : REG2_TARG_1
Target core voltage = 0.725V
0x2 : REG2_TARG_2
Target core voltage = 0.750V
0x3 : REG2_TARG_3
Target core voltage = 0.775V
0x10 : REG2_TARG_16
Target core voltage = 1.100V
0x1E : REG2_TARG_30
Target core voltage = 1.450V
0x1F : REG2_TARG_31
Power FET switched full on. No regulation.
End of enumeration elements list.
RAMP_RATE : Regulator voltage ramp rate.
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
0 : RAMP_RATE_0
Fast
0x1 : RAMP_RATE_1
Medium Fast
0x2 : RAMP_RATE_2
Medium Slow
0x3 : RAMP_RATE_3
Slow
End of enumeration elements list.
FET_ODRIVE : If set, increases the gate drive on power gating FETs to reduce leakage in the off state
bits : 29 - 29 (1 bit)
access : read-write
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