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XTALOSC24M

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected

Registers

OSC_CONFIG0

OSC_CONFIG1

OSC_CONFIG1_SET

OSC_CONFIG1_CLR

OSC_CONFIG1_TOG

OSC_CONFIG2

OSC_CONFIG2_SET

OSC_CONFIG2_CLR

OSC_CONFIG2_TOG

OSC_CONFIG0_SET

OSC_CONFIG0_CLR

OSC_CONFIG0_TOG


OSC_CONFIG0

XTAL OSC Configuration 0 Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC_CONFIG0 OSC_CONFIG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START ENABLE BYPASS INVERT RC_OSC_PROG HYST_PLUS HYST_MINUS RC_OSC_PROG_CUR

START : Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.
bits : 0 - 0 (1 bit)
access : read-write

ENABLE : Enables the tuning logic to calculate new RC tuning values
bits : 1 - 1 (1 bit)
access : read-write

BYPASS : Bypasses any calculated RC tuning value and uses the programmed register value.
bits : 2 - 2 (1 bit)
access : read-write

INVERT : Invert the stepping of the calculated RC tuning value.
bits : 3 - 3 (1 bit)
access : read-write

RC_OSC_PROG : RC osc. tuning values.
bits : 4 - 11 (8 bit)
access : read-write

HYST_PLUS : Positive hysteresis value
bits : 12 - 15 (4 bit)
access : read-write

HYST_MINUS : Negative hysteresis value
bits : 16 - 19 (4 bit)
access : read-write

RC_OSC_PROG_CUR : The current tuning value in use.
bits : 24 - 31 (8 bit)
access : read-write


OSC_CONFIG1

XTAL OSC Configuration 1 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC_CONFIG1 OSC_CONFIG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT_RC_TRG COUNT_RC_CUR

COUNT_RC_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write

COUNT_RC_CUR : The current tuning value in use.
bits : 20 - 31 (12 bit)
access : read-write


OSC_CONFIG1_SET

XTAL OSC Configuration 1 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC_CONFIG1_SET OSC_CONFIG1_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT_RC_TRG COUNT_RC_CUR

COUNT_RC_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write

COUNT_RC_CUR : The current tuning value in use.
bits : 20 - 31 (12 bit)
access : read-write


OSC_CONFIG1_CLR

XTAL OSC Configuration 1 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC_CONFIG1_CLR OSC_CONFIG1_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT_RC_TRG COUNT_RC_CUR

COUNT_RC_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write

COUNT_RC_CUR : The current tuning value in use.
bits : 20 - 31 (12 bit)
access : read-write


OSC_CONFIG1_TOG

XTAL OSC Configuration 1 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC_CONFIG1_TOG OSC_CONFIG1_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT_RC_TRG COUNT_RC_CUR

COUNT_RC_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write

COUNT_RC_CUR : The current tuning value in use.
bits : 20 - 31 (12 bit)
access : read-write


OSC_CONFIG2

XTAL OSC Configuration 2 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC_CONFIG2 OSC_CONFIG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT_1M_TRG ENABLE_1M MUX_1M CLK_1M_ERR_FL

COUNT_1M_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write

ENABLE_1M : Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
bits : 16 - 16 (1 bit)
access : read-write

MUX_1M : Mux the corrected or uncorrected 1MHz clock to the output.
bits : 17 - 17 (1 bit)
access : read-write

CLK_1M_ERR_FL : Flag indicates that the count_1m count wasn't reached within 1 32KHz period
bits : 31 - 31 (1 bit)
access : read-write


OSC_CONFIG2_SET

XTAL OSC Configuration 2 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC_CONFIG2_SET OSC_CONFIG2_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT_1M_TRG ENABLE_1M MUX_1M CLK_1M_ERR_FL

COUNT_1M_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write

ENABLE_1M : Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
bits : 16 - 16 (1 bit)
access : read-write

MUX_1M : Mux the corrected or uncorrected 1MHz clock to the output.
bits : 17 - 17 (1 bit)
access : read-write

CLK_1M_ERR_FL : Flag indicates that the count_1m count wasn't reached within 1 32KHz period
bits : 31 - 31 (1 bit)
access : read-write


OSC_CONFIG2_CLR

XTAL OSC Configuration 2 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC_CONFIG2_CLR OSC_CONFIG2_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT_1M_TRG ENABLE_1M MUX_1M CLK_1M_ERR_FL

COUNT_1M_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write

ENABLE_1M : Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
bits : 16 - 16 (1 bit)
access : read-write

MUX_1M : Mux the corrected or uncorrected 1MHz clock to the output.
bits : 17 - 17 (1 bit)
access : read-write

CLK_1M_ERR_FL : Flag indicates that the count_1m count wasn't reached within 1 32KHz period
bits : 31 - 31 (1 bit)
access : read-write


OSC_CONFIG2_TOG

XTAL OSC Configuration 2 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC_CONFIG2_TOG OSC_CONFIG2_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT_1M_TRG ENABLE_1M MUX_1M CLK_1M_ERR_FL

COUNT_1M_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write

ENABLE_1M : Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
bits : 16 - 16 (1 bit)
access : read-write

MUX_1M : Mux the corrected or uncorrected 1MHz clock to the output.
bits : 17 - 17 (1 bit)
access : read-write

CLK_1M_ERR_FL : Flag indicates that the count_1m count wasn't reached within 1 32KHz period
bits : 31 - 31 (1 bit)
access : read-write


OSC_CONFIG0_SET

XTAL OSC Configuration 0 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC_CONFIG0_SET OSC_CONFIG0_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START ENABLE BYPASS INVERT RC_OSC_PROG HYST_PLUS HYST_MINUS RC_OSC_PROG_CUR

START : Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.
bits : 0 - 0 (1 bit)
access : read-write

ENABLE : Enables the tuning logic to calculate new RC tuning values
bits : 1 - 1 (1 bit)
access : read-write

BYPASS : Bypasses any calculated RC tuning value and uses the programmed register value.
bits : 2 - 2 (1 bit)
access : read-write

INVERT : Invert the stepping of the calculated RC tuning value.
bits : 3 - 3 (1 bit)
access : read-write

RC_OSC_PROG : RC osc. tuning values.
bits : 4 - 11 (8 bit)
access : read-write

HYST_PLUS : Positive hysteresis value
bits : 12 - 15 (4 bit)
access : read-write

HYST_MINUS : Negative hysteresis value
bits : 16 - 19 (4 bit)
access : read-write

RC_OSC_PROG_CUR : The current tuning value in use.
bits : 24 - 31 (8 bit)
access : read-write


OSC_CONFIG0_CLR

XTAL OSC Configuration 0 Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC_CONFIG0_CLR OSC_CONFIG0_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START ENABLE BYPASS INVERT RC_OSC_PROG HYST_PLUS HYST_MINUS RC_OSC_PROG_CUR

START : Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.
bits : 0 - 0 (1 bit)
access : read-write

ENABLE : Enables the tuning logic to calculate new RC tuning values
bits : 1 - 1 (1 bit)
access : read-write

BYPASS : Bypasses any calculated RC tuning value and uses the programmed register value.
bits : 2 - 2 (1 bit)
access : read-write

INVERT : Invert the stepping of the calculated RC tuning value.
bits : 3 - 3 (1 bit)
access : read-write

RC_OSC_PROG : RC osc. tuning values.
bits : 4 - 11 (8 bit)
access : read-write

HYST_PLUS : Positive hysteresis value
bits : 12 - 15 (4 bit)
access : read-write

HYST_MINUS : Negative hysteresis value
bits : 16 - 19 (4 bit)
access : read-write

RC_OSC_PROG_CUR : The current tuning value in use.
bits : 24 - 31 (8 bit)
access : read-write


OSC_CONFIG0_TOG

XTAL OSC Configuration 0 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC_CONFIG0_TOG OSC_CONFIG0_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START ENABLE BYPASS INVERT RC_OSC_PROG HYST_PLUS HYST_MINUS RC_OSC_PROG_CUR

START : Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.
bits : 0 - 0 (1 bit)
access : read-write

ENABLE : Enables the tuning logic to calculate new RC tuning values
bits : 1 - 1 (1 bit)
access : read-write

BYPASS : Bypasses any calculated RC tuning value and uses the programmed register value.
bits : 2 - 2 (1 bit)
access : read-write

INVERT : Invert the stepping of the calculated RC tuning value.
bits : 3 - 3 (1 bit)
access : read-write

RC_OSC_PROG : RC osc. tuning values.
bits : 4 - 11 (8 bit)
access : read-write

HYST_PLUS : Positive hysteresis value
bits : 12 - 15 (4 bit)
access : read-write

HYST_MINUS : Negative hysteresis value
bits : 16 - 19 (4 bit)
access : read-write

RC_OSC_PROG_CUR : The current tuning value in use.
bits : 24 - 31 (8 bit)
access : read-write



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