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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

Registers

HC0

CFG

GC

GS

CV

OFS

CAL

HS

R0


HC0

Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HC0 HC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCH AIEN

ADCH : Input Channel Select
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x19 : ADCH_25

VREFSH = internal channel, for ADC self-test, hard connected to VRH internally

0x1F : ADCH_31

Conversion Disabled.

End of enumeration elements list.

AIEN : Conversion Complete Interrupt Enable/Disable Control
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : AIEN_0

Conversion complete interrupt disabled

0x1 : AIEN_1

Conversion complete interrupt enabled

End of enumeration elements list.


CFG

Configuration register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADICLK MODE ADLSMP ADIV ADLPC ADSTS ADHSC REFSEL ADTRG AVGS OVWREN

ADICLK : Input Clock Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : ADICLK_0

IPG clock

0x1 : ADICLK_1

IPG clock divided by 2

0x3 : ADICLK_3

Asynchronous clock (ADACK)

End of enumeration elements list.

MODE : Conversion Mode Selection
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0 : MODE_0

8-bit conversion

0x1 : MODE_1

10-bit conversion

0x2 : MODE_2

12-bit conversion

End of enumeration elements list.

ADLSMP : Long Sample Time Configuration
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : ADLSMP_0

Short sample mode.

0x1 : ADLSMP_1

Long sample mode.

End of enumeration elements list.

ADIV : Clock Divide Select
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

0 : ADIV_0

Input clock

0x1 : ADIV_1

Input clock / 2

0x2 : ADIV_2

Input clock / 4

0x3 : ADIV_3

Input clock / 8

End of enumeration elements list.

ADLPC : Low-Power Configuration
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : ADLPC_0

ADC hard block not in low power mode.

0x1 : ADLPC_1

ADC hard block in low power mode.

End of enumeration elements list.

ADSTS : Defines the sample time duration
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : ADSTS_0

Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b

0x1 : ADSTS_1

Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b

0x2 : ADSTS_2

Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b

0x3 : ADSTS_3

Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b

End of enumeration elements list.

ADHSC : High Speed Configuration
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : ADHSC_0

Normal conversion selected.

0x1 : ADHSC_1

High speed conversion selected.

End of enumeration elements list.

REFSEL : Voltage Reference Selection
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : REFSEL_0

Selects VREFH/VREFL as reference voltage.

End of enumeration elements list.

ADTRG : Conversion Trigger Select
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : ADTRG_0

Software trigger selected

End of enumeration elements list.

AVGS : Hardware Average select
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : AVGS_0

4 samples averaged

0x1 : AVGS_1

8 samples averaged

0x2 : AVGS_2

16 samples averaged

0x3 : AVGS_3

32 samples averaged

End of enumeration elements list.

OVWREN : Data Overwrite Enable
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : OVWREN_0

Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data.

0x1 : OVWREN_1

Enable the overwriting.

End of enumeration elements list.


GC

General control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GC GC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADACKEN DMAEN ACREN ACFGT ACFE AVGE ADCO CAL

ADACKEN : Asynchronous clock output enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : ADACKEN_0

Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active.

0x1 : ADACKEN_1

Asynchronous clock and clock output enabled regardless of the state of the ADC

End of enumeration elements list.

DMAEN : DMA Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DMAEN_0

DMA disabled (default)

0x1 : DMAEN_1

DMA enabled

End of enumeration elements list.

ACREN : Compare Function Range Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : ACREN_0

Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared.

0x1 : ACREN_1

Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared.

End of enumeration elements list.

ACFGT : Compare Function Greater Than Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : ACFGT_0

Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register.

0x1 : ACFGT_1

Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers.

End of enumeration elements list.

ACFE : Compare Function Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : ACFE_0

Compare function disabled

0x1 : ACFE_1

Compare function enabled

End of enumeration elements list.

AVGE : Hardware average enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : AVGE_0

Hardware average function disabled

0x1 : AVGE_1

Hardware average function enabled

End of enumeration elements list.

ADCO : Continuous Conversion Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : ADCO_0

One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.

0x1 : ADCO_1

Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.

End of enumeration elements list.

CAL : Calibration
bits : 7 - 7 (1 bit)
access : read-write


GS

General status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GS GS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADACT CALF AWKST

ADACT : Conversion Active
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : ADACT_0

Conversion not in progress.

0x1 : ADACT_1

Conversion in progress.

End of enumeration elements list.

CALF : Calibration Failed Flag
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : CALF_0

Calibration completed normally.

0x1 : CALF_1

Calibration failed. ADC accuracy specifications are not guaranteed.

End of enumeration elements list.

AWKST : Asynchronous wakeup interrupt status
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : AWKST_0

No asynchronous interrupt.

0x1 : AWKST_1

Asynnchronous wake up interrupt occured in stop mode.

End of enumeration elements list.


CV

Compare value register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CV CV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CV1 CV2

CV1 : Compare Value 1
bits : 0 - 11 (12 bit)
access : read-write

CV2 : Compare Value 2
bits : 16 - 27 (12 bit)
access : read-write


OFS

Offset correction value register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFS OFS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFS SIGN

OFS : Offset value
bits : 0 - 11 (12 bit)
access : read-write

SIGN : Sign bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SIGN_0

The offset value is added with the raw result

0x1 : SIGN_1

The offset value is subtracted from the raw converted value

End of enumeration elements list.


CAL

Calibration value register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAL CAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAL_CODE

CAL_CODE : Calibration Result Value
bits : 0 - 3 (4 bit)
access : read-write


HS

Status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HS HS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COCO0

COCO0 : Conversion Complete Flag
bits : 0 - 0 (1 bit)
access : read-only


R0

Data result register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R0 R0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDATA

CDATA : Data (result of an ADC conversion)
bits : 0 - 11 (12 bit)
access : read-only



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