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address_offset : 0x0 Bytes (0x0)
size : 0x120 byte (0x0)
mem_usage : registers
protection : not protected
Anadig ARM PLL control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider
bits : 0 - 6 (7 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Analog debug bit.
bits : 11 - 11 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : Enable the clock output.
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
LVDS_SEL : no description available
bits : 17 - 17 (1 bit)
access : read-write
LVDS_24MHZ_SEL : no description available
bits : 18 - 18 (1 bit)
access : read-write
PLL_SEL : no description available
bits : 19 - 19 (1 bit)
access : read-write
PLL_ARM_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 20 - 20 (1 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 21 - 30 (10 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig DDR PLL Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider. Valid values for divider: 33 to 44.
bits : 0 - 6 (7 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Status of ana_irq2 input from analog block.
bits : 11 - 11 (1 bit)
access : read-write
DIV2_ENABLE_CLK : no description available
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : no description available
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
PLL_DDR_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 19 - 19 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 20 - 20 (1 bit)
access : read-write
TEST_DIV_SELECT : Control bits for the post divider for the PLL clk and lvds outputs: 0x0=div-by-4(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-1
bits : 21 - 22 (2 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 23 - 30 (8 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Denominator of Video PLL Fractional Loop Divider Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B : 30 bit Denominator of fractional loop divider.
bits : 0 - 29 (30 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 30 - 31 (2 bit)
access : read-only
Miscellaneous0 Analog Clock Control and Status Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDS1_CLK_SEL : This field selects the clock to be routed to anaclk1/1b 0x00 - Arm PLL; 0x01 - 480 PLL; 0x02 - pfd0; 0x03 - pfd1; 0x04 - pfd2; 0x05 - pfd3; 0x06 - pfd4; 0x07 - pfd5; 0x08 - pfd6; 0x09 - pfd7; 0x0A - Audio PLL; 0x0B - Video PLL; 0x0C - pll_enet_div2 (500MHz); 0x0D - pll_enet_div4 (250MHz); 0x0E - pll_enet_div8 (125MHz); 0x0F - pll_enet_div10 (100MHz); 0x10 - pll_enet_div20 (50MHz); 0x11 - pll_enet_div25 (40MHz); 0x12 - pll_enet_div40 (25MHz); 0x13 - pll_ddr; 0x14 - RC_OSC24; 0x15 - clk24mhz; 0x16 - anatest ring oscillators; 0x17 - aclk2_loopback; 0x18-0x1F - Reserved
bits : 0 - 4 (5 bit)
access : read-write
LVDSCLK1_OBEN : This enables the lvds output buffer for anaclk1/1b
bits : 5 - 5 (1 bit)
access : read-write
LVDSCLK1_IBEN : This enables the lvds input buffer for anaclk1/1b
bits : 6 - 6 (1 bit)
access : read-write
ACLK2_PREDIV : Predivider ACLK2 source/reference clock of the PLL's
bits : 7 - 7 (1 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 8 - 31 (24 bit)
access : read-only
Miscellaneous0 Analog Clock Control and Status Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDS1_CLK_SEL : This field selects the clock to be routed to anaclk1/1b 0x00 - Arm PLL; 0x01 - 480 PLL; 0x02 - pfd0; 0x03 - pfd1; 0x04 - pfd2; 0x05 - pfd3; 0x06 - pfd4; 0x07 - pfd5; 0x08 - pfd6; 0x09 - pfd7; 0x0A - Audio PLL; 0x0B - Video PLL; 0x0C - pll_enet_div2 (500MHz); 0x0D - pll_enet_div4 (250MHz); 0x0E - pll_enet_div8 (125MHz); 0x0F - pll_enet_div10 (100MHz); 0x10 - pll_enet_div20 (50MHz); 0x11 - pll_enet_div25 (40MHz); 0x12 - pll_enet_div40 (25MHz); 0x13 - pll_ddr; 0x14 - RC_OSC24; 0x15 - clk24mhz; 0x16 - anatest ring oscillators; 0x17 - aclk2_loopback; 0x18-0x1F - Reserved
bits : 0 - 4 (5 bit)
access : read-write
LVDSCLK1_OBEN : This enables the lvds output buffer for anaclk1/1b
bits : 5 - 5 (1 bit)
access : read-write
LVDSCLK1_IBEN : This enables the lvds input buffer for anaclk1/1b
bits : 6 - 6 (1 bit)
access : read-write
ACLK2_PREDIV : Predivider ACLK2 source/reference clock of the PLL's
bits : 7 - 7 (1 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 8 - 31 (24 bit)
access : read-only
Miscellaneous0 Analog Clock Control and Status Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDS1_CLK_SEL : This field selects the clock to be routed to anaclk1/1b 0x00 - Arm PLL; 0x01 - 480 PLL; 0x02 - pfd0; 0x03 - pfd1; 0x04 - pfd2; 0x05 - pfd3; 0x06 - pfd4; 0x07 - pfd5; 0x08 - pfd6; 0x09 - pfd7; 0x0A - Audio PLL; 0x0B - Video PLL; 0x0C - pll_enet_div2 (500MHz); 0x0D - pll_enet_div4 (250MHz); 0x0E - pll_enet_div8 (125MHz); 0x0F - pll_enet_div10 (100MHz); 0x10 - pll_enet_div20 (50MHz); 0x11 - pll_enet_div25 (40MHz); 0x12 - pll_enet_div40 (25MHz); 0x13 - pll_ddr; 0x14 - RC_OSC24; 0x15 - clk24mhz; 0x16 - anatest ring oscillators; 0x17 - aclk2_loopback; 0x18-0x1F - Reserved
bits : 0 - 4 (5 bit)
access : read-write
LVDSCLK1_OBEN : This enables the lvds output buffer for anaclk1/1b
bits : 5 - 5 (1 bit)
access : read-write
LVDSCLK1_IBEN : This enables the lvds input buffer for anaclk1/1b
bits : 6 - 6 (1 bit)
access : read-write
ACLK2_PREDIV : Predivider ACLK2 source/reference clock of the PLL's
bits : 7 - 7 (1 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 8 - 31 (24 bit)
access : read-only
Miscellaneous0 Analog Clock Control and Status Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDS1_CLK_SEL : This field selects the clock to be routed to anaclk1/1b 0x00 - Arm PLL; 0x01 - 480 PLL; 0x02 - pfd0; 0x03 - pfd1; 0x04 - pfd2; 0x05 - pfd3; 0x06 - pfd4; 0x07 - pfd5; 0x08 - pfd6; 0x09 - pfd7; 0x0A - Audio PLL; 0x0B - Video PLL; 0x0C - pll_enet_div2 (500MHz); 0x0D - pll_enet_div4 (250MHz); 0x0E - pll_enet_div8 (125MHz); 0x0F - pll_enet_div10 (100MHz); 0x10 - pll_enet_div20 (50MHz); 0x11 - pll_enet_div25 (40MHz); 0x12 - pll_enet_div40 (25MHz); 0x13 - pll_ddr; 0x14 - RC_OSC24; 0x15 - clk24mhz; 0x16 - anatest ring oscillators; 0x17 - aclk2_loopback; 0x18-0x1F - Reserved
bits : 0 - 4 (5 bit)
access : read-write
LVDSCLK1_OBEN : This enables the lvds output buffer for anaclk1/1b
bits : 5 - 5 (1 bit)
access : read-write
LVDSCLK1_IBEN : This enables the lvds input buffer for anaclk1/1b
bits : 6 - 6 (1 bit)
access : read-write
ACLK2_PREDIV : Predivider ACLK2 source/reference clock of the PLL's
bits : 7 - 7 (1 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 8 - 31 (24 bit)
access : read-only
Anadig DDR PLL Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider. Valid values for divider: 33 to 44.
bits : 0 - 6 (7 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Status of ana_irq2 input from analog block.
bits : 11 - 11 (1 bit)
access : read-write
DIV2_ENABLE_CLK : no description available
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : no description available
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
PLL_DDR_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 19 - 19 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 20 - 20 (1 bit)
access : read-write
TEST_DIV_SELECT : Control bits for the post divider for the PLL clk and lvds outputs: 0x0=div-by-4(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-1
bits : 21 - 22 (2 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 23 - 30 (8 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig DDR PLL Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider. Valid values for divider: 33 to 44.
bits : 0 - 6 (7 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Status of ana_irq2 input from analog block.
bits : 11 - 11 (1 bit)
access : read-write
DIV2_ENABLE_CLK : no description available
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : no description available
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
PLL_DDR_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 19 - 19 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 20 - 20 (1 bit)
access : read-write
TEST_DIV_SELECT : Control bits for the post divider for the PLL clk and lvds outputs: 0x0=div-by-4(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-1
bits : 21 - 22 (2 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 23 - 30 (8 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig DDR PLL Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider. Valid values for divider: 33 to 44.
bits : 0 - 6 (7 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Status of ana_irq2 input from analog block.
bits : 11 - 11 (1 bit)
access : read-write
DIV2_ENABLE_CLK : no description available
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : no description available
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
PLL_DDR_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 19 - 19 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 20 - 20 (1 bit)
access : read-write
TEST_DIV_SELECT : Control bits for the post divider for the PLL clk and lvds outputs: 0x0=div-by-4(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-1
bits : 21 - 22 (2 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 23 - 30 (8 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
DDR PLL Spread Spectrum Register.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STEP : The max frequency change = stop/B*24MHz.
bits : 0 - 14 (15 bit)
access : read-write
ENABLE : This bit enables the spread spectrum modulation.
bits : 15 - 15 (1 bit)
access : read-write
STOP : Frequency change = step/B*24MHz.
bits : 16 - 31 (16 bit)
access : read-write
Numerator of DDR PLL Fractional Loop Divider Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A : 30 bit numerator (A) of fractional loop divider (signed integer).
bits : 0 - 29 (30 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 30 - 31 (2 bit)
access : read-only
Anadig ARM PLL control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider
bits : 0 - 6 (7 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Analog debug bit.
bits : 11 - 11 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : Enable the clock output.
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
LVDS_SEL : no description available
bits : 17 - 17 (1 bit)
access : read-write
LVDS_24MHZ_SEL : no description available
bits : 18 - 18 (1 bit)
access : read-write
PLL_SEL : no description available
bits : 19 - 19 (1 bit)
access : read-write
PLL_ARM_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 20 - 20 (1 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 21 - 30 (10 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Denominator of DDR PLL Fractional Loop Divider Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B : 30 bit Denominator (B) of fractional loop divider (signed integer).
bits : 0 - 29 (30 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 30 - 31 (2 bit)
access : read-only
Anadig 480MHz PLL Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider. 0 - Fout=480MHz; 1 - Fout=528MHz.
bits : 0 - 0 (1 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 1 - 3 (3 bit)
access : read-only
MAIN_DIV1_CLKGATE : If set to 1, pll_sys_main_480m_clk is off (power savings). 0: pll_sys_main_480m_clk is enabled.
bits : 4 - 4 (1 bit)
access : read-write
MAIN_DIV2_CLKGATE : If set to 1, pll_sys_main_240m_clk is off (power savings). 0: pll_sys_main_240m_clk is enabled.
bits : 5 - 5 (1 bit)
access : read-write
MAIN_DIV4_CLKGATE : If set to 1, pll_sys_main_120m_clk is off (power savings). 0: pll_sys_main_120m_clk is enabled.
bits : 6 - 6 (1 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Analog debug bit.
bits : 11 - 11 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : Enable the clock output.
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
PLL_480_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 17 - 17 (1 bit)
access : read-write
PFD0_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 18 - 18 (1 bit)
access : read-write
PFD1_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 19 - 19 (1 bit)
access : read-write
PFD2_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 20 - 20 (1 bit)
access : read-write
PFD3_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 21 - 21 (1 bit)
access : read-write
PFD4_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 22 - 22 (1 bit)
access : read-write
PFD5_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 23 - 23 (1 bit)
access : read-write
PFD6_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 24 - 24 (1 bit)
access : read-write
PFD7_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 25 - 25 (1 bit)
access : read-write
PFD0_DIV2_CLKGATE : If set to 1, pll_sys_pfd0_196m_clk is off (power savings). 0: pll_sys_pfd0_196m_clk is enabled.
bits : 26 - 26 (1 bit)
access : read-write
PFD1_DIV2_CLKGATE : If set to 1, pll_sys_pfd1_166m_clk is off (power savings). 0: pll_sys_pfd1_166m_clk is enabled.
bits : 27 - 27 (1 bit)
access : read-write
PFD2_DIV2_CLKGATE : If set to 1, pll_sys_pfd2_135m_clk is off (power savings). 0: pll_sys_pfd2_135m_clk is enabled.
bits : 28 - 28 (1 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 29 - 30 (2 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig 480MHz PLL Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider. 0 - Fout=480MHz; 1 - Fout=528MHz.
bits : 0 - 0 (1 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 1 - 3 (3 bit)
access : read-only
MAIN_DIV1_CLKGATE : If set to 1, pll_sys_main_480m_clk is off (power savings). 0: pll_sys_main_480m_clk is enabled.
bits : 4 - 4 (1 bit)
access : read-write
MAIN_DIV2_CLKGATE : If set to 1, pll_sys_main_240m_clk is off (power savings). 0: pll_sys_main_240m_clk is enabled.
bits : 5 - 5 (1 bit)
access : read-write
MAIN_DIV4_CLKGATE : If set to 1, pll_sys_main_120m_clk is off (power savings). 0: pll_sys_main_120m_clk is enabled.
bits : 6 - 6 (1 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Analog debug bit.
bits : 11 - 11 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : Enable the clock output.
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
PLL_480_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 17 - 17 (1 bit)
access : read-write
PFD0_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 18 - 18 (1 bit)
access : read-write
PFD1_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 19 - 19 (1 bit)
access : read-write
PFD2_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 20 - 20 (1 bit)
access : read-write
PFD3_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 21 - 21 (1 bit)
access : read-write
PFD4_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 22 - 22 (1 bit)
access : read-write
PFD5_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 23 - 23 (1 bit)
access : read-write
PFD6_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 24 - 24 (1 bit)
access : read-write
PFD7_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 25 - 25 (1 bit)
access : read-write
PFD0_DIV2_CLKGATE : If set to 1, pll_sys_pfd0_196m_clk is off (power savings). 0: pll_sys_pfd0_196m_clk is enabled.
bits : 26 - 26 (1 bit)
access : read-write
PFD1_DIV2_CLKGATE : If set to 1, pll_sys_pfd1_166m_clk is off (power savings). 0: pll_sys_pfd1_166m_clk is enabled.
bits : 27 - 27 (1 bit)
access : read-write
PFD2_DIV2_CLKGATE : If set to 1, pll_sys_pfd2_135m_clk is off (power savings). 0: pll_sys_pfd2_135m_clk is enabled.
bits : 28 - 28 (1 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 29 - 30 (2 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig 480MHz PLL Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider. 0 - Fout=480MHz; 1 - Fout=528MHz.
bits : 0 - 0 (1 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 1 - 3 (3 bit)
access : read-only
MAIN_DIV1_CLKGATE : If set to 1, pll_sys_main_480m_clk is off (power savings). 0: pll_sys_main_480m_clk is enabled.
bits : 4 - 4 (1 bit)
access : read-write
MAIN_DIV2_CLKGATE : If set to 1, pll_sys_main_240m_clk is off (power savings). 0: pll_sys_main_240m_clk is enabled.
bits : 5 - 5 (1 bit)
access : read-write
MAIN_DIV4_CLKGATE : If set to 1, pll_sys_main_120m_clk is off (power savings). 0: pll_sys_main_120m_clk is enabled.
bits : 6 - 6 (1 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Analog debug bit.
bits : 11 - 11 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : Enable the clock output.
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
PLL_480_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 17 - 17 (1 bit)
access : read-write
PFD0_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 18 - 18 (1 bit)
access : read-write
PFD1_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 19 - 19 (1 bit)
access : read-write
PFD2_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 20 - 20 (1 bit)
access : read-write
PFD3_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 21 - 21 (1 bit)
access : read-write
PFD4_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 22 - 22 (1 bit)
access : read-write
PFD5_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 23 - 23 (1 bit)
access : read-write
PFD6_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 24 - 24 (1 bit)
access : read-write
PFD7_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 25 - 25 (1 bit)
access : read-write
PFD0_DIV2_CLKGATE : If set to 1, pll_sys_pfd0_196m_clk is off (power savings). 0: pll_sys_pfd0_196m_clk is enabled.
bits : 26 - 26 (1 bit)
access : read-write
PFD1_DIV2_CLKGATE : If set to 1, pll_sys_pfd1_166m_clk is off (power savings). 0: pll_sys_pfd1_166m_clk is enabled.
bits : 27 - 27 (1 bit)
access : read-write
PFD2_DIV2_CLKGATE : If set to 1, pll_sys_pfd2_135m_clk is off (power savings). 0: pll_sys_pfd2_135m_clk is enabled.
bits : 28 - 28 (1 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 29 - 30 (2 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig 480MHz PLL Control Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider. 0 - Fout=480MHz; 1 - Fout=528MHz.
bits : 0 - 0 (1 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 1 - 3 (3 bit)
access : read-only
MAIN_DIV1_CLKGATE : If set to 1, pll_sys_main_480m_clk is off (power savings). 0: pll_sys_main_480m_clk is enabled.
bits : 4 - 4 (1 bit)
access : read-write
MAIN_DIV2_CLKGATE : If set to 1, pll_sys_main_240m_clk is off (power savings). 0: pll_sys_main_240m_clk is enabled.
bits : 5 - 5 (1 bit)
access : read-write
MAIN_DIV4_CLKGATE : If set to 1, pll_sys_main_120m_clk is off (power savings). 0: pll_sys_main_120m_clk is enabled.
bits : 6 - 6 (1 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Analog debug bit.
bits : 11 - 11 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : Enable the clock output.
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
PLL_480_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 17 - 17 (1 bit)
access : read-write
PFD0_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 18 - 18 (1 bit)
access : read-write
PFD1_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 19 - 19 (1 bit)
access : read-write
PFD2_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 20 - 20 (1 bit)
access : read-write
PFD3_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 21 - 21 (1 bit)
access : read-write
PFD4_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 22 - 22 (1 bit)
access : read-write
PFD5_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 23 - 23 (1 bit)
access : read-write
PFD6_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 24 - 24 (1 bit)
access : read-write
PFD7_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 25 - 25 (1 bit)
access : read-write
PFD0_DIV2_CLKGATE : If set to 1, pll_sys_pfd0_196m_clk is off (power savings). 0: pll_sys_pfd0_196m_clk is enabled.
bits : 26 - 26 (1 bit)
access : read-write
PFD1_DIV2_CLKGATE : If set to 1, pll_sys_pfd1_166m_clk is off (power savings). 0: pll_sys_pfd1_166m_clk is enabled.
bits : 27 - 27 (1 bit)
access : read-write
PFD2_DIV2_CLKGATE : If set to 1, pll_sys_pfd2_135m_clk is off (power savings). 0: pll_sys_pfd2_135m_clk is enabled.
bits : 28 - 28 (1 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 29 - 30 (2 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
480MHz Clock Phase Fractional Divider Control Register A
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PFD0_FRAC : This field controls the fractional divide value
bits : 0 - 5 (6 bit)
access : read-write
PFD0_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 6 - 6 (1 bit)
access : read-only
PFD0_DIV1_CLKGATE : If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)
bits : 7 - 7 (1 bit)
access : read-write
PFD1_FRAC : This field controls the fractional divide value
bits : 8 - 13 (6 bit)
access : read-write
PFD1_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 14 - 14 (1 bit)
access : read-only
PFD1_DIV1_CLKGATE : IO Clock Gate
bits : 15 - 15 (1 bit)
access : read-write
PFD2_FRAC : This field controls the fractional divide value
bits : 16 - 21 (6 bit)
access : read-write
PFD2_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 22 - 22 (1 bit)
access : read-only
PFD2_DIV1_CLKGATE : IO Clock Gate
bits : 23 - 23 (1 bit)
access : read-write
PFD3_FRAC : This field controls the fractional divide value
bits : 24 - 29 (6 bit)
access : read-write
PFD3_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 30 - 30 (1 bit)
access : read-only
PFD3_DIV1_CLKGATE : IO Clock Gate
bits : 31 - 31 (1 bit)
access : read-write
480MHz Clock Phase Fractional Divider Control Register A
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PFD0_FRAC : This field controls the fractional divide value
bits : 0 - 5 (6 bit)
access : read-write
PFD0_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 6 - 6 (1 bit)
access : read-only
PFD0_DIV1_CLKGATE : If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)
bits : 7 - 7 (1 bit)
access : read-write
PFD1_FRAC : This field controls the fractional divide value
bits : 8 - 13 (6 bit)
access : read-write
PFD1_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 14 - 14 (1 bit)
access : read-only
PFD1_DIV1_CLKGATE : IO Clock Gate
bits : 15 - 15 (1 bit)
access : read-write
PFD2_FRAC : This field controls the fractional divide value
bits : 16 - 21 (6 bit)
access : read-write
PFD2_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 22 - 22 (1 bit)
access : read-only
PFD2_DIV1_CLKGATE : IO Clock Gate
bits : 23 - 23 (1 bit)
access : read-write
PFD3_FRAC : This field controls the fractional divide value
bits : 24 - 29 (6 bit)
access : read-write
PFD3_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 30 - 30 (1 bit)
access : read-only
PFD3_DIV1_CLKGATE : IO Clock Gate
bits : 31 - 31 (1 bit)
access : read-write
480MHz Clock Phase Fractional Divider Control Register A
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PFD0_FRAC : This field controls the fractional divide value
bits : 0 - 5 (6 bit)
access : read-write
PFD0_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 6 - 6 (1 bit)
access : read-only
PFD0_DIV1_CLKGATE : If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)
bits : 7 - 7 (1 bit)
access : read-write
PFD1_FRAC : This field controls the fractional divide value
bits : 8 - 13 (6 bit)
access : read-write
PFD1_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 14 - 14 (1 bit)
access : read-only
PFD1_DIV1_CLKGATE : IO Clock Gate
bits : 15 - 15 (1 bit)
access : read-write
PFD2_FRAC : This field controls the fractional divide value
bits : 16 - 21 (6 bit)
access : read-write
PFD2_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 22 - 22 (1 bit)
access : read-only
PFD2_DIV1_CLKGATE : IO Clock Gate
bits : 23 - 23 (1 bit)
access : read-write
PFD3_FRAC : This field controls the fractional divide value
bits : 24 - 29 (6 bit)
access : read-write
PFD3_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 30 - 30 (1 bit)
access : read-only
PFD3_DIV1_CLKGATE : IO Clock Gate
bits : 31 - 31 (1 bit)
access : read-write
480MHz Clock Phase Fractional Divider Control Register A
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PFD0_FRAC : This field controls the fractional divide value
bits : 0 - 5 (6 bit)
access : read-write
PFD0_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 6 - 6 (1 bit)
access : read-only
PFD0_DIV1_CLKGATE : If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)
bits : 7 - 7 (1 bit)
access : read-write
PFD1_FRAC : This field controls the fractional divide value
bits : 8 - 13 (6 bit)
access : read-write
PFD1_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 14 - 14 (1 bit)
access : read-only
PFD1_DIV1_CLKGATE : IO Clock Gate
bits : 15 - 15 (1 bit)
access : read-write
PFD2_FRAC : This field controls the fractional divide value
bits : 16 - 21 (6 bit)
access : read-write
PFD2_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 22 - 22 (1 bit)
access : read-only
PFD2_DIV1_CLKGATE : IO Clock Gate
bits : 23 - 23 (1 bit)
access : read-write
PFD3_FRAC : This field controls the fractional divide value
bits : 24 - 29 (6 bit)
access : read-write
PFD3_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 30 - 30 (1 bit)
access : read-only
PFD3_DIV1_CLKGATE : IO Clock Gate
bits : 31 - 31 (1 bit)
access : read-write
480MHz Clock Phase Fractional Divider Control Register B
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PFD4_FRAC : This field controls the fractional divide value
bits : 0 - 5 (6 bit)
access : read-write
PFD4_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 6 - 6 (1 bit)
access : read-only
PFD4_DIV1_CLKGATE : If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)
bits : 7 - 7 (1 bit)
access : read-write
PFD5_FRAC : This field controls the fractional divide value
bits : 8 - 13 (6 bit)
access : read-write
PFD5_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 14 - 14 (1 bit)
access : read-only
PFD5_DIV1_CLKGATE : IO Clock Gate
bits : 15 - 15 (1 bit)
access : read-write
PFD6_FRAC : This field controls the fractional divide value
bits : 16 - 21 (6 bit)
access : read-write
PFD6_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 22 - 22 (1 bit)
access : read-only
PFD6_DIV1_CLKGATE : IO Clock Gate
bits : 23 - 23 (1 bit)
access : read-write
PFD7_FRAC : This field controls the fractional divide value
bits : 24 - 29 (6 bit)
access : read-write
PFD7_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 30 - 30 (1 bit)
access : read-only
PFD7_DIV1_CLKGATE : IO Clock Gate
bits : 31 - 31 (1 bit)
access : read-write
480MHz Clock Phase Fractional Divider Control Register B
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PFD4_FRAC : This field controls the fractional divide value
bits : 0 - 5 (6 bit)
access : read-write
PFD4_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 6 - 6 (1 bit)
access : read-only
PFD4_DIV1_CLKGATE : If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)
bits : 7 - 7 (1 bit)
access : read-write
PFD5_FRAC : This field controls the fractional divide value
bits : 8 - 13 (6 bit)
access : read-write
PFD5_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 14 - 14 (1 bit)
access : read-only
PFD5_DIV1_CLKGATE : IO Clock Gate
bits : 15 - 15 (1 bit)
access : read-write
PFD6_FRAC : This field controls the fractional divide value
bits : 16 - 21 (6 bit)
access : read-write
PFD6_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 22 - 22 (1 bit)
access : read-only
PFD6_DIV1_CLKGATE : IO Clock Gate
bits : 23 - 23 (1 bit)
access : read-write
PFD7_FRAC : This field controls the fractional divide value
bits : 24 - 29 (6 bit)
access : read-write
PFD7_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 30 - 30 (1 bit)
access : read-only
PFD7_DIV1_CLKGATE : IO Clock Gate
bits : 31 - 31 (1 bit)
access : read-write
480MHz Clock Phase Fractional Divider Control Register B
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PFD4_FRAC : This field controls the fractional divide value
bits : 0 - 5 (6 bit)
access : read-write
PFD4_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 6 - 6 (1 bit)
access : read-only
PFD4_DIV1_CLKGATE : If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)
bits : 7 - 7 (1 bit)
access : read-write
PFD5_FRAC : This field controls the fractional divide value
bits : 8 - 13 (6 bit)
access : read-write
PFD5_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 14 - 14 (1 bit)
access : read-only
PFD5_DIV1_CLKGATE : IO Clock Gate
bits : 15 - 15 (1 bit)
access : read-write
PFD6_FRAC : This field controls the fractional divide value
bits : 16 - 21 (6 bit)
access : read-write
PFD6_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 22 - 22 (1 bit)
access : read-only
PFD6_DIV1_CLKGATE : IO Clock Gate
bits : 23 - 23 (1 bit)
access : read-write
PFD7_FRAC : This field controls the fractional divide value
bits : 24 - 29 (6 bit)
access : read-write
PFD7_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 30 - 30 (1 bit)
access : read-only
PFD7_DIV1_CLKGATE : IO Clock Gate
bits : 31 - 31 (1 bit)
access : read-write
480MHz Clock Phase Fractional Divider Control Register B
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PFD4_FRAC : This field controls the fractional divide value
bits : 0 - 5 (6 bit)
access : read-write
PFD4_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 6 - 6 (1 bit)
access : read-only
PFD4_DIV1_CLKGATE : If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)
bits : 7 - 7 (1 bit)
access : read-write
PFD5_FRAC : This field controls the fractional divide value
bits : 8 - 13 (6 bit)
access : read-write
PFD5_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 14 - 14 (1 bit)
access : read-only
PFD5_DIV1_CLKGATE : IO Clock Gate
bits : 15 - 15 (1 bit)
access : read-write
PFD6_FRAC : This field controls the fractional divide value
bits : 16 - 21 (6 bit)
access : read-write
PFD6_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 22 - 22 (1 bit)
access : read-only
PFD6_DIV1_CLKGATE : IO Clock Gate
bits : 23 - 23 (1 bit)
access : read-write
PFD7_FRAC : This field controls the fractional divide value
bits : 24 - 29 (6 bit)
access : read-write
PFD7_STABLE : This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
bits : 30 - 30 (1 bit)
access : read-only
PFD7_DIV1_CLKGATE : IO Clock Gate
bits : 31 - 31 (1 bit)
access : read-write
Anadig ARM PLL control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider
bits : 0 - 6 (7 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Analog debug bit.
bits : 11 - 11 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : Enable the clock output.
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
LVDS_SEL : no description available
bits : 17 - 17 (1 bit)
access : read-write
LVDS_24MHZ_SEL : no description available
bits : 18 - 18 (1 bit)
access : read-write
PLL_SEL : no description available
bits : 19 - 19 (1 bit)
access : read-write
PLL_ARM_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 20 - 20 (1 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 21 - 30 (10 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig ENET PLL Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 0 - 0 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 1 - 1 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 2 - 2 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 3 - 3 (1 bit)
access : read-write
HOLD_RING_OFF : Status of ana_irq2 input from analog block.
bits : 4 - 4 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 5 - 5 (1 bit)
access : read-write
ENABLE_CLK_25MHZ : Enables the ethernet 25MHz clock output.
bits : 6 - 6 (1 bit)
access : read-write
ENABLE_CLK_40MHZ : Enables the ethernet 40MHz clock output.
bits : 7 - 7 (1 bit)
access : read-write
ENABLE_CLK_50MHZ : Enables the ethernet 50MHz clock output.
bits : 8 - 8 (1 bit)
access : read-write
ENABLE_CLK_100MHZ : Enables the ethernet 100MHz clock output.
bits : 9 - 9 (1 bit)
access : read-write
ENABLE_CLK_125MHZ : Enables the ethernet 125MHz clock output.
bits : 10 - 10 (1 bit)
access : read-write
ENABLE_CLK_250MHZ : Enables the ethernet 250MHz clock output.
bits : 11 - 11 (1 bit)
access : read-write
ENABLE_CLK_500MHZ : Enables the ethernet 500MHz clock output.
bits : 12 - 12 (1 bit)
access : read-write
PLL_ENET_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 19 - 30 (12 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig ENET PLL Control Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 0 - 0 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 1 - 1 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 2 - 2 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 3 - 3 (1 bit)
access : read-write
HOLD_RING_OFF : Status of ana_irq2 input from analog block.
bits : 4 - 4 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 5 - 5 (1 bit)
access : read-write
ENABLE_CLK_25MHZ : Enables the ethernet 25MHz clock output.
bits : 6 - 6 (1 bit)
access : read-write
ENABLE_CLK_40MHZ : Enables the ethernet 40MHz clock output.
bits : 7 - 7 (1 bit)
access : read-write
ENABLE_CLK_50MHZ : Enables the ethernet 50MHz clock output.
bits : 8 - 8 (1 bit)
access : read-write
ENABLE_CLK_100MHZ : Enables the ethernet 100MHz clock output.
bits : 9 - 9 (1 bit)
access : read-write
ENABLE_CLK_125MHZ : Enables the ethernet 125MHz clock output.
bits : 10 - 10 (1 bit)
access : read-write
ENABLE_CLK_250MHZ : Enables the ethernet 250MHz clock output.
bits : 11 - 11 (1 bit)
access : read-write
ENABLE_CLK_500MHZ : Enables the ethernet 500MHz clock output.
bits : 12 - 12 (1 bit)
access : read-write
PLL_ENET_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 19 - 30 (12 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig ENET PLL Control Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 0 - 0 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 1 - 1 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 2 - 2 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 3 - 3 (1 bit)
access : read-write
HOLD_RING_OFF : Status of ana_irq2 input from analog block.
bits : 4 - 4 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 5 - 5 (1 bit)
access : read-write
ENABLE_CLK_25MHZ : Enables the ethernet 25MHz clock output.
bits : 6 - 6 (1 bit)
access : read-write
ENABLE_CLK_40MHZ : Enables the ethernet 40MHz clock output.
bits : 7 - 7 (1 bit)
access : read-write
ENABLE_CLK_50MHZ : Enables the ethernet 50MHz clock output.
bits : 8 - 8 (1 bit)
access : read-write
ENABLE_CLK_100MHZ : Enables the ethernet 100MHz clock output.
bits : 9 - 9 (1 bit)
access : read-write
ENABLE_CLK_125MHZ : Enables the ethernet 125MHz clock output.
bits : 10 - 10 (1 bit)
access : read-write
ENABLE_CLK_250MHZ : Enables the ethernet 250MHz clock output.
bits : 11 - 11 (1 bit)
access : read-write
ENABLE_CLK_500MHZ : Enables the ethernet 500MHz clock output.
bits : 12 - 12 (1 bit)
access : read-write
PLL_ENET_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 19 - 30 (12 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig ENET PLL Control Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 0 - 0 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 1 - 1 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 2 - 2 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 3 - 3 (1 bit)
access : read-write
HOLD_RING_OFF : Status of ana_irq2 input from analog block.
bits : 4 - 4 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 5 - 5 (1 bit)
access : read-write
ENABLE_CLK_25MHZ : Enables the ethernet 25MHz clock output.
bits : 6 - 6 (1 bit)
access : read-write
ENABLE_CLK_40MHZ : Enables the ethernet 40MHz clock output.
bits : 7 - 7 (1 bit)
access : read-write
ENABLE_CLK_50MHZ : Enables the ethernet 50MHz clock output.
bits : 8 - 8 (1 bit)
access : read-write
ENABLE_CLK_100MHZ : Enables the ethernet 100MHz clock output.
bits : 9 - 9 (1 bit)
access : read-write
ENABLE_CLK_125MHZ : Enables the ethernet 125MHz clock output.
bits : 10 - 10 (1 bit)
access : read-write
ENABLE_CLK_250MHZ : Enables the ethernet 250MHz clock output.
bits : 11 - 11 (1 bit)
access : read-write
ENABLE_CLK_500MHZ : Enables the ethernet 500MHz clock output.
bits : 12 - 12 (1 bit)
access : read-write
PLL_ENET_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 19 - 30 (12 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig Audio PLL control Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider. Valid range for DIV_SELECT divider value: 27-54 decimal.
bits : 0 - 6 (7 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Status of ana_irq2 input from analog block.
bits : 11 - 11 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : no description available
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
TEST_DIV_SELECT : Control bits for the divider for the PLL clk and lvds outputs: 0x0=div-by-4(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-1
bits : 19 - 20 (2 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 21 - 21 (1 bit)
access : read-only
POST_DIV_SEL : Post-divider for audio PLL: 0x0=div-by-1(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-4
bits : 22 - 23 (2 bit)
access : read-write
PLL_AUDIO_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 24 - 24 (1 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 25 - 30 (6 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig Audio PLL control Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider. Valid range for DIV_SELECT divider value: 27-54 decimal.
bits : 0 - 6 (7 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Status of ana_irq2 input from analog block.
bits : 11 - 11 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : no description available
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
TEST_DIV_SELECT : Control bits for the divider for the PLL clk and lvds outputs: 0x0=div-by-4(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-1
bits : 19 - 20 (2 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 21 - 21 (1 bit)
access : read-only
POST_DIV_SEL : Post-divider for audio PLL: 0x0=div-by-1(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-4
bits : 22 - 23 (2 bit)
access : read-write
PLL_AUDIO_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 24 - 24 (1 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 25 - 30 (6 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig Audio PLL control Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider. Valid range for DIV_SELECT divider value: 27-54 decimal.
bits : 0 - 6 (7 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Status of ana_irq2 input from analog block.
bits : 11 - 11 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : no description available
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
TEST_DIV_SELECT : Control bits for the divider for the PLL clk and lvds outputs: 0x0=div-by-4(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-1
bits : 19 - 20 (2 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 21 - 21 (1 bit)
access : read-only
POST_DIV_SEL : Post-divider for audio PLL: 0x0=div-by-1(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-4
bits : 22 - 23 (2 bit)
access : read-write
PLL_AUDIO_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 24 - 24 (1 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 25 - 30 (6 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig Audio PLL control Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider. Valid range for DIV_SELECT divider value: 27-54 decimal.
bits : 0 - 6 (7 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Status of ana_irq2 input from analog block.
bits : 11 - 11 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : no description available
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
TEST_DIV_SELECT : Control bits for the divider for the PLL clk and lvds outputs: 0x0=div-by-4(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-1
bits : 19 - 20 (2 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 21 - 21 (1 bit)
access : read-only
POST_DIV_SEL : Post-divider for audio PLL: 0x0=div-by-1(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-4
bits : 22 - 23 (2 bit)
access : read-write
PLL_AUDIO_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 24 - 24 (1 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 25 - 30 (6 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Audio PLL Spread Spectrum Register.
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STEP : The max frequency change = stop/B*24MHz.
bits : 0 - 14 (15 bit)
access : read-write
ENABLE : This bit enables the spread spectrum modulation.
bits : 15 - 15 (1 bit)
access : read-write
STOP : Frequency change = step/B*24MHz.
bits : 16 - 31 (16 bit)
access : read-write
Numerator of Audio PLL Fractional Loop Divider Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A : 30 bit numerator of fractional loop divider.
bits : 0 - 29 (30 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 30 - 31 (2 bit)
access : read-only
Anadig ARM PLL control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider
bits : 0 - 6 (7 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Analog debug bit.
bits : 11 - 11 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : Enable the clock output.
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
LVDS_SEL : no description available
bits : 17 - 17 (1 bit)
access : read-write
LVDS_24MHZ_SEL : no description available
bits : 18 - 18 (1 bit)
access : read-write
PLL_SEL : no description available
bits : 19 - 19 (1 bit)
access : read-write
PLL_ARM_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 20 - 20 (1 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 21 - 30 (10 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Denominator of Audio PLL Fractional Loop Divider Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B : 30 bit Denominator of fractional loop divider.
bits : 0 - 29 (30 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 30 - 31 (2 bit)
access : read-only
Anadig Video PLL control Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider. Valid range for DIV_SELECT divider value: 27-54 decimal.
bits : 0 - 6 (7 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Status of ana_irq2 input from analog block.
bits : 11 - 11 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : no description available
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
TEST_DIV_SELECT : Control bits for the divider for the PLL clk and lvds outputs: 0x0=div-by-4(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-1
bits : 19 - 20 (2 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 21 - 21 (1 bit)
access : read-only
POST_DIV_SEL : Post-divider for video PLL: 0x0=div-by-1(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-4
bits : 22 - 23 (2 bit)
access : read-write
PLL_VIDEO_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 24 - 24 (1 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 25 - 30 (6 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig Video PLL control Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider. Valid range for DIV_SELECT divider value: 27-54 decimal.
bits : 0 - 6 (7 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Status of ana_irq2 input from analog block.
bits : 11 - 11 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : no description available
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
TEST_DIV_SELECT : Control bits for the divider for the PLL clk and lvds outputs: 0x0=div-by-4(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-1
bits : 19 - 20 (2 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 21 - 21 (1 bit)
access : read-only
POST_DIV_SEL : Post-divider for video PLL: 0x0=div-by-1(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-4
bits : 22 - 23 (2 bit)
access : read-write
PLL_VIDEO_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 24 - 24 (1 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 25 - 30 (6 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig Video PLL control Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider. Valid range for DIV_SELECT divider value: 27-54 decimal.
bits : 0 - 6 (7 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Status of ana_irq2 input from analog block.
bits : 11 - 11 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : no description available
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
TEST_DIV_SELECT : Control bits for the divider for the PLL clk and lvds outputs: 0x0=div-by-4(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-1
bits : 19 - 20 (2 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 21 - 21 (1 bit)
access : read-only
POST_DIV_SEL : Post-divider for video PLL: 0x0=div-by-1(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-4
bits : 22 - 23 (2 bit)
access : read-write
PLL_VIDEO_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 24 - 24 (1 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 25 - 30 (6 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Anadig Video PLL control Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : This field controls the pll loop divider. Valid range for DIV_SELECT divider value: 27-54 decimal.
bits : 0 - 6 (7 bit)
access : read-write
HALF_LF : Reduces the frequency of the loop filter 2x.
bits : 7 - 7 (1 bit)
access : read-write
DOUBLE_LF : Increases the frequency of the loop filter 2x.
bits : 8 - 8 (1 bit)
access : read-write
HALF_CP : Reduces the charge pump gain 2x.
bits : 9 - 9 (1 bit)
access : read-write
DOUBLE_CP : Increases the charge pump gain 2x.
bits : 10 - 10 (1 bit)
access : read-write
HOLD_RING_OFF : Status of ana_irq2 input from analog block.
bits : 11 - 11 (1 bit)
access : read-write
POWERDOWN : Powers down the PLL.
bits : 12 - 12 (1 bit)
access : read-write
ENABLE_CLK : no description available
bits : 13 - 13 (1 bit)
access : read-write
BYPASS_CLK_SRC : Determines the bypass source.
bits : 14 - 15 (2 bit)
access : read-write
BYPASS : Bypass the pll.
bits : 16 - 16 (1 bit)
access : read-write
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
TEST_DIV_SELECT : Control bits for the divider for the PLL clk and lvds outputs: 0x0=div-by-4(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-1
bits : 19 - 20 (2 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 21 - 21 (1 bit)
access : read-only
POST_DIV_SEL : Post-divider for video PLL: 0x0=div-by-1(default), 0x1=div-by-2, 0x2=div-by-1, 0x3=div-by-4
bits : 22 - 23 (2 bit)
access : read-write
PLL_VIDEO_OVERRIDE : The OVERRIDE bit allows the clock control module to automatically override portions of the register
bits : 24 - 24 (1 bit)
access : read-write
RSVD1 : Always set to zero (0).
bits : 25 - 30 (6 bit)
access : read-only
LOCK : 1 - PLL is currently locked; 0 - PLL is not currently locked.
bits : 31 - 31 (1 bit)
access : read-only
Video PLL Spread Spectrum Register.
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STEP : The max frequency change = stop/B*24MHz.
bits : 0 - 14 (15 bit)
access : read-write
ENABLE : This bit enables the spread spectrum modulation.
bits : 15 - 15 (1 bit)
access : read-write
STOP : Frequency change = step/B*24MHz.
bits : 16 - 31 (16 bit)
access : read-write
Numerator of Video PLL Fractional Loop Divider Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A : 30 bit numerator of fractional loop divider.
bits : 0 - 29 (30 bit)
access : read-write
RSVD0 : Always set to zero (0).
bits : 30 - 31 (2 bit)
access : read-only
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