Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1C0 byte (0x0)
mem_usage : registers
protection : not protected
Basic Low power control register of A7 platform
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPM0 : CORE0 Setting the low power mode that system will enter on next assertion of dsm_request signal.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : LPM0_0
Remain in RUN mode
0x1 : LPM0_1
Transfer to WAIT mode
0x2 : LPM0_2
Transfer to STOP mode
End of enumeration elements list.
LPM1 : CORE1 Setting the low power mode that system will enter on next assertion of dsm_request signal.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : LPM1_0
Remain in RUN mode
0x1 : LPM1_1
Transfer to WAIT mode
0x2 : LPM1_2
Transfer to STOP mode
End of enumeration elements list.
CPU_CLK_ON_LPM : Define if A7 clocks will be disabled on wait/stop mode.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : CPU_CLK_ON_LPM_0
A7 clock disabled on wait/stop mode
0x1 : CPU_CLK_ON_LPM_1
A7 clock enabled on wait/stop mode
End of enumeration elements list.
MASK_CORE0_WFI : CORE0 Wait For Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : MASK_CORE0_WFI_0
WFI for CORE0 is not masked
0x1 : MASK_CORE0_WFI_1
WFI for CORE0 is masked
End of enumeration elements list.
MASK_CORE1_WFI : CORE1 Wait For Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : MASK_CORE1_WFI_0
WFI for CORE1 is not masked
0x1 : MASK_CORE1_WFI_1
WFI for CORE1 is masked
End of enumeration elements list.
MASK_L2CC_WFI : L2 cache controller Wait For Interrupt Mask Register
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : MASK_L2CC_WFI_0
WFI for L2 cache controller is not masked
0x1 : MASK_L2CC_WFI_1
WFI for L2 cache controller is masked
End of enumeration elements list.
IRQ_SRC_C0 : LPCR_A7_BSC[IRQ_SRC_CO], LPCR_A7_BSC[IRQ_SRC_C1], and LPCR_A7_BSC[IRQ_SRC_A7_WUP] work together to decide the wake up source for A7 LPM and core0/core1 power
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : IRQ_SRC_C0_0
core0 wakeup source from external INT[127:0], masked by IMR0 refer to "Power up process for A7 platform" for more specific information
0x1 : IRQ_SRC_C0_1
core0 wakeup source from GIC(nFIQ[0]/nIRQ[0] ), SCU should not be power down during low power mode when this bit is set to 1'b1
End of enumeration elements list.
IRQ_SRC_C1 : LPCR_A7_BSC[IRQ_SRC_CO], LPCR_A7_BSC[IRQ_SRC_C1], and LPCR_A7_BSC[IRQ_SRC_A7_WUP] work together to decide the wake up source for A7 LPM and core0/core1 power
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : IRQ_SRC_C1_0
core1 wakeup source from external INT[127:0], masked by IMR1 refer to "Power up process for A7 platform" for more specific information
0x1 : IRQ_SRC_C1_1
core1 wakeup source from GIC(nFIQ[1]/nIRQ[1] ), SCU should not be power down during low power mode when this bit is set to 1'b1
End of enumeration elements list.
IRQ_SRC_A7_WUP : LPCR_A7_BSC[IRQ_SRC_CO], LPCR_A7_BSC[IRQ_SRC_C1], and LPCR_A7_BSC[IRQ_SRC_A7_WUP] work together to decide the wake up source for A7 LPM and core0/core1 power
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : IRQ_SRC_A7_WUP_0
LPM wakeup source be "OR" result of LPCR_A7_BSC[IRQ_SRC_C0]/LPCR_A7_BSC[IRQ_SRC_C1] setting
0x1 : IRQ_SRC_A7_WUP_1
LPM wakeup source from external INT[127:0], masked by IMR0
End of enumeration elements list.
MASK_DSM_TRIGGER : DSM Trigger Mask
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : MASK_DSM_TRIGGER_0
DSM trigger of A7 platform will not be masked
0x1 : MASK_DSM_TRIGGER_1
DSM trigger of A7 platform will be masked
End of enumeration elements list.
PU PGC software down trigger
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MIPI_PHY_SW_PDN_REQ : Software power down trigger for MIPI_PHY
bits : 0 - 0 (1 bit)
access : read-write
PCIE_PHY_SW_PDN_REQ : Software power down trigger for PCIE_PHY
bits : 1 - 1 (1 bit)
access : read-write
USB_OTG1_PHY_SW_PDN_REQ : Software power down trigger for USB_OTG1_PHY
bits : 2 - 2 (1 bit)
access : read-write
USB_OTG2_PHY_SW_PDN_REQ : Software power down trigger for USB_OTG2_PHY
bits : 3 - 3 (1 bit)
access : read-write
USB_HSIC_PHY_SW_PDN_REQ : Software power down trigger for USB_HSIC_PHY
bits : 4 - 4 (1 bit)
access : read-write
CPU PGC software up trigger status1
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_PUP_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
CORE1_A7_PUP_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
SCU_A7_PUP_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
System low power control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYPASS_PMIC_READY : By asserting this bit GPC will bypass waiting for PMIC_READY signal when coming out of DSM
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : BYPASS_PMIC_READY_0
Don't bypass the PMIC_READY signal - GPC will wait for its assertion during exit of low power mode if standby voltage was enabled
0x1 : BYPASS_PMIC_READY_1
Bypass the PMIC_READY signal - GPC will wait for its assertion during exit of low power mode if standby voltage was enabled
End of enumeration elements list.
SBYOS : Standby clock oscillator bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SBYOS_0
On chip oscillator will not be powered down, after next entrance to DSM.
0x1 : SBYOS_1
On chip oscillator will be powered down, after next entrance to DSM. When returning from DSM, external oscillator will be enabled again, on chip oscillator will return to oscillator mode , and after oscnt count GPC will continue with the exit from DSM process.
End of enumeration elements list.
VSTBY : Voltage standby request bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : VSTBY_0
Voltage will not be changed to standby voltage after next entrance to stop mode. (PMIC_STBY_REQ will remain negated - '0')
0x1 : VSTBY_1
Voltage will be changed to standby voltage after next entrance to stop mode.
End of enumeration elements list.
STBY_COUNT : Standby counter definition
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : STBY_COUNT_0
GPC will wait 4 ckil clock cycles
0x1 : STBY_COUNT_1
GPC will wait 8 ckil clock cycles
0x2 : STBY_COUNT_2
GPC will wait 16 ckil clock cycles
0x3 : STBY_COUNT_3
GPC will wait 32 ckil clock cycles
0x4 : STBY_COUNT_4
GPC will wait 64 ckil clock cycles
0x5 : STBY_COUNT_5
GPC will wait 128 ckil clock cycles
0x6 : STBY_COUNT_6
GPC will wait 256 ckil clock cycles
0x7 : STBY_COUNT_7
GPC will wait 512 ckil clock cycles
End of enumeration elements list.
COSC_PWRDOWN : In run mode, software can manually control powering down of on chip oscillator, i
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : COSC_PWRDOWN_0
On-chip oscillator will not be powered down, i.e. cosc_pwrdown = 0
0x1 : COSC_PWRDOWN_1
On-chip oscillator will be powered down, i.e. cosc_pwrdown = 1
End of enumeration elements list.
COSC_EN : On-chip oscillator enable bit - this bit value is reflected on the output cosc_en
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : COSC_EN_0
Disable on-chip oscillator
0x1 : COSC_EN_1
Enable on-chip oscillator
End of enumeration elements list.
OSCCNT : Oscillator ready counter value
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
0 : OSCCNT_0
count 1 ckil
0xFF : OSCCNT_255
count 256 ckils
End of enumeration elements list.
EN_A7_FASTWUP_WAIT_MODE : Enable A7 fast wake up wait mode, relevant PLLs will not be closed in this mode.
bits : 16 - 16 (1 bit)
access : read-write
EN_A7_FASTWUP_STOP_MODE : Enable A7 fast wake up stop mode, relevant PLLs will not be closed in this mode.
bits : 17 - 17 (1 bit)
access : read-write
EN_M4_FASTWUP_WAIT_MODE : Enable M4 fast wake up wait mode, relevant PLLs will not be closed in this mode.
bits : 18 - 18 (1 bit)
access : read-write
EN_M4_FASTWUP_STOP_MODE : Enable M4 fast wake up stop mode, relevant PLLs will not be closed in this mode.
bits : 19 - 19 (1 bit)
access : read-write
DISABLE_A7_IS_DSM : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLE_A7_IS_DSM_0
Enable a7 isolation signal in DSM
0x1 : DISABLE_A7_IS_DSM_1
Disable a7 isolation signal in DSM
End of enumeration elements list.
REG_BYPASS_COUNT : Counter for REG_BYPASS signal assertion after standby voltage request by PMIC_STBY_REQ.
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0 : REG_BYPASS_COUNT_0
no delay
0x1 : REG_BYPASS_COUNT_1
1 CKIL clock period delay
0x3F : REG_BYPASS_COUNT_63
63 CKIL clock period delay
End of enumeration elements list.
RBC_EN : Enable for REG_BYPASS_COUNTER
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RBC_EN_0
REG_BYPASS_COUNTER disabled
0x1 : RBC_EN_1
REG_BYPASS_COUNTER enabled
End of enumeration elements list.
EN_DSM : DSM enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : EN_DSM_0
DSM disabled
0x1 : EN_DSM_1
DSM enabled
End of enumeration elements list.
Slot configure register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_PDN_SLOT_CONTROL : CORE0 A7 Power-down slot control
bits : 0 - 0 (1 bit)
access : read-write
CORE0_A7_PUP_SLOT_CONTROL : CORE0 A7 Power-up slot control
bits : 1 - 1 (1 bit)
access : read-write
CORE1_A7_PDN_SLOT_CONTROL : CORE1 A7 Power-down slot control
bits : 2 - 2 (1 bit)
access : read-write
CORE1_A7_PUP_SLOT_CONTROL : CORE1 A7 Power-up slot control
bits : 3 - 3 (1 bit)
access : read-write
SCU_PDN_SLOT_CONTROL : SCU Power-down slot control
bits : 4 - 4 (1 bit)
access : read-write
SCU_PUP_SLOT_CONTROL : SCU Power-up slot control
bits : 5 - 5 (1 bit)
access : read-write
FASTMEGA_PDN_SLOT_CONTROL : FASTMEGA Power-down slot control
bits : 6 - 6 (1 bit)
access : read-write
FASTMEGA_PUP_SLOT_CONTROL : FASTMEGA Power-up slot control
bits : 7 - 7 (1 bit)
access : read-write
MIPI_PHY_PDN_SLOT_CONTROL : MIPI_PHY Power-down slot control
bits : 8 - 8 (1 bit)
access : read-write
MIPI_PHY_PUP_SLOT_CONTROL : MIPI_PHY Power-up slot control
bits : 9 - 9 (1 bit)
access : read-write
PCIE_PHY_PDN_SLOT_CONTROL : PCIE_PHY Power-down slot control
bits : 10 - 10 (1 bit)
access : read-write
PCIE_PHY_PUP_SLOT_CONTROL : PCIE_PHY Power-up slot control
bits : 11 - 11 (1 bit)
access : read-write
USB_OTG1_PDN_SLOT_CONTROL : USB_OTG1 Power-down slot control
bits : 12 - 12 (1 bit)
access : read-write
USB_OTG1_PUP_SLOT_CONTROL : USB_OTG1 Power-up slot control
bits : 13 - 13 (1 bit)
access : read-write
USB_OTG2_PDN_SLOT_CONTROL : USB_OTG2 Power-down slot control
bits : 14 - 14 (1 bit)
access : read-write
USB_OTG2_PUP_SLOT_CONTROL : USB_OTG2 Power-up slot control
bits : 15 - 15 (1 bit)
access : read-write
USB_HSIC_PDN_SLOT_CONTROL : USB_HSIC Power-down slot control
bits : 16 - 16 (1 bit)
access : read-write
USB_HSIC_PUP_SLOT_CONTROL : USB_HSIC Power-up slot control
bits : 17 - 17 (1 bit)
access : read-write
M4_VIRTUAL_PDN_SLOT_CONTROL : M4_VIRTUAL Power-down slot control
bits : 18 - 18 (1 bit)
access : read-write
M4_VIRTUAL_PUP_SLOT_CONTROL : M4_VIRTUAL Power-up slot control
bits : 19 - 19 (1 bit)
access : read-write
CPU PGC software dn trigger status1
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_PDN_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
CORE1_A7_PDN_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
SCU_A7_PDN_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
A7 MIX PDN FLG
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A7_MIX_PDN_FLAG : A7 MIX power-down flag
bits : 0 - 0 (1 bit)
access : read-write
A7 PU PDN FLG
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A7_MIPI_PHY_PGC_PDN_FLG : MIPI_PHY PGC power-down flag
bits : 0 - 0 (1 bit)
access : read-write
A7_PCIE_PHY_PGC_PDN_FLG : PCIE_PHY PGC power-down flag
bits : 1 - 1 (1 bit)
access : read-write
A7_USB_OTG1_PHY_PGC_PDN_FLG : USB_OTG1 PGC power-down flag
bits : 2 - 2 (1 bit)
access : read-write
A7_USB_OTG2_PHY_PGC_PDN_FLG : USB_OTG2 PGC power-down flag
bits : 3 - 3 (1 bit)
access : read-write
A7_USB_HSIC_PHY_PGC_PDN_FLG : USB_HSIC PGC power-down flag
bits : 4 - 4 (1 bit)
access : read-write
M4 MIX PDN FLG
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M4_MIX_PDN_FLAG : M4_MIX power-down flag
bits : 0 - 0 (1 bit)
access : read-write
M4 PU PDN FLG
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M4_MIPI_PHY_PGC_PDN_FLG : MIPI_PHY PGC power-down flag
bits : 0 - 0 (1 bit)
access : read-write
M4_PCIE_PHY_PGC_PDN_FLG : PCIE_PHY PGC power-down flag
bits : 1 - 1 (1 bit)
access : read-write
M4_USB_OTG1_PHY_PGC_PDN_FLG : USB_OTG1 PGC power-down flag
bits : 2 - 2 (1 bit)
access : read-write
M4_USB_OTG2_PHY_PGC_PDN_FLG : USB_OTG2 PGC power-down flag
bits : 3 - 3 (1 bit)
access : read-write
M4_USB_HSIC_PHY_PGC_PDN_FLG : USB_HSIC PGC power-down flag
bits : 4 - 4 (1 bit)
access : read-write
Memory low power control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMLP_CTL_DIS : RAM low-power control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEMLP_CTL_DIS_0
Enable RAM low power control
0x1 : MEMLP_CTL_DIS_1
Disable RAM low power control
End of enumeration elements list.
MEMLP_RET_SEL : Retention select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : MEMLP_RET_SEL_0
retention mode 2
0x1 : MEMLP_RET_SEL_1
retention mode 1
End of enumeration elements list.
ROMLP_PDN_DIS : ROM shut down control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ROMLP_PDN_DIS_0
Enable ROM shut down control(should also enable RAM low power control);
0x1 : ROMLP_PDN_DIS_1
Disable ROM shut down control
End of enumeration elements list.
MEMLP_ENT_CNT : Delay counter to make sure all clock off after pll_dis_req is issued by smc
bits : 8 - 15 (8 bit)
access : read-write
MEM_EXT_CNT : Delay counter to start existing from memory low power
bits : 16 - 23 (8 bit)
access : read-write
MEMLP_RET_PGEN : Delay conter for "retnx" and "pgen"
bits : 24 - 31 (8 bit)
access : read-write
Slot configure register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_PDN_SLOT_CONTROL : CORE0 A7 Power-down slot control
bits : 0 - 0 (1 bit)
access : read-write
CORE0_A7_PUP_SLOT_CONTROL : CORE0 A7 Power-up slot control
bits : 1 - 1 (1 bit)
access : read-write
CORE1_A7_PDN_SLOT_CONTROL : CORE1 A7 Power-down slot control
bits : 2 - 2 (1 bit)
access : read-write
CORE1_A7_PUP_SLOT_CONTROL : CORE1 A7 Power-up slot control
bits : 3 - 3 (1 bit)
access : read-write
SCU_PDN_SLOT_CONTROL : SCU Power-down slot control
bits : 4 - 4 (1 bit)
access : read-write
SCU_PUP_SLOT_CONTROL : SCU Power-up slot control
bits : 5 - 5 (1 bit)
access : read-write
FASTMEGA_PDN_SLOT_CONTROL : FASTMEGA Power-down slot control
bits : 6 - 6 (1 bit)
access : read-write
FASTMEGA_PUP_SLOT_CONTROL : FASTMEGA Power-up slot control
bits : 7 - 7 (1 bit)
access : read-write
MIPI_PHY_PDN_SLOT_CONTROL : MIPI_PHY Power-down slot control
bits : 8 - 8 (1 bit)
access : read-write
MIPI_PHY_PUP_SLOT_CONTROL : MIPI_PHY Power-up slot control
bits : 9 - 9 (1 bit)
access : read-write
PCIE_PHY_PDN_SLOT_CONTROL : PCIE_PHY Power-down slot control
bits : 10 - 10 (1 bit)
access : read-write
PCIE_PHY_PUP_SLOT_CONTROL : PCIE_PHY Power-up slot control
bits : 11 - 11 (1 bit)
access : read-write
USB_OTG1_PDN_SLOT_CONTROL : USB_OTG1 Power-down slot control
bits : 12 - 12 (1 bit)
access : read-write
USB_OTG1_PUP_SLOT_CONTROL : USB_OTG1 Power-up slot control
bits : 13 - 13 (1 bit)
access : read-write
USB_OTG2_PDN_SLOT_CONTROL : USB_OTG2 Power-down slot control
bits : 14 - 14 (1 bit)
access : read-write
USB_OTG2_PUP_SLOT_CONTROL : USB_OTG2 Power-up slot control
bits : 15 - 15 (1 bit)
access : read-write
USB_HSIC_PDN_SLOT_CONTROL : USB_HSIC Power-down slot control
bits : 16 - 16 (1 bit)
access : read-write
USB_HSIC_PUP_SLOT_CONTROL : USB_HSIC Power-up slot control
bits : 17 - 17 (1 bit)
access : read-write
M4_VIRTUAL_PDN_SLOT_CONTROL : M4_VIRTUAL Power-down slot control
bits : 18 - 18 (1 bit)
access : read-write
M4_VIRTUAL_PUP_SLOT_CONTROL : M4_VIRTUAL Power-up slot control
bits : 19 - 19 (1 bit)
access : read-write
PGC acknowledge signal selection of A7 platform
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A7_C0_PGC_PDN_ACK : Select power down acknowledge signal of A7 CORE0 PGC as the power down acknowledge for A7 LPM.
bits : 0 - 0 (1 bit)
access : read-write
A7_C1_PGC_PDN_ACK : Select power down acknowledge signal of A7 CORE1 PGC as the power down acknowledge for A7 LPM.
bits : 1 - 1 (1 bit)
access : read-write
A7_PLAT_PGC_PDN_ACK : Select power down acknowledge signal of A7 PLATFORM PGC as the power down acknowledge for A7 LPM.
bits : 2 - 2 (1 bit)
access : read-write
MF_PGC_PDN_ACK : Select power down acknowledge signal of MIX PGC as the power down acknowledge for A7 LPM.
bits : 3 - 3 (1 bit)
access : read-write
MIPI_PGC_PDN_ACK : Select power down acknowledge signal of MIPI PGC as the power down acknowledge for A7 LPM.
bits : 4 - 4 (1 bit)
access : read-write
PCIE_PGC_PDN_ACK : Select power down acknowledge signal of PCIE PGC as the power down acknowledge for A7 LPM.
bits : 5 - 5 (1 bit)
access : read-write
USB_OTG1_PGC_PDN_ACK : Select power down acknowledge signal of USB_OTG1 PGC as the power down acknowledge for A7 LPM.
bits : 6 - 6 (1 bit)
access : read-write
USB_OTG2_PGC_PDN_ACK : Select power down acknowledge signal of USB_OTG2 PGC as the power down acknowledge for A7 LPM.
bits : 7 - 7 (1 bit)
access : read-write
USB_HSIC_PGC_PDN_ACK : Select power down acknowledge signal of USB_HSIC PGC as the power down acknowledge for A7 LPM.
bits : 8 - 8 (1 bit)
access : read-write
A7_PGC_PDN_ACK : Select power down acknowledge signal of A7 (dummy) PGC as the power down acknowledge for A7 LPM.
bits : 15 - 15 (1 bit)
access : read-write
A7_C0_PGC_PUP_ACK : Select power up acknowledge signal of A7 CORE0 PGC as the power up acknowledge for A7 LPM.
bits : 16 - 16 (1 bit)
access : read-write
A7_C1_PGC_PUP_ACK : Select power up acknowledge signal of A7 CORE1 PGC as the power up acknowledge for A7 LPM.
bits : 17 - 17 (1 bit)
access : read-write
A7_PLAT_PGC_PUP_ACK : Select power up acknowledge signal of A7 PLATFORM PGC as the power up acknowledge for A7 LPM.
bits : 18 - 18 (1 bit)
access : read-write
MF_PGC_PUP_ACK : Select power up acknowledge signal of MF PGC as the power up acknowledge for A7 LPM.
bits : 19 - 19 (1 bit)
access : read-write
MIPI_PGC_PUP_ACK : Select power up acknowledge signal of MIPI PGC as the power up acknowledge for A7 LPM.
bits : 20 - 20 (1 bit)
access : read-write
PCIE_PGC_PUP_ACK : Select power up acknowledge signal of PCIE PGC as the power up acknowledge for A7 LPM.
bits : 21 - 21 (1 bit)
access : read-write
USB_OTG1_PGC_PUP_ACK : Select power up acknowledge signal of USB_OTG1 PGC as the power up acknowledge for A7 LPM.
bits : 22 - 22 (1 bit)
access : read-write
USB_OTG2_PGC_PUP_ACK : Select power up acknowledge signal of USB_OTG2 PGC as the power up acknowledge for A7 LPM.
bits : 23 - 23 (1 bit)
access : read-write
USB_HSIC_PGC_PUP_ACK : Select power up acknowledge signal of USB_HSIC PGC as the power up acknowledge for A7 LPM.
bits : 24 - 24 (1 bit)
access : read-write
A7_PGC_PUP_ACK : Select power up acknowledge signal of A7 (dummy) PGC as the power up acknowledge for A7 LPM.
bits : 31 - 31 (1 bit)
access : read-write
A7 MIX software up trigger status register
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
A7_MIPI_PHY_PGC_PUP_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
A7_PCIE_PHY_PGC_PUP_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
A7_USB_OTG1_PHY_PGC_PUP_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
A7_USB_OTG2_PHY_PGC_PUP_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
A7_USB_HSIC_PHY_PGC_PUP_STATUS : no description available
bits : 4 - 4 (1 bit)
access : read-only
PGC acknowledge signal selection of M4 platform
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M4_VIRTUAL_PGC_PDN_ACK : Select power down acknowledge signal of M4 virtual PGC as the power down acknowledge for M4 LPM
bits : 0 - 0 (1 bit)
access : read-write
MF_PGC_PDN_ACK : Select power down acknowledge signal of MIX PGC as the power down acknowledge for M4 LPM.
bits : 3 - 3 (1 bit)
access : read-write
MIPI_PGC_PDN_ACK : Select power down acknowledge signal of MIPI PGC as the power down acknowledge for M4 LPM.
bits : 4 - 4 (1 bit)
access : read-write
PCIE_PGC_PDN_ACK : Select power down acknowledge signal of PCIE PGC as the power down acknowledge for M4 LPM.
bits : 5 - 5 (1 bit)
access : read-write
USB_OTG1_PGC_PDN_ACK : Select power down acknowledge signal of USB_OTG1 PGC as the power down acknowledge for M4 LPM.
bits : 6 - 6 (1 bit)
access : read-write
USB_OTG2_PGC_PDN_ACK : Select power down acknowledge signal of USB_OTG2 PGC as the power down acknowledge for M4 LPM.
bits : 7 - 7 (1 bit)
access : read-write
USB_HSIC_PGC_PDN_ACK : Select power down acknowledge signal of USB_HSIC PGC as the power down acknowledge for M4 LPM.
bits : 8 - 8 (1 bit)
access : read-write
M4_DUMMY_PGC_PDN_ACK : Select power down acknowledge signal of M4 (dummy) PGC as the power down acknowledge for M4 LPM.
bits : 15 - 15 (1 bit)
access : read-write
M4_VIRTUAL_PGC_PUP_ACK : Select power up acknowledge signal of M4 virtual PGC as the power up acknowledge for M4 LPM
bits : 16 - 16 (1 bit)
access : read-write
MF_PGC_PUP_ACK : Select power up acknowledge signal of MF PGC as the power up acknowledge for M4 LPM.
bits : 19 - 19 (1 bit)
access : read-write
MIPI_PGC_PUP_ACK : Select power up acknowledge signal of MIPI PGC as the power up acknowledge for M4 LPM.
bits : 20 - 20 (1 bit)
access : read-write
PCIE_PGC_PUP_ACK : Select power up acknowledge signal of PCIE PGC as the power up acknowledge for M4 LPM.
bits : 21 - 21 (1 bit)
access : read-write
USB_OTG1_PGC_PUP_ACK : Select power up acknowledge signal of USB_OTG1 PGC as the power up acknowledge for M4 LPM.
bits : 22 - 22 (1 bit)
access : read-write
USB_OTG2_PGC_PUP_ACK : Select power up acknowledge signal of USB_OTG2 PGC as the power up acknowledge for M4 LPM.
bits : 23 - 23 (1 bit)
access : read-write
USB_HSIC_PGC_PUP_ACK : Select power up acknowledge signal of USB_HSIC PGC as the power up acknowledge for M4 LPM.
bits : 24 - 24 (1 bit)
access : read-write
M4_DUMMY_PGC_PUP_ACK : Select power up acknowledge signal of M4 (dummy) PGC as the power up acknowledge for M4 LPM.
bits : 31 - 31 (1 bit)
access : read-write
M4 MIX PGC software up trigger status register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
M4_MIPI_PHY_PGC_PUP_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
M4_PCIE_PHY_PGC_PUP_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
M4_USB_OTG1_PHY_PGC_PUP_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
M4_USB_OTG2_PHY_PGC_PUP_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
M4_USB_HSIC_PHY_PGC_PUP_STATUS : no description available
bits : 4 - 4 (1 bit)
access : read-only
A7 PU software up trigger status register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
A7_MIPI_PHY_PGC_PUP_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
A7_PCIE_PHY_PGC_PUP_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
A7_USB_OTG1_PHY_PGC_PUP_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
A7_USB_OTG2_PHY_PGC_PUP_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
A7_USB_HSIC_PHY_PGC_PUP_STATUS : no description available
bits : 4 - 4 (1 bit)
access : read-only
M4 PU PGC software up trigger status register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
M4_MIPI_PHY_PGC_PUP_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
M4_PCIE_PHY_PGC_PUP_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
M4_USB_OTG1_PHY_PGC_PUP_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
M4_USB_OTG2_PHY_PGC_PUP_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
M4_USB_HSIC_PHY_PGC_PUP_STATUS : no description available
bits : 4 - 4 (1 bit)
access : read-only
GPC Miscellaneous register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M4_SLEEP_HOLD_REQ_B : M4 sleep hold
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : M4_SLEEP_HOLD_REQ_B_0
Hold M4 platform in sleep mode. This bit is a software control bit to M4 platform.
0x1 : M4_SLEEP_HOLD_REQ_B_1
Don't hold M4 platform in sleep mode.
End of enumeration elements list.
GPC_IRQ_MASK : GPC interrupt/event masking
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : GPC_IRQ_MASK_0
Not masked
0x1 : GPC_IRQ_MASK_1
Interrupt / event is masked
End of enumeration elements list.
M4_PDN_REQ_MASK : M4 power-down mask
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : M4_PDN_REQ_MASK_0
M4 power down request to virtual M4 PGC will be masked.
0x1 : M4_PDN_REQ_MASK_1
M4 power down request to virtual M4 PGC will not be masked. Set this bit to 1'b1 when M4 virtual PGC is used.
End of enumeration elements list.
Slot configure register
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_PDN_SLOT_CONTROL : CORE0 A7 Power-down slot control
bits : 0 - 0 (1 bit)
access : read-write
CORE0_A7_PUP_SLOT_CONTROL : CORE0 A7 Power-up slot control
bits : 1 - 1 (1 bit)
access : read-write
CORE1_A7_PDN_SLOT_CONTROL : CORE1 A7 Power-down slot control
bits : 2 - 2 (1 bit)
access : read-write
CORE1_A7_PUP_SLOT_CONTROL : CORE1 A7 Power-up slot control
bits : 3 - 3 (1 bit)
access : read-write
SCU_PDN_SLOT_CONTROL : SCU Power-down slot control
bits : 4 - 4 (1 bit)
access : read-write
SCU_PUP_SLOT_CONTROL : SCU Power-up slot control
bits : 5 - 5 (1 bit)
access : read-write
FASTMEGA_PDN_SLOT_CONTROL : FASTMEGA Power-down slot control
bits : 6 - 6 (1 bit)
access : read-write
FASTMEGA_PUP_SLOT_CONTROL : FASTMEGA Power-up slot control
bits : 7 - 7 (1 bit)
access : read-write
MIPI_PHY_PDN_SLOT_CONTROL : MIPI_PHY Power-down slot control
bits : 8 - 8 (1 bit)
access : read-write
MIPI_PHY_PUP_SLOT_CONTROL : MIPI_PHY Power-up slot control
bits : 9 - 9 (1 bit)
access : read-write
PCIE_PHY_PDN_SLOT_CONTROL : PCIE_PHY Power-down slot control
bits : 10 - 10 (1 bit)
access : read-write
PCIE_PHY_PUP_SLOT_CONTROL : PCIE_PHY Power-up slot control
bits : 11 - 11 (1 bit)
access : read-write
USB_OTG1_PDN_SLOT_CONTROL : USB_OTG1 Power-down slot control
bits : 12 - 12 (1 bit)
access : read-write
USB_OTG1_PUP_SLOT_CONTROL : USB_OTG1 Power-up slot control
bits : 13 - 13 (1 bit)
access : read-write
USB_OTG2_PDN_SLOT_CONTROL : USB_OTG2 Power-down slot control
bits : 14 - 14 (1 bit)
access : read-write
USB_OTG2_PUP_SLOT_CONTROL : USB_OTG2 Power-up slot control
bits : 15 - 15 (1 bit)
access : read-write
USB_HSIC_PDN_SLOT_CONTROL : USB_HSIC Power-down slot control
bits : 16 - 16 (1 bit)
access : read-write
USB_HSIC_PUP_SLOT_CONTROL : USB_HSIC Power-up slot control
bits : 17 - 17 (1 bit)
access : read-write
M4_VIRTUAL_PDN_SLOT_CONTROL : M4_VIRTUAL Power-down slot control
bits : 18 - 18 (1 bit)
access : read-write
M4_VIRTUAL_PUP_SLOT_CONTROL : M4_VIRTUAL Power-up slot control
bits : 19 - 19 (1 bit)
access : read-write
IRQ masking register 1 of A7 core0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR1_CORE0_A7 : A7 core0 IRQ[31:0] masking bits:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : IMR1_CORE0_A7_0
IRQ not masked
0x1 : IMR1_CORE0_A7_1
IRQ masked
End of enumeration elements list.
A7 PU PGC software down trigger status
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_PDN_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
CORE1_A7_PDN_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
SCU_A7_PDN_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
M4 PU PGC software down trigger status
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
A7_MIPI_PHY_PGC_PDN_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
A7_PCIE_PHY_PGC_PDN_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
A7_USB_OTG1_PHY_PGC_PDN_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
A7_USB_OTG2_PHY_PGC_PDN_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
A7_USB_HSIC_PHY_PGC_PDN_STATUS : no description available
bits : 4 - 4 (1 bit)
access : read-only
IRQ masking register 2 of A7 core0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR2_CORE0_A7 : A7 core0 IRQ[63:32] masking bits:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : IMR2_CORE0_A7_0
IRQ not masked
0x1 : IMR2_CORE0_A7_1
IRQ masked
End of enumeration elements list.
IRQ masking register 3 of A7 core0
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR3_CORE0_A7 : A7 core0 IRQ[95:64] masking bits:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : IMR3_CORE0_A7_0
IRQ not masked
0x1 : IMR3_CORE0_A7_1
IRQ masked
End of enumeration elements list.
Slot configure register
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_PDN_SLOT_CONTROL : CORE0 A7 Power-down slot control
bits : 0 - 0 (1 bit)
access : read-write
CORE0_A7_PUP_SLOT_CONTROL : CORE0 A7 Power-up slot control
bits : 1 - 1 (1 bit)
access : read-write
CORE1_A7_PDN_SLOT_CONTROL : CORE1 A7 Power-down slot control
bits : 2 - 2 (1 bit)
access : read-write
CORE1_A7_PUP_SLOT_CONTROL : CORE1 A7 Power-up slot control
bits : 3 - 3 (1 bit)
access : read-write
SCU_PDN_SLOT_CONTROL : SCU Power-down slot control
bits : 4 - 4 (1 bit)
access : read-write
SCU_PUP_SLOT_CONTROL : SCU Power-up slot control
bits : 5 - 5 (1 bit)
access : read-write
FASTMEGA_PDN_SLOT_CONTROL : FASTMEGA Power-down slot control
bits : 6 - 6 (1 bit)
access : read-write
FASTMEGA_PUP_SLOT_CONTROL : FASTMEGA Power-up slot control
bits : 7 - 7 (1 bit)
access : read-write
MIPI_PHY_PDN_SLOT_CONTROL : MIPI_PHY Power-down slot control
bits : 8 - 8 (1 bit)
access : read-write
MIPI_PHY_PUP_SLOT_CONTROL : MIPI_PHY Power-up slot control
bits : 9 - 9 (1 bit)
access : read-write
PCIE_PHY_PDN_SLOT_CONTROL : PCIE_PHY Power-down slot control
bits : 10 - 10 (1 bit)
access : read-write
PCIE_PHY_PUP_SLOT_CONTROL : PCIE_PHY Power-up slot control
bits : 11 - 11 (1 bit)
access : read-write
USB_OTG1_PDN_SLOT_CONTROL : USB_OTG1 Power-down slot control
bits : 12 - 12 (1 bit)
access : read-write
USB_OTG1_PUP_SLOT_CONTROL : USB_OTG1 Power-up slot control
bits : 13 - 13 (1 bit)
access : read-write
USB_OTG2_PDN_SLOT_CONTROL : USB_OTG2 Power-down slot control
bits : 14 - 14 (1 bit)
access : read-write
USB_OTG2_PUP_SLOT_CONTROL : USB_OTG2 Power-up slot control
bits : 15 - 15 (1 bit)
access : read-write
USB_HSIC_PDN_SLOT_CONTROL : USB_HSIC Power-down slot control
bits : 16 - 16 (1 bit)
access : read-write
USB_HSIC_PUP_SLOT_CONTROL : USB_HSIC Power-up slot control
bits : 17 - 17 (1 bit)
access : read-write
M4_VIRTUAL_PDN_SLOT_CONTROL : M4_VIRTUAL Power-down slot control
bits : 18 - 18 (1 bit)
access : read-write
M4_VIRTUAL_PUP_SLOT_CONTROL : M4_VIRTUAL Power-up slot control
bits : 19 - 19 (1 bit)
access : read-write
A7 MIX software up trigger status register
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
A7_MIPI_PHY_PGC_PUP_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
A7_PCIE_PHY_PGC_PUP_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
A7_USB_OTG1_PHY_PGC_PUP_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
A7_USB_OTG2_PHY_PGC_PUP_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
A7_USB_HSIC_PHY_PGC_PUP_STATUS : no description available
bits : 4 - 4 (1 bit)
access : read-only
IRQ masking register 4 of A7 core0
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR4_CORE0_A7 : A7 core0 IRQ[127:96] masking bits:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : IMR4_CORE0_A7_0
IRQ not masked
0x1 : IMR4_CORE0_A7_1
IRQ masked
End of enumeration elements list.
M4 MIX PGC software up trigger status register
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
M4_MIPI_PHY_PGC_PUP_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
M4_PCIE_PHY_PGC_PUP_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
M4_USB_OTG1_PHY_PGC_PUP_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
M4_USB_OTG2_PHY_PGC_PUP_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
M4_USB_HSIC_PHY_PGC_PUP_STATUS : no description available
bits : 4 - 4 (1 bit)
access : read-only
A7 PU software up trigger status register
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
A7_MIPI_PHY_PGC_PUP_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
A7_PCIE_PHY_PGC_PUP_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
A7_USB_OTG1_PHY_PGC_PUP_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
A7_USB_OTG2_PHY_PGC_PUP_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
A7_USB_HSIC_PHY_PGC_PUP_STATUS : no description available
bits : 4 - 4 (1 bit)
access : read-only
Advanced Low power control register of A7 platform
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN_C0_WFI_PDN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : EN_C0_WFI_PDN_0
CORE0 will not be power down with WFI request
0x1 : EN_C0_WFI_PDN_1
CORE0 will be power down with WFI request
End of enumeration elements list.
EN_C0_PDN : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : EN_C0_PDN_0
CORE0 will not be power down with low power mode request
0x1 : EN_C0_PDN_1
CORE0 will be power down with low power mode request
End of enumeration elements list.
EN_C1_WFI_PDN : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : EN_C1_WFI_PDN_0
CORE1 will not be power down with WFI request
0x1 : EN_C1_WFI_PDN_1
CORE1 will be power down with WFI request
End of enumeration elements list.
EN_C1_PDN : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : EN_C1_PDN_0
CORE1 will not be power down with low power mode request
0x1 : EN_C1_PDN_1
CORE1 will be power down with low power mode request
End of enumeration elements list.
EN_PLAT_PDN : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : EN_PLAT_PDN_0
SCU and L2 cache RAM will not be power down with low power mode request
0x1 : EN_PLAT_PDN_1
SCU and L2 cache RAM will be power down with low power mode request
End of enumeration elements list.
EN_C0_IRQ_PUP : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : EN_C0_IRQ_PUP_0
CORE0 will power up with IRQ request
0x1 : EN_C0_IRQ_PUP_1
CORE0 will not power up with IRQ request
End of enumeration elements list.
EN_C0_PUP : (only used wake up from CPU01_OFF mode)
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : EN_C0_PUP_0
CORE0 will power up with low power mode request
0x1 : EN_C0_PUP_1
CORE0 will not power up with low power mode request
End of enumeration elements list.
EN_C1_IRQ_PUP : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : EN_C1_IRQ_PUP_0
CORE1 will power up with IRQ request
0x1 : EN_C1_IRQ_PUP_1
CORE1 will not power up with IRQ request
End of enumeration elements list.
EN_C1_PUP : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : EN_C1_PUP_0
CORE1 will power up with low power mode request
0x1 : EN_C1_PUP_1
CORE1 will not power up with low power mode request (only used wake up from CPU01_OFF mode)
End of enumeration elements list.
L2_PGE : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : L2_PGE_0
L2 cache RAM will power down with SCU power domain in A7 platform (used for ALL_OFF mode)
0x1 : L2_PGE_1
L2 cache RAM will not power down with SCU power domain in A7 platform (used for L2 retention mode)
End of enumeration elements list.
IRQ masking register 1 of A7 core1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR1_CORE1_A7 : A7 core1 IRQ[31:0] masking bits:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : IMR1_CORE1_A7_0
IRQ not masked
0x1 : IMR1_CORE1_A7_1
IRQ masked
End of enumeration elements list.
M4 PU PGC software up trigger status register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
M4_MIPI_PHY_PGC_PUP_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
M4_PCIE_PHY_PGC_PUP_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
M4_USB_OTG1_PHY_PGC_PUP_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
M4_USB_OTG2_PHY_PGC_PUP_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
M4_USB_HSIC_PHY_PGC_PUP_STATUS : no description available
bits : 4 - 4 (1 bit)
access : read-only
IRQ masking register 2 of A7 core1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR2_CORE1_A7 : A7 core1 IRQ[63:32] masking bits:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : IMR2_CORE1_A7_0
IRQ not masked
0x1 : IMR2_CORE1_A7_1
IRQ masked
End of enumeration elements list.
Slot configure register
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_PDN_SLOT_CONTROL : CORE0 A7 Power-down slot control
bits : 0 - 0 (1 bit)
access : read-write
CORE0_A7_PUP_SLOT_CONTROL : CORE0 A7 Power-up slot control
bits : 1 - 1 (1 bit)
access : read-write
CORE1_A7_PDN_SLOT_CONTROL : CORE1 A7 Power-down slot control
bits : 2 - 2 (1 bit)
access : read-write
CORE1_A7_PUP_SLOT_CONTROL : CORE1 A7 Power-up slot control
bits : 3 - 3 (1 bit)
access : read-write
SCU_PDN_SLOT_CONTROL : SCU Power-down slot control
bits : 4 - 4 (1 bit)
access : read-write
SCU_PUP_SLOT_CONTROL : SCU Power-up slot control
bits : 5 - 5 (1 bit)
access : read-write
FASTMEGA_PDN_SLOT_CONTROL : FASTMEGA Power-down slot control
bits : 6 - 6 (1 bit)
access : read-write
FASTMEGA_PUP_SLOT_CONTROL : FASTMEGA Power-up slot control
bits : 7 - 7 (1 bit)
access : read-write
MIPI_PHY_PDN_SLOT_CONTROL : MIPI_PHY Power-down slot control
bits : 8 - 8 (1 bit)
access : read-write
MIPI_PHY_PUP_SLOT_CONTROL : MIPI_PHY Power-up slot control
bits : 9 - 9 (1 bit)
access : read-write
PCIE_PHY_PDN_SLOT_CONTROL : PCIE_PHY Power-down slot control
bits : 10 - 10 (1 bit)
access : read-write
PCIE_PHY_PUP_SLOT_CONTROL : PCIE_PHY Power-up slot control
bits : 11 - 11 (1 bit)
access : read-write
USB_OTG1_PDN_SLOT_CONTROL : USB_OTG1 Power-down slot control
bits : 12 - 12 (1 bit)
access : read-write
USB_OTG1_PUP_SLOT_CONTROL : USB_OTG1 Power-up slot control
bits : 13 - 13 (1 bit)
access : read-write
USB_OTG2_PDN_SLOT_CONTROL : USB_OTG2 Power-down slot control
bits : 14 - 14 (1 bit)
access : read-write
USB_OTG2_PUP_SLOT_CONTROL : USB_OTG2 Power-up slot control
bits : 15 - 15 (1 bit)
access : read-write
USB_HSIC_PDN_SLOT_CONTROL : USB_HSIC Power-down slot control
bits : 16 - 16 (1 bit)
access : read-write
USB_HSIC_PUP_SLOT_CONTROL : USB_HSIC Power-up slot control
bits : 17 - 17 (1 bit)
access : read-write
M4_VIRTUAL_PDN_SLOT_CONTROL : M4_VIRTUAL Power-down slot control
bits : 18 - 18 (1 bit)
access : read-write
M4_VIRTUAL_PUP_SLOT_CONTROL : M4_VIRTUAL Power-up slot control
bits : 19 - 19 (1 bit)
access : read-write
IRQ masking register 3 of A7 core1
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR3_CORE1_A7 : A7 core1 IRQ[95:64] masking bits:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : IMR3_CORE1_A7_0
IRQ not masked
0x1 : IMR3_CORE1_A7_1
IRQ masked
End of enumeration elements list.
A7 PU PGC software down trigger status
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_PDN_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
CORE1_A7_PDN_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
SCU_A7_PDN_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
IRQ masking register 4 of A7 core1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR4_CORE1_A7 : A7 core1 IRQ[127:96] masking bits:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : IMR4_CORE1_A7_0
IRQ not masked
0x1 : IMR4_CORE1_A7_1
IRQ masked
End of enumeration elements list.
M4 PU PGC software down trigger status
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
A7_MIPI_PHY_PGC_PDN_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
A7_PCIE_PHY_PGC_PDN_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
A7_USB_OTG1_PHY_PGC_PDN_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
A7_USB_OTG2_PHY_PGC_PDN_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
A7_USB_HSIC_PHY_PGC_PDN_STATUS : no description available
bits : 4 - 4 (1 bit)
access : read-only
A7 MIX software up trigger status register
address_offset : 0x4DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
A7_MIPI_PHY_PGC_PUP_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
A7_PCIE_PHY_PGC_PUP_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
A7_USB_OTG1_PHY_PGC_PUP_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
A7_USB_OTG2_PHY_PGC_PUP_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
A7_USB_HSIC_PHY_PGC_PUP_STATUS : no description available
bits : 4 - 4 (1 bit)
access : read-only
IRQ masking register 1 of M4
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR1_M4 : M4 IRQ[31:0] masking bits:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : IMR1_M4_0
IRQ not masked
0x1 : IMR1_M4_1
IRQ masked
End of enumeration elements list.
Slot configure register
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_PDN_SLOT_CONTROL : CORE0 A7 Power-down slot control
bits : 0 - 0 (1 bit)
access : read-write
CORE0_A7_PUP_SLOT_CONTROL : CORE0 A7 Power-up slot control
bits : 1 - 1 (1 bit)
access : read-write
CORE1_A7_PDN_SLOT_CONTROL : CORE1 A7 Power-down slot control
bits : 2 - 2 (1 bit)
access : read-write
CORE1_A7_PUP_SLOT_CONTROL : CORE1 A7 Power-up slot control
bits : 3 - 3 (1 bit)
access : read-write
SCU_PDN_SLOT_CONTROL : SCU Power-down slot control
bits : 4 - 4 (1 bit)
access : read-write
SCU_PUP_SLOT_CONTROL : SCU Power-up slot control
bits : 5 - 5 (1 bit)
access : read-write
FASTMEGA_PDN_SLOT_CONTROL : FASTMEGA Power-down slot control
bits : 6 - 6 (1 bit)
access : read-write
FASTMEGA_PUP_SLOT_CONTROL : FASTMEGA Power-up slot control
bits : 7 - 7 (1 bit)
access : read-write
MIPI_PHY_PDN_SLOT_CONTROL : MIPI_PHY Power-down slot control
bits : 8 - 8 (1 bit)
access : read-write
MIPI_PHY_PUP_SLOT_CONTROL : MIPI_PHY Power-up slot control
bits : 9 - 9 (1 bit)
access : read-write
PCIE_PHY_PDN_SLOT_CONTROL : PCIE_PHY Power-down slot control
bits : 10 - 10 (1 bit)
access : read-write
PCIE_PHY_PUP_SLOT_CONTROL : PCIE_PHY Power-up slot control
bits : 11 - 11 (1 bit)
access : read-write
USB_OTG1_PDN_SLOT_CONTROL : USB_OTG1 Power-down slot control
bits : 12 - 12 (1 bit)
access : read-write
USB_OTG1_PUP_SLOT_CONTROL : USB_OTG1 Power-up slot control
bits : 13 - 13 (1 bit)
access : read-write
USB_OTG2_PDN_SLOT_CONTROL : USB_OTG2 Power-down slot control
bits : 14 - 14 (1 bit)
access : read-write
USB_OTG2_PUP_SLOT_CONTROL : USB_OTG2 Power-up slot control
bits : 15 - 15 (1 bit)
access : read-write
USB_HSIC_PDN_SLOT_CONTROL : USB_HSIC Power-down slot control
bits : 16 - 16 (1 bit)
access : read-write
USB_HSIC_PUP_SLOT_CONTROL : USB_HSIC Power-up slot control
bits : 17 - 17 (1 bit)
access : read-write
M4_VIRTUAL_PDN_SLOT_CONTROL : M4_VIRTUAL Power-down slot control
bits : 18 - 18 (1 bit)
access : read-write
M4_VIRTUAL_PUP_SLOT_CONTROL : M4_VIRTUAL Power-up slot control
bits : 19 - 19 (1 bit)
access : read-write
M4 MIX PGC software up trigger status register
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
M4_MIPI_PHY_PGC_PUP_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
M4_PCIE_PHY_PGC_PUP_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
M4_USB_OTG1_PHY_PGC_PUP_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
M4_USB_OTG2_PHY_PGC_PUP_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
M4_USB_HSIC_PHY_PGC_PUP_STATUS : no description available
bits : 4 - 4 (1 bit)
access : read-only
A7 PU software up trigger status register
address_offset : 0x53C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
A7_MIPI_PHY_PGC_PUP_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
A7_PCIE_PHY_PGC_PUP_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
A7_USB_OTG1_PHY_PGC_PUP_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
A7_USB_OTG2_PHY_PGC_PUP_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
A7_USB_HSIC_PHY_PGC_PUP_STATUS : no description available
bits : 4 - 4 (1 bit)
access : read-only
IRQ masking register 2 of M4
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR2_M4 : M4 IRQ[63:32] masking bits:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : IMR2_M4_0
IRQ not masked
0x1 : IMR2_M4_1
IRQ masked
End of enumeration elements list.
M4 PU PGC software up trigger status register
address_offset : 0x56C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
M4_MIPI_PHY_PGC_PUP_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
M4_PCIE_PHY_PGC_PUP_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
M4_USB_OTG1_PHY_PGC_PUP_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
M4_USB_OTG2_PHY_PGC_PUP_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
M4_USB_HSIC_PHY_PGC_PUP_STATUS : no description available
bits : 4 - 4 (1 bit)
access : read-only
IRQ masking register 3 of M4
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR3_M4 : M4 IRQ[95:64] masking bits:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : IMR3_M4_0
IRQ not masked
0x1 : IMR3_M4_1
IRQ masked
End of enumeration elements list.
IRQ masking register 4 of M4
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR4_M4 : M4 IRQ[127:96] masking bits:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : IMR4_M4_0
IRQ not masked
0x1 : IMR4_M4_1
IRQ masked
End of enumeration elements list.
Slot configure register
address_offset : 0x5D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_PDN_SLOT_CONTROL : CORE0 A7 Power-down slot control
bits : 0 - 0 (1 bit)
access : read-write
CORE0_A7_PUP_SLOT_CONTROL : CORE0 A7 Power-up slot control
bits : 1 - 1 (1 bit)
access : read-write
CORE1_A7_PDN_SLOT_CONTROL : CORE1 A7 Power-down slot control
bits : 2 - 2 (1 bit)
access : read-write
CORE1_A7_PUP_SLOT_CONTROL : CORE1 A7 Power-up slot control
bits : 3 - 3 (1 bit)
access : read-write
SCU_PDN_SLOT_CONTROL : SCU Power-down slot control
bits : 4 - 4 (1 bit)
access : read-write
SCU_PUP_SLOT_CONTROL : SCU Power-up slot control
bits : 5 - 5 (1 bit)
access : read-write
FASTMEGA_PDN_SLOT_CONTROL : FASTMEGA Power-down slot control
bits : 6 - 6 (1 bit)
access : read-write
FASTMEGA_PUP_SLOT_CONTROL : FASTMEGA Power-up slot control
bits : 7 - 7 (1 bit)
access : read-write
MIPI_PHY_PDN_SLOT_CONTROL : MIPI_PHY Power-down slot control
bits : 8 - 8 (1 bit)
access : read-write
MIPI_PHY_PUP_SLOT_CONTROL : MIPI_PHY Power-up slot control
bits : 9 - 9 (1 bit)
access : read-write
PCIE_PHY_PDN_SLOT_CONTROL : PCIE_PHY Power-down slot control
bits : 10 - 10 (1 bit)
access : read-write
PCIE_PHY_PUP_SLOT_CONTROL : PCIE_PHY Power-up slot control
bits : 11 - 11 (1 bit)
access : read-write
USB_OTG1_PDN_SLOT_CONTROL : USB_OTG1 Power-down slot control
bits : 12 - 12 (1 bit)
access : read-write
USB_OTG1_PUP_SLOT_CONTROL : USB_OTG1 Power-up slot control
bits : 13 - 13 (1 bit)
access : read-write
USB_OTG2_PDN_SLOT_CONTROL : USB_OTG2 Power-down slot control
bits : 14 - 14 (1 bit)
access : read-write
USB_OTG2_PUP_SLOT_CONTROL : USB_OTG2 Power-up slot control
bits : 15 - 15 (1 bit)
access : read-write
USB_HSIC_PDN_SLOT_CONTROL : USB_HSIC Power-down slot control
bits : 16 - 16 (1 bit)
access : read-write
USB_HSIC_PUP_SLOT_CONTROL : USB_HSIC Power-up slot control
bits : 17 - 17 (1 bit)
access : read-write
M4_VIRTUAL_PDN_SLOT_CONTROL : M4_VIRTUAL Power-down slot control
bits : 18 - 18 (1 bit)
access : read-write
M4_VIRTUAL_PUP_SLOT_CONTROL : M4_VIRTUAL Power-up slot control
bits : 19 - 19 (1 bit)
access : read-write
A7 PU PGC software down trigger status
address_offset : 0x63C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_PDN_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
CORE1_A7_PDN_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
SCU_A7_PDN_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
M4 PU PGC software down trigger status
address_offset : 0x66C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
A7_MIPI_PHY_PGC_PDN_STATUS : no description available
bits : 0 - 0 (1 bit)
access : read-only
A7_PCIE_PHY_PGC_PDN_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-only
A7_USB_OTG1_PHY_PGC_PDN_STATUS : no description available
bits : 2 - 2 (1 bit)
access : read-only
A7_USB_OTG2_PHY_PGC_PDN_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
A7_USB_HSIC_PHY_PGC_PDN_STATUS : no description available
bits : 4 - 4 (1 bit)
access : read-only
Slot configure register
address_offset : 0x6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_PDN_SLOT_CONTROL : CORE0 A7 Power-down slot control
bits : 0 - 0 (1 bit)
access : read-write
CORE0_A7_PUP_SLOT_CONTROL : CORE0 A7 Power-up slot control
bits : 1 - 1 (1 bit)
access : read-write
CORE1_A7_PDN_SLOT_CONTROL : CORE1 A7 Power-down slot control
bits : 2 - 2 (1 bit)
access : read-write
CORE1_A7_PUP_SLOT_CONTROL : CORE1 A7 Power-up slot control
bits : 3 - 3 (1 bit)
access : read-write
SCU_PDN_SLOT_CONTROL : SCU Power-down slot control
bits : 4 - 4 (1 bit)
access : read-write
SCU_PUP_SLOT_CONTROL : SCU Power-up slot control
bits : 5 - 5 (1 bit)
access : read-write
FASTMEGA_PDN_SLOT_CONTROL : FASTMEGA Power-down slot control
bits : 6 - 6 (1 bit)
access : read-write
FASTMEGA_PUP_SLOT_CONTROL : FASTMEGA Power-up slot control
bits : 7 - 7 (1 bit)
access : read-write
MIPI_PHY_PDN_SLOT_CONTROL : MIPI_PHY Power-down slot control
bits : 8 - 8 (1 bit)
access : read-write
MIPI_PHY_PUP_SLOT_CONTROL : MIPI_PHY Power-up slot control
bits : 9 - 9 (1 bit)
access : read-write
PCIE_PHY_PDN_SLOT_CONTROL : PCIE_PHY Power-down slot control
bits : 10 - 10 (1 bit)
access : read-write
PCIE_PHY_PUP_SLOT_CONTROL : PCIE_PHY Power-up slot control
bits : 11 - 11 (1 bit)
access : read-write
USB_OTG1_PDN_SLOT_CONTROL : USB_OTG1 Power-down slot control
bits : 12 - 12 (1 bit)
access : read-write
USB_OTG1_PUP_SLOT_CONTROL : USB_OTG1 Power-up slot control
bits : 13 - 13 (1 bit)
access : read-write
USB_OTG2_PDN_SLOT_CONTROL : USB_OTG2 Power-down slot control
bits : 14 - 14 (1 bit)
access : read-write
USB_OTG2_PUP_SLOT_CONTROL : USB_OTG2 Power-up slot control
bits : 15 - 15 (1 bit)
access : read-write
USB_HSIC_PDN_SLOT_CONTROL : USB_HSIC Power-down slot control
bits : 16 - 16 (1 bit)
access : read-write
USB_HSIC_PUP_SLOT_CONTROL : USB_HSIC Power-up slot control
bits : 17 - 17 (1 bit)
access : read-write
M4_VIRTUAL_PDN_SLOT_CONTROL : M4_VIRTUAL Power-down slot control
bits : 18 - 18 (1 bit)
access : read-write
M4_VIRTUAL_PUP_SLOT_CONTROL : M4_VIRTUAL Power-up slot control
bits : 19 - 19 (1 bit)
access : read-write
IRQ status register 1 of A7
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISR1_A7 : A7 IRQ[31:0] status
bits : 0 - 31 (32 bit)
access : read-only
IRQ status register 2 of A7
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISR2_A7 : A7 IRQ[63:32] status
bits : 0 - 31 (32 bit)
access : read-only
Slot configure register
address_offset : 0x770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_PDN_SLOT_CONTROL : CORE0 A7 Power-down slot control
bits : 0 - 0 (1 bit)
access : read-write
CORE0_A7_PUP_SLOT_CONTROL : CORE0 A7 Power-up slot control
bits : 1 - 1 (1 bit)
access : read-write
CORE1_A7_PDN_SLOT_CONTROL : CORE1 A7 Power-down slot control
bits : 2 - 2 (1 bit)
access : read-write
CORE1_A7_PUP_SLOT_CONTROL : CORE1 A7 Power-up slot control
bits : 3 - 3 (1 bit)
access : read-write
SCU_PDN_SLOT_CONTROL : SCU Power-down slot control
bits : 4 - 4 (1 bit)
access : read-write
SCU_PUP_SLOT_CONTROL : SCU Power-up slot control
bits : 5 - 5 (1 bit)
access : read-write
FASTMEGA_PDN_SLOT_CONTROL : FASTMEGA Power-down slot control
bits : 6 - 6 (1 bit)
access : read-write
FASTMEGA_PUP_SLOT_CONTROL : FASTMEGA Power-up slot control
bits : 7 - 7 (1 bit)
access : read-write
MIPI_PHY_PDN_SLOT_CONTROL : MIPI_PHY Power-down slot control
bits : 8 - 8 (1 bit)
access : read-write
MIPI_PHY_PUP_SLOT_CONTROL : MIPI_PHY Power-up slot control
bits : 9 - 9 (1 bit)
access : read-write
PCIE_PHY_PDN_SLOT_CONTROL : PCIE_PHY Power-down slot control
bits : 10 - 10 (1 bit)
access : read-write
PCIE_PHY_PUP_SLOT_CONTROL : PCIE_PHY Power-up slot control
bits : 11 - 11 (1 bit)
access : read-write
USB_OTG1_PDN_SLOT_CONTROL : USB_OTG1 Power-down slot control
bits : 12 - 12 (1 bit)
access : read-write
USB_OTG1_PUP_SLOT_CONTROL : USB_OTG1 Power-up slot control
bits : 13 - 13 (1 bit)
access : read-write
USB_OTG2_PDN_SLOT_CONTROL : USB_OTG2 Power-down slot control
bits : 14 - 14 (1 bit)
access : read-write
USB_OTG2_PUP_SLOT_CONTROL : USB_OTG2 Power-up slot control
bits : 15 - 15 (1 bit)
access : read-write
USB_HSIC_PDN_SLOT_CONTROL : USB_HSIC Power-down slot control
bits : 16 - 16 (1 bit)
access : read-write
USB_HSIC_PUP_SLOT_CONTROL : USB_HSIC Power-up slot control
bits : 17 - 17 (1 bit)
access : read-write
M4_VIRTUAL_PDN_SLOT_CONTROL : M4_VIRTUAL Power-down slot control
bits : 18 - 18 (1 bit)
access : read-write
M4_VIRTUAL_PUP_SLOT_CONTROL : M4_VIRTUAL Power-up slot control
bits : 19 - 19 (1 bit)
access : read-write
IRQ status register 3 of A7
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISR3_A7 : A7 IRQ[95:64] status
bits : 0 - 31 (32 bit)
access : read-only
IRQ status register 4 of A7
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISR4_A7 : A7 IRQ[127:96] status
bits : 0 - 31 (32 bit)
access : read-only
Low power control register of CPU1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPM0 : Setting the low power mode that system will enter on next assertion of dsm_request signal.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : LPM0_0
Remain in RUN mode
0x1 : LPM0_1
Transfer to WAIT mode
0x2 : LPM0_2
Transfer to STOP mode
End of enumeration elements list.
EN_M4_PDN : Enable m4 virtual PGC power down with LPM enter
bits : 2 - 2 (1 bit)
access : read-write
EN_M4_PUP : Enable m4 virtual PGC power up with LPM enter
bits : 3 - 3 (1 bit)
access : read-write
CPU_CLK_ON_LPM : Define if M4 clocks will be disabled on wait/stop mode.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : CPU_CLK_ON_LPM_0
M4 clock disabled on wait/stop mode.
0x1 : CPU_CLK_ON_LPM_1
M4 clock enabled on wait/stop mode.
End of enumeration elements list.
MASK_M4_WFI : M4 WFI Mask
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : MASK_M4_WFI_0
WFI for M4 is not masked
0x1 : MASK_M4_WFI_1
WFI for M4 is masked
End of enumeration elements list.
MASK_DSM_TRIGGER : M4 WFI Mask
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : MASK_DSM_TRIGGER_0
DSM trigger of M4 platform will not be masked
0x1 : MASK_DSM_TRIGGER_1
DSM trigger of M4 platform will be masked
End of enumeration elements list.
IRQ status register 1 of M4
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISR1_M4 : M4 IRQ[31:0] status
bits : 0 - 31 (32 bit)
access : read-only
IRQ status register 2 of M4
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISR2_M4 : M4 IRQ[63:32] status
bits : 0 - 31 (32 bit)
access : read-only
Slot configure register
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_PDN_SLOT_CONTROL : CORE0 A7 Power-down slot control
bits : 0 - 0 (1 bit)
access : read-write
CORE0_A7_PUP_SLOT_CONTROL : CORE0 A7 Power-up slot control
bits : 1 - 1 (1 bit)
access : read-write
CORE1_A7_PDN_SLOT_CONTROL : CORE1 A7 Power-down slot control
bits : 2 - 2 (1 bit)
access : read-write
CORE1_A7_PUP_SLOT_CONTROL : CORE1 A7 Power-up slot control
bits : 3 - 3 (1 bit)
access : read-write
SCU_PDN_SLOT_CONTROL : SCU Power-down slot control
bits : 4 - 4 (1 bit)
access : read-write
SCU_PUP_SLOT_CONTROL : SCU Power-up slot control
bits : 5 - 5 (1 bit)
access : read-write
FASTMEGA_PDN_SLOT_CONTROL : FASTMEGA Power-down slot control
bits : 6 - 6 (1 bit)
access : read-write
FASTMEGA_PUP_SLOT_CONTROL : FASTMEGA Power-up slot control
bits : 7 - 7 (1 bit)
access : read-write
MIPI_PHY_PDN_SLOT_CONTROL : MIPI_PHY Power-down slot control
bits : 8 - 8 (1 bit)
access : read-write
MIPI_PHY_PUP_SLOT_CONTROL : MIPI_PHY Power-up slot control
bits : 9 - 9 (1 bit)
access : read-write
PCIE_PHY_PDN_SLOT_CONTROL : PCIE_PHY Power-down slot control
bits : 10 - 10 (1 bit)
access : read-write
PCIE_PHY_PUP_SLOT_CONTROL : PCIE_PHY Power-up slot control
bits : 11 - 11 (1 bit)
access : read-write
USB_OTG1_PDN_SLOT_CONTROL : USB_OTG1 Power-down slot control
bits : 12 - 12 (1 bit)
access : read-write
USB_OTG1_PUP_SLOT_CONTROL : USB_OTG1 Power-up slot control
bits : 13 - 13 (1 bit)
access : read-write
USB_OTG2_PDN_SLOT_CONTROL : USB_OTG2 Power-down slot control
bits : 14 - 14 (1 bit)
access : read-write
USB_OTG2_PUP_SLOT_CONTROL : USB_OTG2 Power-up slot control
bits : 15 - 15 (1 bit)
access : read-write
USB_HSIC_PDN_SLOT_CONTROL : USB_HSIC Power-down slot control
bits : 16 - 16 (1 bit)
access : read-write
USB_HSIC_PUP_SLOT_CONTROL : USB_HSIC Power-up slot control
bits : 17 - 17 (1 bit)
access : read-write
M4_VIRTUAL_PDN_SLOT_CONTROL : M4_VIRTUAL Power-down slot control
bits : 18 - 18 (1 bit)
access : read-write
M4_VIRTUAL_PUP_SLOT_CONTROL : M4_VIRTUAL Power-up slot control
bits : 19 - 19 (1 bit)
access : read-write
IRQ status register 3 of M4
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISR3_M4 : M4 IRQ[95:64] status
bits : 0 - 31 (32 bit)
access : read-only
IRQ status register 4 of M4
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISR4_M4 : M4 IRQ[127:96] status
bits : 0 - 31 (32 bit)
access : read-only
PGC CPU mapping
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FASTMEGA_A7_DOMAIN : FAST/MEGA mapping
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FASTMEGA_A7_DOMAIN_0
Don't map FAST/MEGA to A7 domain
0x1 : FASTMEGA_A7_DOMAIN_1
Map FAST/MEGA to A7 domain
End of enumeration elements list.
MIPI_PHY_A7_DOMAIN : MIPI_PHY mapping
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : MIPI_PHY_A7_DOMAIN_0
Don't map MIPI_PHY to A7 domain
0x1 : MIPI_PHY_A7_DOMAIN_1
Map MIPI_PHY to A7 domain
End of enumeration elements list.
PCIE_PHY_A7_DOMAIN : MIPI_PHY mapping
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PCIE_PHY_A7_DOMAIN_0
Don't map PCIE_PHY to A7 domain
0x1 : PCIE_PHY_A7_DOMAIN_1
Map PCIE_PHY to A7 domain
End of enumeration elements list.
USB_OTG1_PHY_A7_DOMAIN : USB_OTG1_PHY mapping
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : USB_OTG1_PHY_A7_DOMAIN_0
Don't map USB_OTG1_PHY to A7 domain
0x1 : USB_OTG1_PHY_A7_DOMAIN_1
Map USB_OTG1_PHY to A7 domain
End of enumeration elements list.
USB_OTG2_PHY_A7_DOMAIN : USB_OTG2_PHY mapping
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : USB_OTG2_PHY_A7_DOMAIN_0
Don't map USB_OTG2_PHY to A7 domain
0x1 : USB_OTG2_PHY_A7_DOMAIN_1
Map USB_OTG2_PHY to A7 domain
End of enumeration elements list.
USB_HSIC_PHY_A7_DOMAIN : USB_HSIC_PHY mapping
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : USB_HSIC_PHY_A7_DOMAIN_0
Don't map USB_HSIC_PHY to A7 domain
0x1 : USB_HSIC_PHY_A7_DOMAIN_1
Map USB_HSIC_PHY to A7 domain
End of enumeration elements list.
FASTMEGA_M4_DOMAIN : FAST/MEGA mapping
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : FASTMEGA_M4_DOMAIN_0
Don't map FAST/MEGA to M4 domain
0x1 : FASTMEGA_M4_DOMAIN_1
Map FAST/MEGA to M4 domain
End of enumeration elements list.
MIPI_PHY_M4_DOMAIN : MIPI_PHY mapping
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : MIPI_PHY_M4_DOMAIN_0
Don't map MIPI_PHY to M4 domain
0x1 : MIPI_PHY_M4_DOMAIN_1
Map MIPI_PHY to M4 domain
End of enumeration elements list.
PCIE_PHY_M4_DOMAIN : MIPI_PHY mapping
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : PCIE_PHY_M4_DOMAIN_0
Don't map PCIE_PHY to M4 domain
0x1 : PCIE_PHY_M4_DOMAIN_1
Map PCIE_PHY to M4 domain
End of enumeration elements list.
USB_OTG1_PHY_M4_DOMAIN : USB_OTG1_PHY mapping
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : USB_OTG1_PHY_M4_DOMAIN_0
Don't map USB_OTG1_PHY to M4 domain
0x1 : USB_OTG1_PHY_M4_DOMAIN_1
Map USB_OTG1_PHY to M4 domain
End of enumeration elements list.
USB_OTG2_PHY_M4_DOMAIN : USB_OTG2_PHY mapping
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : USB_OTG2_PHY_M4_DOMAIN_0
Don't map USB_OTG2_PHY to M4 domain
0x1 : USB_OTG2_PHY_M4_DOMAIN_1
Map USB_OTG2_PHY to M4 domain
End of enumeration elements list.
USB_HSIC_PHY_M4_DOMAIN : USB_HSIC_PHY mapping
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : USB_HSIC_PHY_M4_DOMAIN_0
Don't map USB_HSIC_PHY to M4 domain
0x1 : USB_HSIC_PHY_M4_DOMAIN_1
Map USB_HSIC_PHY to M4 domain
End of enumeration elements list.
CPU PGC software up trigger
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_SW_PUP_REQ : Software power up trigger for Core0 A7 PGC
bits : 0 - 0 (1 bit)
access : read-write
CORE1_A7_SW_PUP_REQ : Software power up trigger for Core1 A7 PGC
bits : 1 - 1 (1 bit)
access : read-write
SCU_A7_SW_PUP_REQ : Software power up trigger for SCU A7
bits : 2 - 2 (1 bit)
access : read-write
PU PGC software up trigger
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MIPI_PHY_SW_PUP_REQ : Software power up trigger for MIPI_PHY
bits : 0 - 0 (1 bit)
access : read-write
PCIE_PHY_SW_PUP_REQ : Software power up trigger for PCIE_PHY
bits : 1 - 1 (1 bit)
access : read-write
USB_OTG1_PHY_SW_PUP_REQ : Software power up trigger for USB_OTG1_PHY
bits : 2 - 2 (1 bit)
access : read-write
USB_OTG2_PHY_SW_PUP_REQ : Software power up trigger for USB_OTG2_PHY
bits : 3 - 3 (1 bit)
access : read-write
USB_HSIC_PHY_SW_PUP_REQ : Software power up trigger for USB_HSIC_PHY
bits : 4 - 4 (1 bit)
access : read-write
CPU PGC software down trigger
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CORE0_A7_SW_PDN_REQ : Software power down trigger for Core0 A7 PGC
bits : 0 - 0 (1 bit)
access : read-write
CORE1_A7_SW_PDN_REQ : Software power down trigger for Core1 A7 PGC
bits : 1 - 1 (1 bit)
access : read-write
SCU_A7_SW_PDN_REQ : Software power down trigger for SCU A7
bits : 2 - 2 (1 bit)
access : read-write
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