Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2004 byte (0x0)
mem_usage : registers
protection : not protected
CSIS Interrupt Mask
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSK_ERR_id : Unknown ID Error
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MSK_ERR_id_0
Disable (masked)
0x1 : MSK_ERR_id_1
Enable (unmasked)
End of enumeration elements list.
MSK_ERR_CRC : CRC Error
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : MSK_ERR_CRC_0
Disable (masked)
0x1 : MSK_ERR_CRC_1
Enable (unmasked)
End of enumeration elements list.
MSK_ERR_ECC : ECC Error
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : MSK_ERR_ECC_0
Disable (masked)
0x1 : MSK_ERR_ECC_1
Enable (unmasked)
End of enumeration elements list.
MSK_ERR_WRONG_CFG : Wrong configuration
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : MSK_ERR_WRONG_CFG_0
Disable (masked)
0x1 : MSK_ERR_WRONG_CFG_1
Enable (unmasked)
End of enumeration elements list.
MSK_ERR_OVER : Image FIFO overflow interrupt, [CH3,CH2,CH1,CH0]
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : MSK_ERR_OVER_0
Disable (masked)
0x1 : MSK_ERR_OVER_1
Enable (unmasked)
End of enumeration elements list.
MSK_ERR_LOST_FE : Lost of Frame End packet, [CH3,CH2,CH1,CH0]
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : MSK_ERR_LOST_FE_0
Disable (masked)
0x1 : MSK_ERR_LOST_FE_1
Enable (unmasked)
End of enumeration elements list.
MSK_ERR_LOST_FS : Lost of Frame Start packet, [CH3,CH2,CH1,CH0]
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : MSK_ERR_LOST_FS_0
Disable (masked)
0x1 : MSK_ERR_LOST_FS_1
Enable (unmasked)
End of enumeration elements list.
MSK_ERR_SOT_HS : Start of transmission error [reserved, reserved, Lane1, Lane0]
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : MSK_ERR_SOT_HS_0
Disable (masked)
0x1 : MSK_ERR_SOT_HS_1
Enable (unmasked)
End of enumeration elements list.
MSK_FRAMEEND : FE packet is received, [CH3,CH2,CH1,CH0]
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0 : MSK_FRAMEEND_0
Disable (masked)
0x1 : MSK_FRAMEEND_1
Enable (unmasked)
End of enumeration elements list.
MSK_FRAMESTART : FS packet is received, [CH3,CH2,CH1,CH0]
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : MSK_FRAMESTART_0
Disable (masked)
0x1 : MSK_FRAMESTART_1
Enable (unmasked)
End of enumeration elements list.
MSK_ODDAFTER : Non Image data are received at Odd frame and After Image.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : MSK_ODDAFTER_0
Disable (masked)
0x1 : MSK_ODDAFTER_1
Enable (unmasked)
End of enumeration elements list.
MSK_ODDBEFORE : Non Image data are received at Odd frame and Before Image.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : MSK_ODDBEFORE_0
Disable (masked)
0x1 : MSK_ODDBEFORE_1
Enable (unmasked)
End of enumeration elements list.
MSK_EVENAFTER : Non Image data are received at Even frame and After Image.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : MSK_EVENAFTER_0
Disable (masked)
0x1 : MSK_EVENAFTER_1
Enable (unmasked)
End of enumeration elements list.
MSK_EVENBEFORE : Non Image data are received at Even frame and Before Image.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : MSK_EVENBEFORE_0
Disable (masked)
0x1 : MSK_EVENBEFORE_1
Enable (unmasked)
End of enumeration elements list.
CSIS Interrupt Source
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR_ID : Unknown ID Error
bits : 0 - 0 (1 bit)
access : read-write
ERR_CRC : CRC Error
bits : 1 - 1 (1 bit)
access : read-write
ERR_ECC : ECC Error
bits : 2 - 2 (1 bit)
access : read-write
ERR_WRONG_CFG : Wrong Configuration
bits : 3 - 3 (1 bit)
access : read-write
ERR_OVER : Overflow is caused in image FIFO, [CH3,CH2,CH1,CH0] Outer bandwidth has to be faster than imputer bandwidth
bits : 4 - 7 (4 bit)
access : read-write
ERR_LOST_FE : Indication of lost of Frame End packet, [CH3,CH2,CH1,CH0]
bits : 8 - 11 (4 bit)
access : read-write
ERR_LOST_FS : Indication of lost of Frame Start packet, [CH3,CH2,CH1,CH0]
bits : 12 - 15 (4 bit)
access : read-write
ERR_SOT_HS : Start of transmission error, [reserved, reserved, Lane1 , Lane0]
bits : 16 - 19 (4 bit)
access : read-write
FRAMEEND : FE packet is received, [CH3,CH2,CH1,CH0]
bits : 20 - 23 (4 bit)
access : read-write
FRAMESTART : FS packet is received, [CH3,CH2,CH1,CH0]
bits : 24 - 27 (4 bit)
access : read-write
ODDAFTER : Non Image data are received at Odd frame and After Image.
bits : 28 - 28 (1 bit)
access : read-write
ODDBEFORE : Non Image data are received at Odd frame and Before Image.
bits : 29 - 29 (1 bit)
access : read-write
EVENAFTER : Non Image data are received at Even frame and After Image.
bits : 30 - 30 (1 bit)
access : read-write
EVENBEFORE : Non Image data are received at Even frame and Before Image.
bits : 31 - 31 (1 bit)
access : read-write
D-PHY Status
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STOPSTATECLK : Clock lane is in Stop state.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : STOPSTATECLK_0
Not Stop state
0x1 : STOPSTATECLK_1
Stop state
End of enumeration elements list.
ULPSCLK : Clock lane is in ULPS.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : ULPSCLK_0
Not ULPS
0x1 : ULPSCLK_1
ULPS
End of enumeration elements list.
RSVD6 : Reserved
bits : 2 - 3 (2 bit)
access : read-only
STOPSTATEDAT : Data lane [3:0] is in Stop State. [7]: Reserved [6]: Reserved [5]: Data lane 1 [4]: Data lane 0
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
0 : STOPSTATEDAT_0
Not Stop state
0x1 : STOPSTATEDAT_1
Stop state
End of enumeration elements list.
ULPSDAT : Data lane [3:0] is in ULPS. [11]: Reserved [10]: Reserved [9]: Data lane 1 [8]: Dsata lane 0
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : ULPSDAT_0
Not ULPS
0x1 : ULPSDAT_1
ULPS
End of enumeration elements list.
RSVD5 : Reserved
bits : 12 - 31 (20 bit)
access : read-only
Non Image Data
address_offset : 0x2000 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NONIMGDATA : Non Image data memory
bits : 0 - 31 (32 bit)
access : read-only
D-PHY Common Control
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_CLK : D-PHY clock lane enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ENABLE_CLK_0
Disable
0x1 : ENABLE_CLK_1
Enable
End of enumeration elements list.
ENABLE_DAT : D-PHY enable
bits : 1 - 4 (4 bit)
access : read-write
Enumeration:
0 : ENABLE_DAT_0
Disable
0x1 : ENABLE_DAT_1
Enable
End of enumeration elements list.
S_DPDN_SWAP_DAT : Swapping Dp and Dn channel of data lanes.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : S_DPDN_SWAP_DAT_0
Default
0x1 : S_DPDN_SWAP_DAT_1
Swapped
End of enumeration elements list.
S_DPDN_SWAP_CLK : Swapping Dp and Dn channel of clock lane.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : S_DPDN_SWAP_CLK_0
Default
0x1 : S_DPDN_SWAP_CLK_1
Swapped
End of enumeration elements list.
RSVD7 : Reserved
bits : 7 - 21 (15 bit)
access : read-only
S_CLKSETTLECTL : D-PHY control register is for standard spec v0.9 of MIPI CSI2.
bits : 22 - 23 (2 bit)
access : read-write
HSSETTLE : HS-RX settle time control register
bits : 24 - 31 (8 bit)
access : read-write
D-PHY Master and Slave Control register low
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B_DPHYCTRL : D-PHY Master and Slave control register Low part
bits : 0 - 31 (32 bit)
access : read-write
D-PHY Master and Slave Control register high
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B_DPHYCTRL : D-PHY Master and Slave control register High part
bits : 0 - 31 (32 bit)
access : read-write
D-PHY Slave Control register low
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S_DPHYCTRL : D-PHY Slave control register Low part
bits : 0 - 31 (32 bit)
access : read-write
D-PHY Slave Control register high
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S_DPHYCTRL : D-PHY Slave control register High part
bits : 0 - 31 (32 bit)
access : read-write
CSIS Common Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSI_EN : MIPI CSI2 system enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CSI_EN_0
Disable
0x1 : CSI_EN_1
Enable
End of enumeration elements list.
SW_REST : Software Reset
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
0 : SW_REST_0
Ready
0x1 : SW_REST_1
Reset
End of enumeration elements list.
UPDATE_SHADOW_CTRL : Update Shadow Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : UPDATE_SHADOW_CTRL_0
Disable (default)
0x1 : UPDATE_SHADOW_CTRL_1
Enable
End of enumeration elements list.
RSVD3 : Reserved
bits : 3 - 7 (5 bit)
access : read-only
LANE_NUMBER : Number of data lane
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : LANE_NUMBER_0
1 data lane
0x1 : LANE_NUMBER_1
2 data lane
End of enumeration elements list.
INTERLEAVE_MODE : Select Interleave mode, VC (Virtual channel) and DT (Data type)
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : INTERLEAVE_MODE_0
CH0 only, no data interleave
0x1 : INTERLEAVE_MODE_1
DT only
0x2 : INTERLEAVE_MODE_2
VC only
0x3 : INTERLEAVE_MODE_3
VC and DT
End of enumeration elements list.
RSVD2 : Reserved
bits : 12 - 15 (4 bit)
access : read-only
UPDATE_SHADOW : Strobe of updating shadow registers
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : UPDATE_SHADOW_0
Default
0x1 : UPDATE_SHADOW_1
Update the shadow registers
End of enumeration elements list.
RSVD1 : Reserved
bits : 20 - 31 (12 bit)
access : read-only
ISP Configuration register of CH0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VIRTUAL_CHANNEL : Set Virtual channel for data interleave
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : VIRTUAL_CHANNEL_0
VC = 0
0x1 : VIRTUAL_CHANNEL_1
VC = 1
0x2 : VIRTUAL_CHANNEL_2
VC = 2
0x3 : VIRTUAL_CHANNEL_3
VC = 3
End of enumeration elements list.
DATAFORMAT : Image Data Format
bits : 2 - 7 (6 bit)
access : read-write
Enumeration:
0x18 : DATAFORMAT_24
YUV420 (8-bit)
0x19 : DATAFORMAT_25
YUV420 (10-bit)
0x1A : DATAFORMAT_26
YUV420 (8-bit legacy)
0x1C : DATAFORMAT_28
YUV420 (8-bit CSPS)
0x1D : DATAFORMAT_29
YUV420 (10-bit CSPS)
0x1E : DATAFORMAT_30
YUV422 (8-bit)
0x1F : DATAFORMAT_31
YUV422 (10-bit)
0x22 : DATAFORMAT_34
RGB565
0x23 : DATAFORMAT_35
RGB666
0x24 : DATAFORMAT_36
RGB888
0x28 : DATAFORMAT_40
RAW6
0x29 : DATAFORMAT_41
RAW7
0x2A : DATAFORMAT_42
RAW8
0x2B : DATAFORMAT_43
RAW10
0x2C : DATAFORMAT_44
RAW12
0x2D : DATAFORMAT_45
RAW14
0x30 : DATAFORMAT_48
User defined 1
0x31 : DATAFORMAT_49
User defined 2
0x32 : DATAFORMAT_50
User defined 3
0x33 : DATAFORMAT_51
User defined 4
0x34 : DATAFORMAT_52
User defined 5
0x35 : DATAFORMAT_53
User defined 6
0x36 : DATAFORMAT_54
User defined 7
0x37 : DATAFORMAT_55
User defined 8
End of enumeration elements list.
DECOMP_EN : Decompress Enable Do not enable this when data format is not RAW6 / 7 / 8 / 10.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DECOMP_EN_0
Disable (default)
0x1 : DECOMP_EN_1
Enable
End of enumeration elements list.
DECOMP_PREDICT : Decompress prediction mode of CH0 Cannot use advanced prediction for RAW8 type
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DECOMP_PREDICT_0
Simple prediction
0x1 : DECOMP_PREDICT_1
Advanced prediction
End of enumeration elements list.
RGB_SWAP : Swapping RGB sequence
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : RGB_SWAP_0
MSB is R and LSB is B.
0x1 : RGB_SWAP_1
MSB is B and LSB is R (swapped).
End of enumeration elements list.
PARALLEL : Output bus width of CH0 is 32 bits. When this bit is set, the outer bus width of CSIS V3.3 is 32.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : PARALLEL_0
Normal output
0x1 : PARALLEL_1
32-bit data alignment
End of enumeration elements list.
DOUBLE_CMPNT : Double component per clock cycle in YUV422 formats
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DOUBLE_CMPNT_0
Single component per clock cycle (half pixel per clock cycle)
0x1 : DOUBLE_CMPNT_1
Double component per clock cycle (a pixel per clock cycle)
End of enumeration elements list.
RSVD8 : Reserved
bits : 13 - 23 (11 bit)
access : read-only
MEM_FULL_GAP : When the room of Image memory is lower than this, STOPREQ_EN is 0, then the image data cannot be blocked (Do not set this register lower than 4)
bits : 24 - 31 (8 bit)
access : read-write
ISP Image Resolution register of CH0
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HRESOL : Horizontal Image resolution
bits : 0 - 15 (16 bit)
access : read-write
VRESOL : Vertical Image resolution
bits : 16 - 31 (16 bit)
access : read-write
ISP SYNC register of CH0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VSYNC_EINTV : Interval between last Hsync falling and Vsync falling 12'h000 ~ 12'hFFF cycle of Pixel clock
bits : 0 - 11 (12 bit)
access : read-write
VSYNC_SINTV : Interval between Vsync rising and first Hsync rising 6'h00 ~ 6'h3F cycle of Pixel clock
bits : 12 - 17 (6 bit)
access : read-write
HSYNC_LINTV : Interval between Hsync falling and Hsync rising (Line interval) 6'h00 ~ 6'h3F cycle of Pixel clock
bits : 18 - 23 (6 bit)
access : read-write
RSVD9 : Reserved
bits : 24 - 31 (8 bit)
access : read-only
CSIS Clock gate Control
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WCLK_SRC : Pixel Clock Source
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : WCLK_SRC_0
PCLK
0x1 : WCLK_SRC_1
EXTCLK (WRAP_CLK)
End of enumeration elements list.
CLKGATE_EN : Bit 7, 6, 5 is reserved, bit 4 set for CH0.
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : CLKGATE_EN_0
Pixel clock is always alive.
0x1 : CLKGATE_EN_1
Pixel clock is alive during the interval of frame.
End of enumeration elements list.
RSVD4 : Reserved
bits : 8 - 15 (8 bit)
access : read-only
CLKGATE_TRAIL : 0 ~ 15 (1~16 Trailing clocks) [31:28], [27:24], [23:20] Reserved; [19:16] CH0
bits : 16 - 31 (16 bit)
access : read-write
Shadow Configuration register of CH0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VIRTUAL_CHANNEL : Current Virtual channel
bits : 0 - 1 (2 bit)
access : read-only
DataFormat : Current Image Data Format
bits : 2 - 7 (6 bit)
access : read-only
DECOMP_EN_SDW : Current Decompress enable
bits : 8 - 8 (1 bit)
access : read-only
DECOMP_PREDICT_SDW : Current Decompress prediction mode
bits : 9 - 9 (1 bit)
access : read-only
RGB_SWAP_SDW : Current RGB_SWAP
bits : 10 - 10 (1 bit)
access : read-only
PARALLEL_SDW : Current Parallel
bits : 11 - 11 (1 bit)
access : read-only
DOUBLE_CMPNT_SDW : Current Double component
bits : 12 - 12 (1 bit)
access : read-only
RSVD10 : Reserved
bits : 13 - 23 (11 bit)
access : read-only
NAMEMEM_FULL_GAP_SDW : Current MEM_FULL_GAP
bits : 24 - 31 (8 bit)
access : read-only
Shadow Resolution register of CH0
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HRESOL_SDW : Current Horizontal Image resolution
bits : 0 - 15 (16 bit)
access : read-only
VRESOL_SDW : Current Vertical Image resolution
bits : 16 - 31 (16 bit)
access : read-only
Shadow SYNC register of CH0
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VSYNC_EINTV_SDW : Current interval between last Hsync falling and Vsync falling
bits : 0 - 11 (12 bit)
access : read-only
VSYNC_SINTV_SDW : Current interval between Vsync rising and first Hsync rising
bits : 12 - 17 (6 bit)
access : read-only
HSYNC_LINTV_SDW : Current interval between Hsync falling and Hsync rising (Line interval)
bits : 18 - 23 (6 bit)
access : read-only
RSVD11 : Reserved
bits : 24 - 31 (8 bit)
access : read-only
Debug Control register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_CH_OUTPUT : [3] CH3 [2] CH2 [1] CH1 [0] CH0
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x1 : DBG_CH_OUTPUT_1
Force the channel output to 1
End of enumeration elements list.
DBG_BLK_EXC_FRAME : [7] CH3 [6] CH2 [5] CH1 [4] CH0
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : DBG_BLK_EXC_FRAME_0
Do not block the exceeded frame
0x1 : DBG_BLK_EXC_FRAME_1
Block the exceeded frame
End of enumeration elements list.
DBG_DONT_STOP_LAST_LINE : [11] CH3 [10] CH2 [9] CH1 [8] CH0
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : DBG_DONT_STOP_LAST_LINE_0
Can receive STOP_REQ from ISP any time
0x1 : DBG_DONT_STOP_LAST_LINE_1
Ignore STOP_REQ from ISP at the LAST_LINE
End of enumeration elements list.
DBG_FORCE_UPDATE : [15] CH3 [14] CH2 [13] CH1 [12] CH0
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : DBG_FORCE_UPDATE_0
Update shadow reg normally
0x1 : DBG_FORCE_UPDATE_1
Force to update shadow reg without waiting end of frame
End of enumeration elements list.
RSVD12 : Reserved
bits : 16 - 31 (16 bit)
access : read-only
Debug Interrupt Mask
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM_VSYNC_RISE : [3] CH3 [2] CH2 [1] CH1 [0] CH0
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : CAM_VSYNC_RISE_0
Disable (masked)
0x1 : CAM_VSYNC_RISE_1
Enable (unmasked)
End of enumeration elements list.
CAM_VSYNC_FALL : [7] CH3 [6] CH2 [5] CH1 [4] CH0
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : CAM_VSYNC_FALL_0
Disable (masked)
0x1 : CAM_VSYNC_FALL_1
Enable (unmasked)
End of enumeration elements list.
EARLY_FS : Early FS
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : EARLY_FS_0
Disable (masked)
0x1 : EARLY_FS_1
Enable (unmasked)
End of enumeration elements list.
EARLY_FE : Early FE
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : EARLY_FE_0
Disable (masked)
0x1 : EARLY_FE_1
Enable (unmasked)
End of enumeration elements list.
TRUNCATED_FRAME : Truncated Frame
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : TRUNCATED_FRAME_0
Disable (masked)
0x1 : TRUNCATED_FRAME_1
Enable (unmasked)
End of enumeration elements list.
ERR_FRAME_SIZE : Error Frame Size
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0 : ERR_FRAME_SIZE_0
Disable (masked)
0x1 : ERR_FRAME_SIZE_1
Enable (unmasked)
End of enumeration elements list.
DT_IGNORE : DT_IGNORE
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DT_IGNORE_0
Disable (masked)
0x1 : DT_IGNORE_1
Enable (unmasked)
End of enumeration elements list.
DT_NOT_SUPPORT : DT_NOT_SUPPORT
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DT_NOT_SUPPORT_0
Disable (masked)
0x1 : DT_NOT_SUPPORT_1
Enable (unmasked)
End of enumeration elements list.
RSVD13 : Reserved
bits : 26 - 31 (6 bit)
access : read-only
Debug Interrupt Mask
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM_VSYNC_RISE : The rising of vsync in the CAM I/F [3] CH3 [2] CH2 [1] CH1 [0] CH0
bits : 0 - 3 (4 bit)
access : read-write
CAM_VSYNC_FALL : The falling of vsync in the CAM I/F [7] CH3 [6] CH2 [5] CH1 [4] CH0
bits : 4 - 7 (4 bit)
access : read-write
EARLY_FS : Frame Start packet is received during transfer of image. [11] CH3 [10] CH2 [9] CH1 [8] CH0
bits : 8 - 11 (4 bit)
access : read-write
EARLY_FE : Frame End packet is received during transfer of image. [15] CH3 [14] CH2 [13] CH1 [12] CH0
bits : 12 - 15 (4 bit)
access : read-write
TRUNCATED_FRAME : Truncated frame is received. [19] CH3 [18] CH2 [17] CH1 [16] CH0
bits : 16 - 19 (4 bit)
access : read-write
ERR_FRAME_SIZE : The received frame is not matched with the configured. [23] CH3 [22] CH2 [21] CH1 [20] CH0
bits : 20 - 23 (4 bit)
access : read-write
DT_IGNORE : The data type of the received packet is ignored (NULL or BLANKING)
bits : 24 - 24 (1 bit)
access : read-write
DT_NOT_SUPPURT : The data type of the received packet is not supported (RGB444 or RGB555)
bits : 25 - 25 (1 bit)
access : read-write
RSVD14 : Reserved
bits : 26 - 31 (6 bit)
access : read-only
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