VERSION

CLKCTRL

TIMEOUT

CONFIG

ESCMODE

MDRESOL

MVPORCH

MHPORCH

MSYNC

SDRESOL

INTSRC

INTMSK

PKTHDR

STATUS

PAYLOAD

RXFIFO

FIFOTHLD

FIFOCTRL

MEMACCHR

MULTI_PKT

RGB_STATUS

PLLCTRL_1G

PLLCTRL

PLLCTRL1

PLLCTRL2

PLLTMR

PHYCTRL_B1

PHYCTRL_B2

PHYCTRL_M1

PHYCTRL_M2

PHYTIMING

PHYTIMING1

PHYTIMING2

SWRST

VERSION : Specifies the DSIM version information
bits : 0 - 31 (32 bit)
access : read-only

ESCPRESCALER : Specifies the escape clock prescaler value
bits : 0 - 15 (16 bit)
access : read-write

LANEESCCLKEN : Enables escape clock for D-phy lane LaneEscClkEn[0] = Clock lane LaneEscClkEn[1] = Data lane 0 LaneEscClkEn[2] = Data lane 1 LaneEscClkEn[3] = Reserved LaneEscClkEn[4] = Reserved
bits : 19 - 23 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ByteClkEn : Enables byte clock
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BYTECLKSRC : Selects byte clock source
bits : 25 - 26 (2 bit)
access : read-write

PLLBYPASS : Sets the PLLBypass signal connected to D-PHY module input for selecting clock source bit
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ESCCLKEN : Enables the escape clock generating prescaler
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPHY_SEL : D-PHY Select
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXREQUESTHSCLK : Specifies the HS clock request for HS transfer at clock lane (Turn on HS clock)
bits : 31 - 31 (1 bit)
access : read-write

LPDRTOUT : Specifies the timer for LP Rx mode timeout
bits : 0 - 15 (16 bit)
access : read-write

BTAOUT : Specifies the timer for BTA
bits : 16 - 23 (8 bit)
access : read-write

LANEEN : Enables the lane
bits : 0 - 4 (5 bit)
access : read-write

NUMOFDATLANE : Sets the data lane number
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SUBPIXFORMAT : Specifies pixel stream format for main display
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MAINPIXFORMAT : Specifies pixel stream format for main display
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SUBVC : Specifies virtual channel number for sub display
bits : 16 - 17 (2 bit)
access : read-write

MAINVC : Specifies virtual channel number for main display
bits : 18 - 19 (2 bit)
access : read-write

HSADISABLEMODE : Specifies HSA disable mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HBPDISABLEMODE : Specifies HBP disable mode
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HFPDISABLEMODE : Specifies HFP disable mode
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSEDISABLEMODE : In Vsync pulse and Vporch area, MIPI DSI master transfers only Hsync start packet to MIPI DSI slave at MIPI DSI spec 1
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTOMODE : Specifies auto vertical count mode In Video mode, the vertical line transition uses line counter configured by VSA, VBP, and Vertical resolution
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VIDEOMODE : Specifies display configuration
bits : 25 - 25 (1 bit)
access : read-write

BURSTMODE : Selects Burst mode in Video mode In Non-burst mode, RGB data area is filled with RGB data and Null packets, according to input bandwidth of RGB interface
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYNCINFORM : Selects Sync Pulse or Event mode in Video mode In command mode, this bit is ignored.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EOT_R03 : Disables EoT packet in HS mode.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFLUSH_VS : Auto flush of MD FIFO using Vsync pulse
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKLANE_STOP_START : PHY clock lane On / Off for ESD
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NON_CONTINUOUS_CLOCK_LANE : Non-continuous clock mode
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXULPSCLKEXIT : Specifies ULPS exit request for clock lane. Manually clears after ULPS exit.
bits : 0 - 0 (1 bit)
access : read-write

TXULPSCLK : Specifies ULPS request for clock lane. Manually clears after ULPS exit.
bits : 1 - 1 (1 bit)
access : read-write

TXULPSEXIT : Specifies ULPS exit request for data lane. Manually clears after ULPS exit.
bits : 2 - 2 (1 bit)
access : read-write

TXULPSDAT : Specifies ULPS request for data lane. Manually clears after ULPS exit.
bits : 3 - 3 (1 bit)
access : read-write

TXTRIGGERRST : Specifies remote reset trigger function
bits : 4 - 4 (1 bit)
access : read-write

TXLPDT : Specifies data transmission in LP mode (all data transfer in LPDT)
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMDLPDT : Specifies LPDT transfers command in SFR FIFO
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FORCEBTA : Forces Bus Turn Around 1 = Sends the protocol layer request to D-PHY
bits : 16 - 16 (1 bit)
access : read-write

FORCESTOPSTATE : Forces Stopstate for D-PHY
bits : 20 - 20 (1 bit)
access : read-write

STOPSTATE_CNT : After transmitting read packet or write "set_tear_on" command, BTA requests to D-phy automatically
bits : 21 - 31 (11 bit)
access : read-write

MAINHRESOL : Specifies Horizontal resolution (1 ~ 2047)
bits : 0 - 11 (12 bit)
access : read-write

MainVResol : Specifies Vertical resolution (1 ~ 2047)
bits : 16 - 27 (12 bit)
access : read-write

MAINSTANDBY : Specifies standby for receiving DISPCON output in Command mode after setting all configuration
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MAINVBP : Specifies vertical back porch width for Video mode (line count)
bits : 0 - 10 (11 bit)
access : read-write

STABLEVFP : Specifies the number of horizontal lines, where command packet transmission is not allowed after end of active region
bits : 16 - 26 (11 bit)
access : read-write

CMDALLOW : Specifies the number of horizontal lines, where command packet transmission is allowed after Stable VFP period
bits : 28 - 31 (4 bit)
access : read-write

MAINHBP : Specifies the horizontal back porch width for Video mode
bits : 0 - 15 (16 bit)
access : read-write

MAINHFP : Specifies the horizontal front porch width for Video mode
bits : 16 - 31 (16 bit)
access : read-write

MAINHSA : Specifies the horizontal sync pulse width for Video mode
bits : 0 - 15 (16 bit)
access : read-write

MAINVSA : Specifies the vertical sync pulse width for Video mode (Line count)
bits : 22 - 31 (10 bit)
access : read-write

SUBHRESOL : Specifies the Horizontal resolution (1 ~ 1024)
bits : 0 - 10 (11 bit)
access : read-write

SUBVRESOL : Specifies the Vertical resolution (1 ~ 1024)
bits : 16 - 26 (11 bit)
access : read-write

SUBSTANDBY : Specifies standby for receiving DISPCON output in Command mode after setting all configuration
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ERRCONTENTLP1 : Specifies the LP1 Contention Error (only lane0, because BTA occurs at lane0 only)
bits : 0 - 0 (1 bit)
access : read-write

ERRCONTENTLP0 : Specifies the LP0 Contention Error (only lane0, because BTA occurs at lane0 only)
bits : 1 - 1 (1 bit)
access : read-write

ERRCONTROL0 : Controls Error lane0. For more information, refer to standard D-PHY specification.
bits : 2 - 2 (1 bit)
access : read-write

ERRCONTROL1 : Controls Error lane1. For more information, refer to standard D-PHY specification.
bits : 3 - 3 (1 bit)
access : read-write

ERRSYNC0 : Specifies the LPDT Sync Error lane0. For more information, refer to standard D-PHY specification.
bits : 6 - 6 (1 bit)
access : read-write

ERRSYNC1 : Specifies the LPDT Sync Error lane1. For more information, refer to standard D-PHY specification.
bits : 7 - 7 (1 bit)
access : read-write

ERRESC0 : Specifies the escape mode entry error lane 0
bits : 10 - 10 (1 bit)
access : read-write

ERRESC1 : Specifies the escape mode entry error lane 1
bits : 11 - 11 (1 bit)
access : read-write

ERRRXCRC : Specifies the CRC error in LPDR
bits : 14 - 14 (1 bit)
access : read-write

ERRRXECC : Specifies the ECC multi bit error in LPDR
bits : 15 - 15 (1 bit)
access : read-write

RXACK : Receives ACK Rx trigger
bits : 16 - 16 (1 bit)
access : read-write

RXTE : Receives TE Rx trigger
bits : 17 - 17 (1 bit)
access : read-write

RXDATDONE : Completes receiving data
bits : 18 - 18 (1 bit)
access : read-write

TATOUT : Turns around Acknowledge Timeout. See time out register (0x10).
bits : 20 - 20 (1 bit)
access : read-write

LPDRTOUT : Specifies the LP Rx timeout. See time out register (0x10).
bits : 21 - 21 (1 bit)
access : read-write

FRAMEDONE : Indicates when MIPI DSIM transfers the whole image frame
bits : 24 - 24 (1 bit)
access : read-write

BUSTURNOVER : Indicates when bus grant turns over from DSI slave to DSI master.
bits : 25 - 25 (1 bit)
access : read-write

SYNCOVERRIDE : Indicates that other DSI command transfer have overridden sync timing.
bits : 27 - 27 (1 bit)
access : read-write

SFRPHFIFOEMPTY : Specifies the SFR Packet Header FIFO emtpy
bits : 28 - 28 (1 bit)
access : read-write

SFRPLFIFOEMPTY : Specifies the SFR payload FIFO empty.
bits : 29 - 29 (1 bit)
access : read-write

SWRSTRELEASE : Releases the software reset.
bits : 30 - 30 (1 bit)
access : read-write

PLLSTABLE : Indicates that D-phy PLL is stable.
bits : 31 - 31 (1 bit)
access : read-write

MSKCONTENTLP1 : Specifies LP1 contention error. For more information, refer to standard D-PHY specification.
bits : 0 - 0 (1 bit)
access : read-write

MSKCONTENTLP0 : Specifies LP0 contention error. For more information, refer to standard D-PHY specification.
bits : 1 - 1 (1 bit)
access : read-write

MSKCONTROL0 : Controls error in lane0. For more information, refer to standard D-PHY specification.
bits : 2 - 2 (1 bit)
access : read-write

MSKCONTROL1 : Controls error in lane1. For more information, refer to standard D-PHY specification.
bits : 3 - 3 (1 bit)
access : read-write

MSKSYNC0 : Specifies LPDT sync error in lane0. For more information, refer to standard D-PHY specification.
bits : 6 - 6 (1 bit)
access : read-write

MSKSYNC1 : Specifies LPDT sync error in lane1. For more information, refer to standard D-PHY specification.
bits : 7 - 7 (1 bit)
access : read-write

MSKESC0 : Specifies escape mode entry error in lane0
bits : 10 - 10 (1 bit)
access : read-write

MSKESC1 : Specifies escape mode entry error in lane1
bits : 11 - 11 (1 bit)
access : read-write

MSKRXCRC : Specifies CRC error in LPDR
bits : 14 - 14 (1 bit)
access : read-write

MSKRXECC : Specifies ECC multibit error in LPDR
bits : 15 - 15 (1 bit)
access : read-write

MSKRXACK : Specifies receipt of ACK Rx trigger
bits : 16 - 16 (1 bit)
access : read-write

MSKRXTE : Specifies receipt of TE Rx trigger
bits : 17 - 17 (1 bit)
access : read-write

MSKRXDATDONE : Specifies completion of data receiving
bits : 18 - 18 (1 bit)
access : read-write

MSKTATOUT : Specifies turnaround acknowledge timeout. See time out register (0x10)
bits : 20 - 20 (1 bit)
access : read-write

MSKLPDRTOUT : Specifies LP Rx timeout. See time out register (0x10).
bits : 21 - 21 (1 bit)
access : read-write

MSKFRAMEDONE : Indicates when MIPI DSIM transfers whole image frame.
bits : 24 - 24 (1 bit)
access : read-write

MSKBUSTURNOVER : Indicates when bus grant turns over from DSI slave to DSI master.
bits : 25 - 25 (1 bit)
access : read-write

MSKSYNCOVERRIDE : Indicates that other DSI command transfer have overridden sync timing.
bits : 27 - 27 (1 bit)
access : read-write

MSKSFRPHFIFOEMPTY : Interrupt Mask for SFR packet header FIFO empty
bits : 28 - 28 (1 bit)
access : read-write

MSKSFRPLFIFOEMPTY : Empties SFR payload FIFO.
bits : 29 - 29 (1 bit)
access : read-write

MSKSWRSTRELEASE : Releases software reset.
bits : 30 - 30 (1 bit)
access : read-write

MSKPLLSTABLE : Indicates that D-PHY PLL is stable.
bits : 31 - 31 (1 bit)
access : read-write

PACKETHEADER : Writes the packet header of Tx packet
bits : 0 - 23 (24 bit)
access : read-write

STOPSTATEDAT : Specifies the stop state indicator at data lane StopstateDat[0]: Data lane 0 StopstateDat[1]: Data lane 1 StopstateDat[2]: Reserved StopstateDat[3]: Reserved
bits : 0 - 3 (4 bit)
access : read-only

ULPSDAT : Specifies the ULPS indicator at data lanes UlpsDat[0]: Data lane 0 UlpsDat[1]: Data lane 1 UlpsDat[2]: Reserved UlpsDat[3]: Reserved
bits : 4 - 7 (4 bit)
access : read-only

Enumeration:

End of enumeration elements list.

STOPSTATECLK : Specifies the stop state indicator at clock lane
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ULPSCLK : Specifies the ULPS indicator at clock lane
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXREADYHSCLK : Specifies the HS clock ready at clock lane
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DIRECTION : Specifies the data direction indicator
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SWRSTRLS : Specifies the software reset status
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PLLSTABLE : D-PHY PLL generates stable byteclk.
bits : 31 - 31 (1 bit)
access : read-only

PAYLOAD : Writes the Payload of Tx packet
bits : 0 - 31 (32 bit)
access : read-write

RXFIFO : In the Rx mode, you can read Rx data through this register
bits : 0 - 31 (32 bit)
access : read-only

WFULLLEVELSFR : Almost full level of SFR payload FIFO
bits : 0 - 8 (9 bit)
access : read-write

NINITMAIN : MD FIFO write point initialize
bits : 0 - 0 (1 bit)
access : read-write

NINITSUB : SD FIFO write point initialize
bits : 1 - 1 (1 bit)
access : read-write

NLNITL80 : S-i80 FIFO write point initialize
bits : 2 - 2 (1 bit)
access : read-write

NINITSFR : SFR FIFO write point initialize
bits : 3 - 3 (1 bit)
access : read-write

NINITRX : MD FIFO read point initialize
bits : 4 - 4 (1 bit)
access : read-write

EMPTYLMAIN : Main display payload FIFO empty
bits : 8 - 8 (1 bit)
access : read-only

FULLLMAIN : Main display payload FIFO full
bits : 9 - 9 (1 bit)
access : read-only

EMPTYHMAIN : Main display packet header FIFO empty
bits : 10 - 10 (1 bit)
access : read-only

FULLHMAIN : Main display packet header FIFO full
bits : 11 - 11 (1 bit)
access : read-only

EMPTYLSUB : Sub display payload FIFO empty
bits : 12 - 12 (1 bit)
access : read-only

FULLLSUB : Sub display payload FIFO full
bits : 13 - 13 (1 bit)
access : read-only

EMPTYHSUB : Sub display packet header FIFO empty
bits : 14 - 14 (1 bit)
access : read-only

FULLHSUB : Sub display packet header FIFO full
bits : 15 - 15 (1 bit)
access : read-only

EMPTYLI80 : S-i80 payload FIFO empty
bits : 16 - 16 (1 bit)
access : read-only

FULLLI80 : S-i80 payload FIFO full
bits : 17 - 17 (1 bit)
access : read-only

EMPTYHI80 : S-i80 packet header FIFO empty
bits : 18 - 18 (1 bit)
access : read-only

FULLHI80 : S-i80 packet header FIFO full
bits : 19 - 19 (1 bit)
access : read-only

EMPTYLSFR : SFR payload FIFO empty
bits : 20 - 20 (1 bit)
access : read-only

FULLLSFR : SFR payload FIFO full
bits : 21 - 21 (1 bit)
access : read-only

EMPTYHSFR : SFR packet header FIFO empty
bits : 22 - 22 (1 bit)
access : read-only

FullHSfr : SFR packet header FIFO full
bits : 23 - 23 (1 bit)
access : read-only

EMPTYRX : Rx FIFO empty
bits : 24 - 24 (1 bit)
access : read-only

FULLRX : Rx FIFO full
bits : 25 - 25 (1 bit)
access : read-only

EMAA_MD : Main display FIFO memory A port margin adjustment
bits : 0 - 2 (3 bit)
access : read-write

EMAB_MD : Main display FIFO memory B port margin adjustment
bits : 3 - 5 (3 bit)
access : read-write

RETN_MD : Main display FIFO memory Retention
bits : 6 - 6 (1 bit)
access : read-write

PGEN_MD : Main display FIFO memory power gating
bits : 7 - 7 (1 bit)
access : read-write

EMAA_SD : Sub display FIFO memory A port margin adjustment
bits : 8 - 10 (3 bit)
access : read-write

EMAB_SD : Sub display FIFO memory B port margin adjustment
bits : 11 - 13 (3 bit)
access : read-write

RETN_SD : Sub display FIFO memory Retention
bits : 14 - 14 (1 bit)
access : read-write

PGEN_SD : Sub display FIFO memory power gating
bits : 15 - 15 (1 bit)
access : read-write

MULTI_PKT_CNT_REF : Specifies the number of packets on single transmission
bits : 0 - 15 (16 bit)
access : read-write

PKT_SEND_CNT_REF : Specifies the command packet(s) send point indicator
bits : 16 - 27 (12 bit)
access : read-write

PKT_GO_RDY : Specifies the send command packet(s) on this frame VFP
bits : 28 - 28 (1 bit)
access : read-write

PKT_GO_EN : Specifies the send command packet(s) per frame enable . Packet go can transfer by only HS mode.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MULTI_PKT_EN : Specifies the send multi command packets on single transmission
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RGBSTATE : Specifies the RGB packetize FSM status
bits : 0 - 12 (13 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CMDMODE_INSEL : Specifies the command mode input selection
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PRPRCTLCLK : 1 Gbps D-PHY PLL Ths-prepare driving time control
bits : 0 - 2 (3 bit)
access : read-write

PREPRCTL : 1 Gbps D-PHY PLL Tclk-prepare and Ths-prepare driving control.
bits : 4 - 6 (3 bit)
access : read-write

FREQ_BAND : 1 Gbps D-PHY Timing control for D-PHY global operation timing.
bits : 8 - 11 (4 bit)
access : read-write

HSZEROCTL : 1 Gbps D-PHY HS-Zero driving timing control.
bits : 12 - 15 (4 bit)
access : read-write

PMS : Specifies the PLL PMS value
bits : 1 - 19 (19 bit)
access : read-write

PLLEN : Enables PLL
bits : 23 - 23 (1 bit)
access : read-write

DPDNSWAP_DAT : Swaps Dp / Dn channel of Data lanes. If this bit is set, Dp and Dn channel swap each other.
bits : 24 - 24 (1 bit)
access : read-write

DPDNSWAP_CLK : Swaps Dp / Dn channel of clock lane. If this bit is set, Dp and Dn channel swap each other.
bits : 25 - 25 (1 bit)
access : read-write

M_PLLCTL0 : M_PLLCTL[31:0] to D-PHY
bits : 0 - 31 (32 bit)
access : read-write

M_PLLCTL1 : M_PLLCTL[39:32] to D-PHY
bits : 0 - 7 (8 bit)
access : read-write

PLLTIMER : Specifies the PLL Timer for stability of the generated clock (System clock cycle base)
bits : 0 - 31 (32 bit)
access : read-write

B_DPHYCTL0 : B_DPHYCTL[31:0] to D-PHY
bits : 0 - 31 (32 bit)
access : read-write

B_DPHYCTL1 : B_DPHYCTL[63:32] to D-PHY
bits : 0 - 31 (32 bit)
access : read-write

M_DPHYCTL0 : M_DPHYCTL[31:0] to D-PHY
bits : 0 - 31 (32 bit)
access : read-write

M_DPHYCTL1 : M_DPHYCTL[63:32] to D-PHY
bits : 0 - 31 (32 bit)
access : read-write

M_THSEXITCTL : M_THSEXITCTL[7:0] to D-PHY
bits : 0 - 7 (8 bit)
access : read-write

M_TLPXCTL : M_TLPXCTL[7:0] to D-PHY
bits : 8 - 15 (8 bit)
access : read-write

M_TCLKTRAILCTL : M_TCLKTRAILCTL[7:0] to D-PHY
bits : 0 - 7 (8 bit)
access : read-write

M_TCLKPOSTCTL : M_TCLKPOSTCTL[7:0] to D-PHY
bits : 8 - 15 (8 bit)
access : read-write

M_TCLKZEROCTL : M_TCLKZEROCTL[7:0] to D-PHY
bits : 16 - 23 (8 bit)
access : read-write

M_TCLKPRPRCTL : M_TCLKPRPRCTL[7:0] to D-PHY
bits : 24 - 31 (8 bit)
access : read-write

M_THSTRAILCTL : M_THSTRAILCTL[7:0] to D-PHY
bits : 0 - 7 (8 bit)
access : read-write

M_THSZEROCTL : M_THSZEROCTL[7:0] to D-PHY
bits : 8 - 15 (8 bit)
access : read-write

M_THSPRPRCTL : M_THSPRPRCTL[7:0] to D-PHY
bits : 16 - 23 (8 bit)
access : read-write

SWRST : Specifies the software reset (High active)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FUNCRST : Specifies the software reset (High active)
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.