Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC00 byte (0x0)
mem_usage : registers
protection : not protected
SNVS_HP Lock Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MC_SL : Monotonic Counter Soft Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : MC_SL_0
Write access (increment) is allowed
0x1 : MC_SL_1
Write access (increment) is not allowed
End of enumeration elements list.
GPR_SL : General Purpose Register Soft Lock When set, prevents any writes to the GPR
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : GPR_SL_0
Write access is allowed
0x1 : GPR_SL_1
Write access is not allowed
End of enumeration elements list.
SNVS_HP Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTN : Value of the BTN input
bits : 6 - 6 (1 bit)
access : read-only
BI : Button Interrupt. Signal ipi_snvs_btn_int_b was asserted.
bits : 7 - 7 (1 bit)
access : read-write
SNVS_HP Real Time Counter MSB Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC : HP Real Time Counter Most significant 32 bits
bits : 0 - 31 (32 bit)
access : read-write
SNVS_HP Real Time Counter LSB Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC : HP Real Time Counter Least significant 32 bits
bits : 0 - 31 (32 bit)
access : read-write
SNVS_HP Time Alarm MSB Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPTA : HP Time Alarm Most significant 15 bits
bits : 0 - 14 (15 bit)
access : read-write
SNVS_HP Time Alarm LSB Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPTA : HP Time Alarm Least significant bits
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP Lock Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MC_HL : Monotonic Counter Hard Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : MC_HL_0
Write access (increment) is allowed.
0x1 : MC_HL_1
Write access (increment) is not allowed.
End of enumeration elements list.
GPR_HL : General Purpose Register Hard Lock When set, prevents any writes to the GPR
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : GPR_HL_0
Write access is allowed.
0x1 : GPR_HL_1
Write access is not allowed.
End of enumeration elements list.
SNVS_LP Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MC_ENV : Monotonic Counter Enable and Valid When set, the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : MC_ENV_0
MC is disabled or invalid.
0x1 : MC_ENV_1
MC is enabled and valid.
End of enumeration elements list.
DP_EN : Dumb PMIC Enabled When set, software can control the system power
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DP_EN_0
Smart PMIC enabled.
0x1 : DP_EN_1
Dumb PMIC enabled.
End of enumeration elements list.
TOP : Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : TOP_0
Leave system power on.
0x1 : TOP_1
Turn off system power.
End of enumeration elements list.
PWR_GLITCH_EN : By default the detection of a power glitch does not cause the pmic_en_b signal to be asserted
bits : 7 - 7 (1 bit)
access : read-write
BTN_PRESS_TIME : Button press time out values for PMIC Logic
bits : 16 - 17 (2 bit)
access : read-write
DEBOUNCE : This field configures the amount of debounce time for the BTN input signal
bits : 18 - 19 (2 bit)
access : read-write
ON_TIME : The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoCpower
bits : 20 - 21 (2 bit)
access : read-write
PK_EN : PMIC On Request Enable
bits : 22 - 22 (1 bit)
access : read-write
PK_OVERRIDE : PMIC On Request Override
bits : 23 - 23 (1 bit)
access : read-write
SNVS_HP Command Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LP_SWR : LP Software Reset When set, it resets the SNVS_LP section
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
0 : LP_SWR_0
No Action
0x1 : LP_SWR_1
Reset LP section
End of enumeration elements list.
LP_SWR_DIS : LP Software Reset Disable When set, disables the LP software reset
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : LP_SWR_DIS_0
LP software reset is enabled
0x1 : LP_SWR_DIS_1
LP software reset is disabled
End of enumeration elements list.
NPSWA_EN : Non-Privileged Software Access Enable When set, allows non-privileged software to access all SNVS registers, including those that are privileged software read/write access only
bits : 31 - 31 (1 bit)
access : read-write
SNVS_LP Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCR : Monotonic Counter Rollover.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : MCR_0
MC has not reached its maximum value.
0x1 : MCR_1
MC has reached its maximum value.
End of enumeration elements list.
EO : Emergency Off This bit is set when a power off is requested.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : EO_0
Emergency off was not detected.
0x1 : EO_1
Emergency off was detected.
End of enumeration elements list.
SPO : Set Power Off The SPO bit is set when the set_pwr_off_irq interrupt is triggered, which happens when software writes a 1 to the TOP bit in the LPCR or when the power button is pressed longer than the configured debounce time
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SPO_0
Emergency Off was not detected.
0x1 : SPO_1
Emergency Off was detected..
End of enumeration elements list.
SNVS_LP Secure Monotonic Counter MSB Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MON_COUNTER : Monotonic Counter Most Significant 16 Bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR register is detected
bits : 0 - 15 (16 bit)
access : read-write
MC_ERA_BITS : Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses.
bits : 16 - 31 (16 bit)
access : read-write
SNVS_LP Secure Monotonic Counter LSB Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MON_COUNTER : Monotonic Counter bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR Register is detected
bits : 0 - 31 (32 bit)
access : read-write
SNVS_LP General Purpose Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR : General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
bits : 0 - 31 (32 bit)
access : read-write
SNVS_HP Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC_EN : HP Real Time Counter Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RTC_EN_0
RTC is disabled
0x1 : RTC_EN_1
RTC is enabled
End of enumeration elements list.
HPTA_EN : HP Time Alarm Enable When set, the time alarm interrupt is generated if the value in the HP Time Alarm Registers is equal to the value of the HP Real Time Counter
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : HPTA_EN_0
HP Time Alarm Interrupt is disabled
0x1 : HPTA_EN_1
HP Time Alarm Interrupt is enabled
End of enumeration elements list.
PI_EN : HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP Real Time Counter is enabled
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PI_EN_0
HP Periodic Interrupt is disabled
0x1 : PI_EN_1
HP Periodic Interrupt is enabled
End of enumeration elements list.
PI_FREQ : Periodic Interrupt Frequency Defines frequency of the periodic interrupt
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : PI_FREQ_0
- bit 0 of the RTC is selected as a source of the periodic interrupt
0x1 : PI_FREQ_1
- bit 1 of the RTC is selected as a source of the periodic interrupt
0x2 : PI_FREQ_2
- bit 2 of the RTC is selected as a source of the periodic interrupt
0x3 : PI_FREQ_3
- bit 3 of the RTC is selected as a source of the periodic interrupt
0x4 : PI_FREQ_4
- bit 4 of the RTC is selected as a source of the periodic interrupt
0x5 : PI_FREQ_5
- bit 5 of the RTC is selected as a source of the periodic interrupt
0x6 : PI_FREQ_6
- bit 6 of the RTC is selected as a source of the periodic interrupt
0x7 : PI_FREQ_7
- bit 7 of the RTC is selected as a source of the periodic interrupt
0x8 : PI_FREQ_8
- bit 8 of the RTC is selected as a source of the periodic interrupt
0x9 : PI_FREQ_9
- bit 9 of the RTC is selected as a source of the periodic interrupt
0xA : PI_FREQ_10
- bit 10 of the RTC is selected as a source of the periodic interrupt
0xB : PI_FREQ_11
- bit 11 of the RTC is selected as a source of the periodic interrupt
0xC : PI_FREQ_12
- bit 12 of the RTC is selected as a source of the periodic interrupt
0xD : PI_FREQ_13
- bit 13 of the RTC is selected as a source of the periodic interrupt
0xE : PI_FREQ_14
- bit 14 of the RTC is selected as a source of the periodic interrupt
0xF : PI_FREQ_15
- bit 15 of the RTC is selected as a source of the periodic interrupt
End of enumeration elements list.
HPCALB_EN : HP Real Time Counter Calibration Enabled Indicates that the time calibration mechanism is enabled.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : HPCALB_EN_0
HP Timer calibration disabled
0x1 : HPCALB_EN_1
HP Timer calibration enabled
End of enumeration elements list.
HPCALB_VAL : HP Calibration Value Defines signed calibration value for the HP Real Time Counter
bits : 10 - 14 (5 bit)
access : read-write
Enumeration:
0 : HPCALB_VAL_0
+0 counts per each 32768 ticks of the counter
0x1 : HPCALB_VAL_1
+1 counts per each 32768 ticks of the counter
0x2 : HPCALB_VAL_2
+2 counts per each 32768 ticks of the counter
0xF : HPCALB_VAL_15
+15 counts per each 32768 ticks of the counter
0x10 : HPCALB_VAL_16
-16 counts per each 32768 ticks of the counter
0x11 : HPCALB_VAL_17
-15 counts per each 32768 ticks of the counter
0x1E : HPCALB_VAL_30
-2 counts per each 32768 ticks of the counter
0x1F : HPCALB_VAL_31
-1 counts per each 32768 ticks of the counter
End of enumeration elements list.
BTN_CONFIG : Button Configuration
bits : 24 - 26 (3 bit)
access : read-write
BTN_MASK : Button interrupt mask
bits : 27 - 27 (1 bit)
access : read-write
SNVS_HP Version ID Register 1
address_offset : 0xBF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINOR_REV : SNVS block minor version number
bits : 0 - 7 (8 bit)
access : read-only
MAJOR_REV : SNVS block major version number
bits : 8 - 15 (8 bit)
access : read-only
IP_ID : SNVS block ID
bits : 16 - 31 (16 bit)
access : read-only
SNVS_HP Version ID Register 2
address_offset : 0xBFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CONFIG_OPT : SNVS Configuration Option
bits : 0 - 7 (8 bit)
access : read-only
ECO_REV : SNVS ECO Revision
bits : 8 - 15 (8 bit)
access : read-only
INTG_OPT : SNVS Integration Option
bits : 16 - 23 (8 bit)
access : read-only
IP_ERA : Era of the IP design
bits : 24 - 31 (8 bit)
access : read-only
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