Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1004 byte (0x0)
mem_usage : registers
protection : not protected
SRC Reset Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK_TEMPSENSE_RESET : Mask tempsense_reset source
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x5 : MASK_TEMPSENSE_RESET_5
tempsense_reset is masked
0xA : MASK_TEMPSENSE_RESET_10
tempsense_reset is not masked
End of enumeration elements list.
DOMAIN0 : Domain0 assignment control. Effective when dom_en is set to 1.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN0_0
This register is not assigned to domain0. The master from domain3 cannot write to this register.
0x1 : DOMAIN0_1
This register is assigned to domain0. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN1 : Domain1 assignment control. Effective when dom_en is set to 1.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN1_0
This register is not assigned to domain1. The master from domain3 cannot write to this register.
0x1 : DOMAIN1_1
This register is assigned to domain1. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN2 : Domain2 assignment control. Effective when dom_en is set to 1.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN2_0
This register is not assigned to domain2. The master from domain3 cannot write to this register.
0x1 : DOMAIN2_1
This register is assigned to domain2. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN3 : Domain3 assignment control. Effective when dom_en is set to 1.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN3_0
This register is not assigned to domain3. The master from domain3 cannot write to this register.
0x1 : DOMAIN3_1
This register is assigned to domain3. The master from domain3 can write to this register
End of enumeration elements list.
LOCK : Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LOCK_0
[31] and [27:24] bits can be modified
0x1 : LOCK_1
[31] and [27:24] bits cannot be modified
End of enumeration elements list.
DOM_EN : Domain Control enable for this register
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DOM_EN_0
Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
0x1 : DOM_EN_1
Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
End of enumeration elements list.
SRC DDR Controller Reset Control Register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DDRC_PRST : DDR Controller preset and DDR PHY reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DDRC_PRST_0
De-ssert DDR Controller preset and DDR PHY reset reset
0x1 : DDRC_PRST_1
Assert DDR Controller preset and DDR PHY reset
End of enumeration elements list.
DDRC_CORE_RST : DDR Controller core_ddrc_rstn and aresetn
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DDRC_CORE_RST_0
De-ssert DDR controller aresetn and core_ddrc_rstn
0x1 : DDRC_CORE_RST_1
Assert DDR Controller preset and DDR PHY reset
End of enumeration elements list.
DOMAIN0 : Domain0 assignment control. Effective when dom_en is set to 1.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN0_0
This register is not assigned to domain0. The master from domain3 cannot write to this register.
0x1 : DOMAIN0_1
This register is assigned to domain0. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN1 : Domain1 assignment control. Effective when dom_en is set to 1.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN1_0
This register is not assigned to domain1. The master from domain3 cannot write to this register.
0x1 : DOMAIN1_1
This register is assigned to domain1. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN2 : Domain2 assignment control. Effective when dom_en is set to 1.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN2_0
This register is not assigned to domain2. The master from domain3 cannot write to this register.
0x1 : DOMAIN2_1
This register is assigned to domain2. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN3 : Domain3 assignment control. Effective when dom_en is set to 1.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN3_0
This register is not assigned to domain3. The master from domain3 cannot write to this register.
0x1 : DOMAIN3_1
This register is assigned to domain3. The master from domain3 can write to this register
End of enumeration elements list.
LOCK : Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LOCK_0
[31] and [27:24] bits can be modified
0x1 : LOCK_1
[31] and [27:24] bits cannot be modified
End of enumeration elements list.
DOM_EN : Domain Control enable for this register
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DOM_EN_0
Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
0x1 : DOM_EN_1
Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
End of enumeration elements list.
EIM Reset Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIM_RST : EIM reset is needed in order to reconfigure the eim chip select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : EIM_RST_0
assert EIM controller reset
0x1 : EIM_RST_1
do not assert EIM controller reset
End of enumeration elements list.
DOMAIN0 : Domain0 assignment control. Effective when dom_en is set to 1.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN0_0
This register is not assigned to domain0. The master from domain3 cannot write to this register.
0x1 : DOMAIN0_1
This register is assigned to domain0. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN1 : Domain1 assignment control. Effective when dom_en is set to 1.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN1_0
This register is not assigned to domain1. The master from domain3 cannot write to this register.
0x1 : DOMAIN1_1
This register is assigned to domain1. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN2 : Domain2 assignment control. Effective when dom_en is set to 1.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN2_0
This register is not assigned to domain2. The master from domain3 cannot write to this register.
0x1 : DOMAIN2_1
This register is assigned to domain2. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN3 : Domain3 assignment control. Effective when dom_en is set to 1.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN3_0
This register is not assigned to domain3. The master from domain3 cannot write to this register.
0x1 : DOMAIN3_1
This register is assigned to domain3. The master from domain3 can write to this register
End of enumeration elements list.
LOCK : Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LOCK_0
[31] and [27:24] bits can be modified
0x1 : LOCK_1
[31] and [27:24] bits cannot be modified
End of enumeration elements list.
DOM_EN : Domain Control enable for this register
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DOM_EN_0
Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
0x1 : DOM_EN_1
Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
End of enumeration elements list.
HSIC PHY Reset Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSICPHY_PORT_RST : HSIC PHY Port Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : HSICPHY_PORT_RST_0
Do not assert HSIC PHY Port Reset
0x1 : HSICPHY_PORT_RST_1
Assert HSIC PHY Port Reset
End of enumeration elements list.
DOMAIN0 : Domain0 assignment control. Effective when dom_en is set to 1.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN0_0
This register is not assigned to domain0. The master from domain3 cannot write to this register.
0x1 : DOMAIN0_1
This register is assigned to domain0. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN1 : Domain1 assignment control. Effective when dom_en is set to 1.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN1_0
This register is not assigned to domain1. The master from domain3 cannot write to this register.
0x1 : DOMAIN1_1
This register is assigned to domain1. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN2 : Domain2 assignment control. Effective when dom_en is set to 1.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN2_0
This register is not assigned to domain2. The master from domain3 cannot write to this register.
0x1 : DOMAIN2_1
This register is assigned to domain2. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN3 : Domain3 assignment control. Effective when dom_en is set to 1.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN3_0
This register is not assigned to domain3. The master from domain3 cannot write to this register.
0x1 : DOMAIN3_1
This register is assigned to domain3. The master from domain3 can write to this register
End of enumeration elements list.
LOCK : Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LOCK_0
[31] and [27:24] bits can be modified
0x1 : LOCK_1
[31] and [27:24] bits cannot be modified
End of enumeration elements list.
DOM_EN : Domain Control enable for this register
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DOM_EN_0
Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
0x1 : DOM_EN_1
Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
End of enumeration elements list.
USB OTG PHY1 Reset Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBPHY1_POR : USB OTG PHY 1 PORThis is a self clearing bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : USBPHY1_POR_0
De-assert USB OTG PHY1 reset
0x1 : USBPHY1_POR_1
Assert USB OTG PHY1 reset
End of enumeration elements list.
USBPHY1_PORT_RST : USB OTG PHY1 Port Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : USBPHY1_PORT_RST_0
Do not assert USB OTG PHY1 Port Reset
0x1 : USBPHY1_PORT_RST_1
Assert USB OTG PHY1 Port Reset
End of enumeration elements list.
DOMAIN0 : Domain0 assignment control. Effective when dom_en is set to 1.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN0_0
This register is not assigned to domain0. The master from domain3 cannot write to this register.
0x1 : DOMAIN0_1
This register is assigned to domain0. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN1 : Domain1 assignment control. Effective when dom_en is set to 1.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN1_0
This register is not assigned to domain1. The master from domain3 cannot write to this register.
0x1 : DOMAIN1_1
This register is assigned to domain1. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN2 : Domain2 assignment control. Effective when dom_en is set to 1.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN2_0
This register is not assigned to domain2. The master from domain3 cannot write to this register.
0x1 : DOMAIN2_1
This register is assigned to domain2. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN3 : Domain3 assignment control. Effective when dom_en is set to 1.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN3_0
This register is not assigned to domain3. The master from domain3 cannot write to this register.
0x1 : DOMAIN3_1
This register is assigned to domain3. The master from domain3 can write to this register
End of enumeration elements list.
LOCK : Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LOCK_0
[31] and [27:24] bits can be modified
0x1 : LOCK_1
[31] and [27:24] bits cannot be modified
End of enumeration elements list.
DOM_EN : Domain Control enable for this register
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DOM_EN_0
Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
0x1 : DOM_EN_1
Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
End of enumeration elements list.
USB OTG PHY2 Reset Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBPHY2_POR : USB OTG PHY 2 PORThis is a self clearing bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : USBPHY2_POR_0
De-assert USB OTG PHY2 reset
0x1 : USBPHY2_POR_1
Assert USB OTG PHY2 reset
End of enumeration elements list.
USBPHY2_PORT_RST : USB OTG PHY2 Port Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : USBPHY2_PORT_RST_0
Do not assert USB OTG PHY2 Port Reset
0x1 : USBPHY2_PORT_RST_1
Assert USB OTG PHY2 Port Reset
End of enumeration elements list.
DOMAIN0 : Domain0 assignment control. Effective when dom_en is set to 1.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN0_0
This register is not assigned to domain0. The master from domain3 cannot write to this register.
0x1 : DOMAIN0_1
This register is assigned to domain0. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN1 : Domain1 assignment control. Effective when dom_en is set to 1.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN1_0
This register is not assigned to domain1. The master from domain3 cannot write to this register.
0x1 : DOMAIN1_1
This register is assigned to domain1. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN2 : Domain2 assignment control. Effective when dom_en is set to 1.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN2_0
This register is not assigned to domain2. The master from domain3 cannot write to this register.
0x1 : DOMAIN2_1
This register is assigned to domain2. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN3 : Domain3 assignment control. Effective when dom_en is set to 1.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN3_0
This register is not assigned to domain3. The master from domain3 cannot write to this register.
0x1 : DOMAIN3_1
This register is assigned to domain3. The master from domain3 can write to this register
End of enumeration elements list.
LOCK : Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LOCK_0
[31] and [27:24] bits can be modified
0x1 : LOCK_1
[31] and [27:24] bits cannot be modified
End of enumeration elements list.
DOM_EN : Domain Control enable for this register
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DOM_EN_0
Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
0x1 : DOM_EN_1
Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
End of enumeration elements list.
MIPI PHY Reset Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MIPI_PHY_MRST : MIPI PHY Master Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : MIPI_PHY_MRST_0
Do not assert MIPI PHY Master reset
0x1 : MIPI_PHY_MRST_1
Assert MIPI PHY Master reset
End of enumeration elements list.
MIPI_PHY_SRST : MIPI PHY Slave Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : MIPI_PHY_SRST_0
Do not assert MIPI PHY Slave reset
0x1 : MIPI_PHY_SRST_1
Assert MIPI PHY Slave reset
End of enumeration elements list.
DOMAIN0 : Domain0 assignment control. Effective when dom_en is set to 1.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN0_0
This register is not assigned to domain0. The master from domain3 cannot write to this register.
0x1 : DOMAIN0_1
This register is assigned to domain0. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN1 : Domain1 assignment control. Effective when dom_en is set to 1.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN1_0
This register is not assigned to domain1. The master from domain3 cannot write to this register.
0x1 : DOMAIN1_1
This register is assigned to domain1. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN2 : Domain2 assignment control. Effective when dom_en is set to 1.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN2_0
This register is not assigned to domain2. The master from domain3 cannot write to this register.
0x1 : DOMAIN2_1
This register is assigned to domain2. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN3 : Domain3 assignment control. Effective when dom_en is set to 1.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN3_0
This register is not assigned to domain3. The master from domain3 cannot write to this register.
0x1 : DOMAIN3_1
This register is assigned to domain3. The master from domain3 can write to this register
End of enumeration elements list.
LOCK : Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LOCK_0
[31] and [27:24] bits can be modified
0x1 : LOCK_1
[31] and [27:24] bits cannot be modified
End of enumeration elements list.
DOM_EN : Domain Control enable for this register
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DOM_EN_0
Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
0x1 : DOM_EN_1
Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
End of enumeration elements list.
PCIE PHY Reset Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCIEPHY_G_RST : PCIE PHY Global Reset
bits : 1 - 1 (1 bit)
access : read-write
PCIEPHY_BTN : PCIE PHY button
bits : 2 - 2 (1 bit)
access : read-write
PCIEPHY_PERST : Pciephy_perst
bits : 3 - 3 (1 bit)
access : read-write
PCIE_CTRL_APPS_CLK_REQ : Pcie_ctrl_app_clk_req_n
bits : 4 - 4 (1 bit)
access : read-write
PCIE_CTRL_APPS_RST : Pcie_ctrl_app_init_rst
bits : 5 - 5 (1 bit)
access : read-write
PCIE_CTRL_APPS_EN : Pcie_ctrl_app_ltssm_enable
bits : 6 - 6 (1 bit)
access : read-write
PCIE_CTRL_APPS_READY : Pcie_ctrl_app_ready_entr_l23
bits : 7 - 7 (1 bit)
access : read-write
PCIE_CTRL_APPS_ENTER : Pcie_ctrl_app_req_entr_l1
bits : 8 - 8 (1 bit)
access : read-write
PCIE_CTRL_APPS_EXIT : Pcie_ctrl_app_req_exit_l1
bits : 9 - 9 (1 bit)
access : read-write
PCIE_CTRL_APPS_PME : Pcie_ctrl_apps_pm_xmt_pme
bits : 10 - 10 (1 bit)
access : read-write
PCIE_CTRL_APPS_TURNOFF : Pcie_ctrl_apps_pm_xmt_turnoff
bits : 11 - 11 (1 bit)
access : read-write
PCIE_CTRL_CFG_L1_AUX : Pcie_ctrl_cfg_l1_aux_clk_switch_core_clk_gate_en
bits : 12 - 12 (1 bit)
access : read-write
PCIE_CTRL_CFG_L1_MAC : Pcie_ctrl_cfg_l1_mac_powerdown_override_to_p2_en
bits : 13 - 13 (1 bit)
access : read-write
PCIE_CTRL_SYS_INT : PCIE_CTRL_SYS_INT
bits : 14 - 14 (1 bit)
access : read-write
DOMAIN0 : Domain0 assignment control. Effective when dom_en is set to 1.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN0_0
This register is not assigned to domain0. The master from domain3 cannot write to this register.
0x1 : DOMAIN0_1
This register is assigned to domain0. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN1 : Domain1 assignment control. Effective when dom_en is set to 1.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN1_0
This register is not assigned to domain1. The master from domain3 cannot write to this register.
0x1 : DOMAIN1_1
This register is assigned to domain1. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN2 : Domain2 assignment control. Effective when dom_en is set to 1.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN2_0
This register is not assigned to domain2. The master from domain3 cannot write to this register.
0x1 : DOMAIN2_1
This register is assigned to domain2. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN3 : Domain3 assignment control. Effective when dom_en is set to 1.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN3_0
This register is not assigned to domain3. The master from domain3 cannot write to this register.
0x1 : DOMAIN3_1
This register is assigned to domain3. The master from domain3 can write to this register
End of enumeration elements list.
LOCK : Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LOCK_0
[31] and [27:24] bits can be modified
0x1 : LOCK_1
[31] and [27:24] bits cannot be modified
End of enumeration elements list.
DOM_EN : Domain Control enable for this register
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DOM_EN_0
Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
0x1 : DOM_EN_1
Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
End of enumeration elements list.
A7 Reset Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A7_CORE_POR_RESET0 : POR reset for A7 core0 only
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : A7_CORE_POR_RESET0_0
do not assert core0 reset
0x1 : A7_CORE_POR_RESET0_1
assert core0 reset
End of enumeration elements list.
A7_CORE_POR_RESET1 : POR reset for A7 core1 only
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : A7_CORE_POR_RESET1_0
do not assert core1 reset
0x1 : A7_CORE_POR_RESET1_1
assert core1 reset
End of enumeration elements list.
A7_CORE_RESET0 : Software reset for core0 only
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : A7_CORE_RESET0_0
do not assert core0 reset
0x1 : A7_CORE_RESET0_1
assert core0 reset
End of enumeration elements list.
A7_CORE_RESET1 : Software reset for core1 only
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : A7_CORE_RESET1_0
do not assert core1 reset
0x1 : A7_CORE_RESET1_1
assert core1 reset
End of enumeration elements list.
A7_DBG_RESET0 : Software reset for core0 debug only
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : A7_DBG_RESET0_0
do not assert core0 debug reset
0x1 : A7_DBG_RESET0_1
assert core0 debug reset
End of enumeration elements list.
A7_DBG_RESET1 : Software reset for core1 debug only
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : A7_DBG_RESET1_0
do not assert core1 debug reset
0x1 : A7_DBG_RESET1_1
assert core1 debug reset
End of enumeration elements list.
A7_ETM_RESET0 : Software reset for core0 ETM only
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : A7_ETM_RESET0_0
do not assert core0 ETM reset
0x1 : A7_ETM_RESET0_1
assert core0 ETM reset
End of enumeration elements list.
A7_ETM_RESET1 : Software reset for core1 ETM only
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : A7_ETM_RESET1_0
do not assert core1 ETM reset
0x1 : A7_ETM_RESET1_1
assert core1 ETM reset
End of enumeration elements list.
MASK_WDOG1_RST : Mask wdog1_rst_b source
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x5 : MASK_WDOG1_RST_5
wdog1_rst_b is masked
0xA : MASK_WDOG1_RST_10
wdog1_rst_b is not masked
End of enumeration elements list.
A7_SOC_DBG_RESET : Software reset for system level debug reset
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : A7_SOC_DBG_RESET_0
do not assert system level debug reset
0x1 : A7_SOC_DBG_RESET_1
assert system level debug reset
End of enumeration elements list.
A7_L2RESET : Software reset for A7 Snoop Control Unit (SCU)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : A7_L2RESET_0
do not assert SCU reset
0x1 : A7_L2RESET_1
assert SCU reset
End of enumeration elements list.
DOMAIN0 : Domain0 assignment control. Effective when dom_en is set to 1.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN0_0
This register is not assigned to domain0. The master from domain3 cannot write to this register.
0x1 : DOMAIN0_1
This register is assigned to domain0. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN1 : Domain1 assignment control. Effective when dom_en is set to 1.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN1_0
This register is not assigned to domain1. The master from domain3 cannot write to this register.
0x1 : DOMAIN1_1
This register is assigned to domain1. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN2 : Domain2 assignment control. Effective when dom_en is set to 1.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN2_0
This register is not assigned to domain2. The master from domain3 cannot write to this register.
0x1 : DOMAIN2_1
This register is assigned to domain2. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN3 : Domain3 assignment control. Effective when dom_en is set to 1.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN3_0
This register is not assigned to domain3. The master from domain3 cannot write to this register.
0x1 : DOMAIN3_1
This register is assigned to domain3. The master from domain3 can write to this register
End of enumeration elements list.
LOCK : Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LOCK_0
[31] and [27:24] bits can be modified
0x1 : LOCK_1
[31] and [27:24] bits cannot be modified
End of enumeration elements list.
DOM_EN : Domain Control enable for this register
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DOM_EN_0
Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
0x1 : DOM_EN_1
Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
End of enumeration elements list.
SRC Boot Mode Register 1
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BOOT_CFG1 : Refer to fusemap.
bits : 0 - 7 (8 bit)
access : read-only
BOOT_CFG2 : Refer to fusemap.
bits : 8 - 15 (8 bit)
access : read-only
BOOT_CFG3 : Refer to fusemap.
bits : 16 - 23 (8 bit)
access : read-only
BOOT_CFG4 : Refer to fusemap.
bits : 24 - 31 (8 bit)
access : read-only
SRC Reset Status Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ipp_reset_b : Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ipp_reset_b_0
Reset is not a result of ipp_reset_b pin.
0x1 : ipp_reset_b_1
Reset is a result of ipp_reset_b pin.
End of enumeration elements list.
csu_reset_b : Indicates whether the reset was the result of the csu_reset_b input
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : csu_reset_b_0
Reset is not a result of the csu_reset_b event.
0x1 : csu_reset_b_1
Reset is a result of the csu_reset_b event.
End of enumeration elements list.
ipp_user_reset_b : Indicates whether the reset was the result of the ipp_user_reset_b qualified reset.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : ipp_user_reset_b_0
Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
0x1 : ipp_user_reset_b_1
Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
End of enumeration elements list.
wdog1_rst_b : IC Watchdog1 Time-out reset
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : wdog1_rst_b_0
Reset is not a result of the watchdog1 time-out event.
0x1 : wdog1_rst_b_1
Reset is a result of the watchdog1 time-out event.
End of enumeration elements list.
jtag_rst_b : HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : jtag_rst_b_0
Reset is not a result of HIGH-Z reset from JTAG.
0x1 : jtag_rst_b_1
Reset is a result of HIGH-Z reset from JTAG.
End of enumeration elements list.
jtag_sw_rst : JTAG software reset. Indicates whether the reset was the result of software reset from JTAG.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : jtag_sw_rst_0
Reset is not a result of software reset from JTAG.
0x1 : jtag_sw_rst_1
Reset is a result of software reset from JTAG.
End of enumeration elements list.
wdog3_rst_b : IC Watchdog3 Time-out reset
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : wdog3_rst_b_0
Reset is not a result of the watchdog3 time-out event.
0x1 : wdog3_rst_b_1
Reset is a result of the watchdog3 time-out event.
End of enumeration elements list.
wdog4_rst_b : IC Watchdog4 Time-out reset
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : wdog4_rst_b_0
Reset is not a result of the watchdog4 time-out event.
0x1 : wdog4_rst_b_1
Reset is a result of the watchdog4 time-out event.
End of enumeration elements list.
tempsense_rst_b : Temper Sensor software reset
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : tempsense_rst_b_0
Reset is not a result of software reset from Temperature Sensor.
0x1 : tempsense_rst_b_1
Reset is a result of software reset from Temperature Sensor.
End of enumeration elements list.
SRC Interrupt Status Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HSICPHY_PASSED_RESET : Interrupt generated to indicate that HSIC PHY passed software reset and is ready to be used
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : HSICPHY_PASSED_RESET_0
Interrupt generated not due to HSIC PHY passed reset
0x1 : HSICPHY_PASSED_RESET_1
Interrupt generated due to HSIC PHY passed reset
End of enumeration elements list.
OTGPHY1_PASSED_RESET : Interrupt generated to indicate that OTG PHY1 passed software reset and is ready to be used
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : OTGPHY1_PASSED_RESET_0
Interrupt generated not due to OTG PHY1 passed reset
0x1 : OTGPHY1_PASSED_RESET_1
Interrupt generated due to OTG PHY1 passed reset
End of enumeration elements list.
OTGPHY2_PASSED_RESET : Interrupt generated to indicate that OTG PHY2 passed software reset and is ready to be used
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : OTGPHY2_PASSED_RESET_0
Interrupt generated not due to OTG PHY2 passed reset
0x1 : OTGPHY2_PASSED_RESET_1
Interrupt generated due to OTG PHY2 passed reset
End of enumeration elements list.
MIPIPHY_PASSED_RESET : Interrupt generated to indicate that MIPI PHY passed software reset and is ready to be used
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : MIPIPHY_PASSED_RESET_0
Interrupt generated not due to MIPI PHY passed reset
0x1 : MIPIPHY_PASSED_RESET_1
Interrupt generated due to MIPI PHY passed reset
End of enumeration elements list.
M4C_PASSED_RESET : Interrupt generated to indicate that m4 core passed software reset and is ready to be used
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : M4C_PASSED_RESET_0
interrupt generated not due to m4 core reset
0x1 : M4C_PASSED_RESET_1
interrupt generated due to m4 core reset
End of enumeration elements list.
M4P_PASSED_RESET : Interrupt generated to indicate that m4 platform passed software reset and is ready to be used
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : M4P_PASSED_RESET_0
interrupt generated not due to m4 platform reset
0x1 : M4P_PASSED_RESET_1
interrupt generated due to m4 platform reset
End of enumeration elements list.
SRC Interrupt Mask Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MASK_HSICPHY_PASSED_RESET : mask interrupt generation due to HSIC PHY passed reset
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : MASK_HSICPHY_PASSED_RESET_0
do not mask interrupt due to HSIC PHY passed reset - interrupt will be created
0x1 : MASK_HSICPHY_PASSED_RESET_1
mask interrupt due to HSIC PHY passed reset
End of enumeration elements list.
MASK_OTGPHY1_PASSED_RESET : mask interrupt generation due to OTG PHY1 passed reset
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : MASK_OTGPHY1_PASSED_RESET_0
do not mask interrupt due to OTG PHY1 passed reset - interrupt will be created
0x1 : MASK_OTGPHY1_PASSED_RESET_1
mask interrupt due to OTG PHY1 passed reset
End of enumeration elements list.
MASK_OTGPHY2_PASSED_RESET : mask interrupt generation due to OTG PHY2 passed reset
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : MASK_OTGPHY2_PASSED_RESET_0
do not mask interrupt due to OTG PHY2 passed reset - interrupt will be created
0x1 : MASK_OTGPHY2_PASSED_RESET_1
mask interrupt due to OTG PHY2 passed reset
End of enumeration elements list.
MASK_MIPIPHY_PASSED_RESET : mask interrupt generation due to MIPI PHY passed reset
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : MASK_MIPIPHY_PASSED_RESET_0
do not mask interrupt due to MIPI PHY passed reset - interrupt will be created
0x1 : MASK_MIPIPHY_PASSED_RESET_1
mask interrupt due to MIPI PHY passed reset
End of enumeration elements list.
MASK_M4C_PASSED_RESET : mask interrupt generation due to m4 core passed reset
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : MASK_M4C_PASSED_RESET_0
do not mask interrupt due to m4 core passed reset - interrupt will be created
0x1 : MASK_M4C_PASSED_RESET_1
mask interrupt due to m4 core passed reset
End of enumeration elements list.
MASK_M4P_PASSED_RESET : mask interrupt generation due to m4 platform passed reset
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : MASK_M4P_PASSED_RESET_0
do not mask interrupt due to m4 platform passed reset - interrupt will be created
0x1 : MASK_M4P_PASSED_RESET_1
mask interrupt due to m4platform passed reset
End of enumeration elements list.
SRC Boot Mode Register 2
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_CONFIG : SECONFIG[1] shows the state of the SECONFIG[1] fuse
bits : 0 - 1 (2 bit)
access : read-only
DIR_BT_DIS : DIR_BT_DIS shows the state of the DIR_BT_DIS fuse
bits : 3 - 3 (1 bit)
access : read-only
BT_FUSE_SEL : BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse
bits : 4 - 4 (1 bit)
access : read-only
BMOD : BMOD[1:0] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B
bits : 24 - 25 (2 bit)
access : read-only
SRC General Purpose Register 1
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERSISTENT_ENTRY0 : Holds entry function for core0 for waking-up from low power mode
bits : 0 - 31 (32 bit)
access : read-write
SRC General Purpose Register 2
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERSISTENT_ARG0 : Holds argument of entry function for core0 for waking-up from low power mode
bits : 0 - 31 (32 bit)
access : read-write
SRC General Purpose Register 3
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERSISTENT_ENTRY1 : Holds entry function for core1
bits : 0 - 31 (32 bit)
access : read-write
A7 Reset Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A7_CORE1_ENABLE : core 1 enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : A7_CORE1_ENABLE_0
core1 is disabled
0x1 : A7_CORE1_ENABLE_1
core1 is enabled
End of enumeration elements list.
DOMAIN0 : Domain0 assignment control. Effective when dom_en is set to 1.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN0_0
This register is not assigned to domain0. The master from domain3 cannot write to this register.
0x1 : DOMAIN0_1
This register is assigned to domain0. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN1 : Domain1 assignment control. Effective when dom_en is set to 1.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN1_0
This register is not assigned to domain1. The master from domain3 cannot write to this register.
0x1 : DOMAIN1_1
This register is assigned to domain1. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN2 : Domain2 assignment control. Effective when dom_en is set to 1.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN2_0
This register is not assigned to domain2. The master from domain3 cannot write to this register.
0x1 : DOMAIN2_1
This register is assigned to domain2. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN3 : Domain3 assignment control. Effective when dom_en is set to 1.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN3_0
This register is not assigned to domain3. The master from domain3 cannot write to this register.
0x1 : DOMAIN3_1
This register is assigned to domain3. The master from domain3 can write to this register
End of enumeration elements list.
LOCK : Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LOCK_0
[31] and [27:24] bits can be modified
0x1 : LOCK_1
[31] and [27:24] bits cannot be modified
End of enumeration elements list.
DOM_EN : Domain Control enable for this register
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DOM_EN_0
Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
0x1 : DOM_EN_1
Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
End of enumeration elements list.
SRC General Purpose Register 4
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERSISTENT_ARG1 : Holds argument of entry function for core1
bits : 0 - 31 (32 bit)
access : read-write
SRC General Purpose Register 5
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC General Purpose Register 6
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC General Purpose Register 7
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC General Purpose Register 8
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC General Purpose Register 9
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SRC General Purpose Register 10
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M4 Reset Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_M4C_RST : Self-clearing SW reset for M4 core This is a self clearing bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SW_M4C_RST_0
do not assert M4 core reset
0x1 : SW_M4C_RST_1
assert M4 core reset
End of enumeration elements list.
SW_M4P_RST : Self-clearing SW reset for M4 platform This is a self clearing bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SW_M4P_RST_0
do not assert M4 platform reset
0x1 : SW_M4P_RST_1
assert M4 platform reset
End of enumeration elements list.
ENABLE_M4 : Enable M4
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : ENABLE_M4_0
M4 is disabled
0x1 : ENABLE_M4_1
M4 is enabled
End of enumeration elements list.
MASK_WDOG3_RST : Mask wdog3_rst_b source
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x5 : MASK_WDOG3_RST_5
wdog3_rst_b is masked
0xA : MASK_WDOG3_RST_10
wdog3_rst_b is not masked
End of enumeration elements list.
WDOG3_RST_OPTION_M4 : Wdog3_rst_b option for M4. This bit is only effective when wdog3_rst_option is set to 1.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : WDOG3_RST_OPTION_M4_0
wdgo3_rst_b Reset M4 core only
0x1 : WDOG3_RST_OPTION_M4_1
Reset both M4 core and platform
End of enumeration elements list.
WDOG3_RST_OPTION : Wdog3_rst_b option
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : WDOG3_RST_OPTION_0
Wdog3_rst_b asserts M4 reset
0x1 : WDOG3_RST_OPTION_1
Wdog3_rst_b asserts global reset
End of enumeration elements list.
DOMAIN0 : Domain0 assignment control. Effective when dom_en is set to 1.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN0_0
This register is not assigned to domain0. The master from domain3 cannot write to this register.
0x1 : DOMAIN0_1
This register is assigned to domain0. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN1 : Domain1 assignment control. Effective when dom_en is set to 1.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN1_0
This register is not assigned to domain1. The master from domain3 cannot write to this register.
0x1 : DOMAIN1_1
This register is assigned to domain1. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN2 : Domain2 assignment control. Effective when dom_en is set to 1.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN2_0
This register is not assigned to domain2. The master from domain3 cannot write to this register.
0x1 : DOMAIN2_1
This register is assigned to domain2. The master from domain3 can write to this register
End of enumeration elements list.
DOMAIN3 : Domain3 assignment control. Effective when dom_en is set to 1.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DOMAIN3_0
This register is not assigned to domain3. The master from domain3 cannot write to this register.
0x1 : DOMAIN3_1
This register is assigned to domain3. The master from domain3 can write to this register
End of enumeration elements list.
LOCK : Domain control bits lock Lock bit is a write-once register, once it is set to 1, it can't be write to 0
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LOCK_0
[31] and [27:24] bits can be modified
0x1 : LOCK_1
[31] and [27:24] bits cannot be modified
End of enumeration elements list.
DOM_EN : Domain Control enable for this register
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DOM_EN_0
Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
0x1 : DOM_EN_1
Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
End of enumeration elements list.
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