Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2D44 byte (0x0)
mem_usage : registers
protection : not protected
HW_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0
HW_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0
HW_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1
HW_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1
HW_INPUT_FETCH_BACKGROUND_COLOR_CH0
HW_INPUT_FETCH_BACKGROUND_COLOR_CH1
HW_INPUT_FETCH_SHIFT_OFFSET_CH0
HW_INPUT_FETCH_SHIFT_OFFSET_CH1
HW_INPUT_FETCH_SHIFT_WIDTH_CH0
HW_INPUT_FETCH_SHIFT_WIDTH_CH1
HW_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0
HW_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0
HW_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1
HW_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1
HW_DITHER_FETCH_BACKGROUND_COLOR_CH0
HW_DITHER_FETCH_BACKGROUND_COLOR_CH1
HW_DITHER_FETCH_SHIFT_CTRL_CH0
HW_DITHER_FETCH_SHIFT_CTRL_CH1
HW_DITHER_FETCH_SHIFT_OFFSET_CH0
HW_DITHER_FETCH_SHIFT_OFFSET_CH1
HW_DITHER_FETCH_SHIFT_WIDTH_CH0
HW_DITHER_FETCH_SHIFT_WIDTH_CH1
HW_DITHER_STORE_SHIFT_CTRL_CH0
HW_DITHER_STORE_SHIFT_CTRL_CH1
Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enables PXP operation with specified parameters
bits : 0 - 0 (1 bit)
access : read-write
IRQ_ENABLE : Interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
NEXT_IRQ_ENABLE : Next command interrupt enable
bits : 2 - 2 (1 bit)
access : read-write
LUT_DMA_IRQ_ENABLE : LUT DMA interrupt enable
bits : 3 - 3 (1 bit)
access : read-write
ENABLE_LCD0_HANDSHAKE : Enable handshake with LCD0 controller
bits : 4 - 4 (1 bit)
access : read-write
HANDSHAKE_ABORT_SKIP : When skip is enable, even the abort asserted, pxp will not assert the ready directly but wait for whole block line complete
bits : 5 - 5 (1 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
ROTATE0 : Indicates the clockwise rotation to be applied at the output buffer
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ROT_0
ROT_0
0x1 : ROT_90
ROT_90
0x2 : ROT_180
ROT_180
0x3 : ROT_270
ROT_270
End of enumeration elements list.
HFLIP0 : Indicates that the output buffer should be flipped horizontally (effect applied before rotation).
bits : 10 - 10 (1 bit)
access : read-write
VFLIP0 : Indicates that the output buffer should be flipped vertically (effect applied before rotation).
bits : 11 - 11 (1 bit)
access : read-write
ROTATE1 : Indicates the clockwise rotation to be applied at the input buffer
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ROT_0
ROT_0
0x1 : ROT_90
ROT_90
0x2 : ROT_180
ROT_180
0x3 : ROT_270
ROT_270
End of enumeration elements list.
HFLIP1 : Indicates that the input should be flipped horizontally (effect applied before rotation).
bits : 14 - 14 (1 bit)
access : read-write
VFLIP1 : Indicates that the input should be flipped vertically (effect applied before rotation).
bits : 15 - 15 (1 bit)
access : read-write
ENABLE_PS_AS_OUT : Enable the PS engine, AS engine, OUTBUF in the PXP primary processing flow.
bits : 16 - 16 (1 bit)
access : read-write
ENABLE_DITHER : Enable the Dithering engine in the PXP primary processing flow.
bits : 17 - 17 (1 bit)
access : read-write
ENABLE_WFE_A : Enable the WFE-A engine in the PXP primary processing flow.
bits : 18 - 18 (1 bit)
access : read-write
ENABLE_WFE_B : Enable the WFE-B engine in the PXP primary processing flow.
bits : 19 - 19 (1 bit)
access : read-write
ENABLE_INPUT_FETCH_STORE : Enable the Input Fetch and Store engine in the PXP primary processing flow.
bits : 20 - 20 (1 bit)
access : read-write
ENABLE_ALPHA_B : Enable the Alpha-B engine in the PXP primary processing flow.
bits : 21 - 21 (1 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 22 - 22 (1 bit)
access : read-only
BLOCK_SIZE : Select the block size to process through the Rotate block.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : 8X8
Process 8x8 pixel blocks.
0x1 : 16X16
Process 16x16 pixel blocks.
End of enumeration elements list.
ENABLE_CSC2 : Enable the CSC2 engine in the PXP primary processing flow.
bits : 24 - 24 (1 bit)
access : read-write
ENABLE_LUT : Enable the LUT engine in the PXP primary processing flow.
bits : 25 - 25 (1 bit)
access : read-write
ENABLE_ROTATE0 : Enable the ROTATE0 engine in the PXP primary processing flow.
bits : 26 - 26 (1 bit)
access : read-write
ENABLE_ROTATE1 : Enable the ROTATE1 engine in the PXP primary processing flow.
bits : 27 - 27 (1 bit)
access : read-write
EN_REPEAT : Enable the PXP to run continuously
bits : 28 - 28 (1 bit)
access : read-write
RSVD4 : Reserved, always set to zero.
bits : 29 - 29 (1 bit)
access : read-only
CLKGATE : This bit must be set to zero for normal operation
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : Set this bit to zero to enable normal PXP operation
bits : 31 - 31 (1 bit)
access : read-write
Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Indicates current PXP interrupt status
bits : 0 - 0 (1 bit)
access : read-write
AXI_WRITE_ERROR_0 : Indicates PXP encountered an AXI write error and processing has been terminated.
bits : 1 - 1 (1 bit)
access : read-write
AXI_READ_ERROR_0 : Indicates PXP encountered an AXI read error and processing has been terminated.
bits : 2 - 2 (1 bit)
access : read-write
NEXT_IRQ : Indicates that a command issued with the "Next Command" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register
bits : 3 - 3 (1 bit)
access : read-write
AXI_ERROR_ID_0 : Indicates the AXI0 ID of the failing bus operation.
bits : 4 - 7 (4 bit)
access : read-only
LUT_DMA_LOAD_DONE_IRQ : Indicates that the LUT DMA transfer has completed.
bits : 8 - 8 (1 bit)
access : read-write
AXI_WRITE_ERROR_1 : Indicates PXP encountered an AXI write error and processing has been terminated.
bits : 9 - 9 (1 bit)
access : read-write
AXI_READ_ERROR_1 : Indicates PXP encountered an AXI read error and processing has been terminated.
bits : 10 - 10 (1 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 11 - 11 (1 bit)
access : read-only
AXI_ERROR_ID_1 : Indicates the AXI1 ID of the failing bus operation.
bits : 12 - 15 (4 bit)
access : read-only
BLOCKY : Indicates the X coordinate of the block currently being rendered.
bits : 16 - 23 (8 bit)
access : read-only
BLOCKX : Indicates the X coordinate of the block currently being rendered.
bits : 24 - 31 (8 bit)
access : read-only
PS Background Color
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COLOR : Background color (in 24bpp format) for any pixels not within the buffer range specified by the PS ULC/LRC
bits : 0 - 23 (24 bit)
access : read-write
RSVD : Reserved, always set to zero.
bits : 24 - 31 (8 bit)
access : read-only
PS Scale Factor Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XSCALE : This is a two bit integer and 12 bit fractional representation (##
bits : 0 - 14 (15 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 15 - 15 (1 bit)
access : read-only
YSCALE : This is a two bit integer and 12 bit fractional representation (##
bits : 16 - 30 (15 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 31 - 31 (1 bit)
access : read-only
PS Scale Offset Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XOFFSET : This is a 12 bit fractional representation (0
bits : 0 - 11 (12 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 12 - 15 (4 bit)
access : read-only
YOFFSET : This is a 12 bit fractional representation (0
bits : 16 - 27 (12 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 28 - 31 (4 bit)
access : read-only
PS Color Key Low
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIXEL : Low range of color key applied to PS buffer
bits : 0 - 23 (24 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 24 - 31 (8 bit)
access : read-only
PS Color Key High
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIXEL : High range of color key applied to PS buffer
bits : 0 - 23 (24 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 24 - 31 (8 bit)
access : read-only
Alpha Surface Control
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD0 : Reserved, always set to zero.
bits : 0 - 0 (1 bit)
access : read-only
ALPHA_CTRL : Determines how the alpha value is constructed for this alpha surface
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Embedded
Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored.
0x1 : Override
Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels.
0x2 : Multiply
Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field.
0x3 : ROPs
Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels.
End of enumeration elements list.
ENABLE_COLORKEY : Indicates that colorkey functionality is enabled for this alpha surface
bits : 3 - 3 (1 bit)
access : read-write
FORMAT : Indicates the input buffer format for AS.
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : ARGB8888
32-bit pixels with alpha
0x1 : RGBA8888
32-bit pixels with alpha
0x4 : RGB888
32-bit pixels without alpha (unpacked 24-bit format)
0x8 : ARGB1555
16-bit pixels with alpha
0x9 : ARGB4444
16-bit pixels with alpha
0xC : RGB555
16-bit pixels without alpha
0xD : RGB444
16-bit pixels without alpha
0xE : RGB565
16-bit pixels without alpha
End of enumeration elements list.
ALPHA : Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in REG_AS_CTRL[ALPHA_CTRL]
bits : 8 - 15 (8 bit)
access : read-write
ROP : Indicates a raster operation to perform when enabled
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : MASKAS
AS AND PS
0x1 : MASKNOTAS
nAS AND PS
0x2 : MASKASNOT
AS AND nPS
0x3 : MERGEAS
AS OR PS
0x4 : MERGENOTAS
nAS OR PS
0x5 : MERGEASNOT
AS OR nPS
0x6 : NOTCOPYAS
nAS
0x7 : NOT
nPS
0x8 : NOTMASKAS
AS NAND PS
0x9 : NOTMERGEAS
AS NOR PS
0xA : XORAS
AS XOR PS
0xB : NOTXORAS
AS XNOR PS
End of enumeration elements list.
ALPHA0_INVERT : Setting this bit to logic 0 will not alter the alpha0 value
bits : 20 - 20 (1 bit)
access : read-write
ALPHA1_INVERT : Setting this bit to logic 0 will not alter the alpha1 value
bits : 21 - 21 (1 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 22 - 31 (10 bit)
access : read-only
Alpha Surface Buffer Pointer
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer for the alpha surface 0 buffer.
bits : 0 - 31 (32 bit)
access : read-write
Dither Control Register 0
address_offset : 0x1670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE0 : Enables the dither engine 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disabled
The dither engine 0 will not process any frames.
0x1 : Enabled
The dither engine 0 is on and ready for processing
End of enumeration elements list.
ENABLE1 : Enables the dither engine 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : Disabled
The dither engine 1 will not process any frames.
0x1 : Enabled
The dither engine 1 is on and ready for processing
End of enumeration elements list.
ENABLE2 : Enables the dither engine 2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : Disabled
The dither engine 2 will not process any frames.
0x1 : Enabled
The dither engine 2 is on and ready for processing
End of enumeration elements list.
DITHER_MODE0 : Dither mode.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : 0
Pass through.
0x1 : 1
Floyd-Steinberg.
0x2 : 2
Atkinson.
0x3 : 3
Ordered.
0x4 : 4
No Dithering, quantization only.
End of enumeration elements list.
DITHER_MODE1 : Dither mode.
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : 0
Pass through.
0x3 : 3
Ordered.
0x4 : 4
No Dithering, quantization only.
End of enumeration elements list.
DITHER_MODE2 : Dither mode.
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : 0
Pass through.
0x3 : 3
Ordered.
0x4 : 4
No Dithering, quantization only.
End of enumeration elements list.
NUM_QUANT_BIT : Number of bits to quantize down to. From 8 to (0-7).
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x1 : 1
Quantize down to 1 bit.
0x2 : 2
Quantize down to 2 bits.
0x3 : 3
Quantize down to 3 bits.
0x4 : 4
Quantize down to 4 bits.
0x5 : 5
Quantize down to 5 bits.
0x6 : 6
Quantize down to 6 bits.
0x7 : 7
Quantize down to 7 bits.
End of enumeration elements list.
LUT_MODE : Specify to use memory lut to transform pixel
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
0 : 0
LUT mode off.
0x1 : 1
Use LUT at pre-diter stage.
0x2 : 2
Use LUT at post-dither stage.
End of enumeration elements list.
IDX_MATRIX0_SIZE : For Dither Engine 0
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0 : 0
4x4
0x1 : 1
8x8
0x2 : 2
16x16
0x3 : 3
Input value of index
End of enumeration elements list.
IDX_MATRIX1_SIZE : For Dither Engine 1
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
0 : 0
4x4
0x1 : 1
8x8
0x2 : 2
16x16
0x3 : 3
Input value of index
End of enumeration elements list.
IDX_MATRIX2_SIZE : For Dither Engine 2
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0 : 0
4x4
0x1 : 1
8x8
0x2 : 2
16x16
0x3 : 3
Input value of index
End of enumeration elements list.
FINAL_LUT_ENABLE : Enables a final stage register based LUT at the last stage before output
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : Disabled
The dither engine 2 will not process any frames.
0x1 : Enabled
The dither engine 2 is on and ready for processing
End of enumeration elements list.
ORDERED_ROUND_MODE : For test purposes
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : 0
Use truncation method.
0x1 : 1
Use rounding method.
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 25 - 28 (4 bit)
access : read-only
BUSY2 : When set indicates if the dither engine 2 is busy -- started but not finished processing all of the pixels in the current frame
bits : 29 - 29 (1 bit)
access : read-only
BUSY1 : When set indicates if the dither engine 1 is busy -- started but not finished processing all of the pixels in the current frame
bits : 30 - 30 (1 bit)
access : read-only
BUSY0 : When set indicates if the dither engine 0 is busy -- started but not finished processing all of the pixels in the current frame
bits : 31 - 31 (1 bit)
access : read-only
Final stage lookup value Register
address_offset : 0x1680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Final stage LUT data value.
bits : 0 - 7 (8 bit)
access : read-write
DATA1 : Final stage LUT data value.
bits : 8 - 15 (8 bit)
access : read-write
DATA2 : Final stage LUT data value.
bits : 16 - 23 (8 bit)
access : read-write
DATA3 : Final stage LUT data value.
bits : 24 - 31 (8 bit)
access : read-write
Final stage lookup value Register
address_offset : 0x1690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA4 : Final stage LUT data value.
bits : 0 - 7 (8 bit)
access : read-write
DATA5 : Final stage LUT data value.
bits : 8 - 15 (8 bit)
access : read-write
DATA6 : Final stage LUT data value.
bits : 16 - 23 (8 bit)
access : read-write
DATA7 : Final stage LUT data value.
bits : 24 - 31 (8 bit)
access : read-write
Final stage lookup value Register
address_offset : 0x16A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA8 : Final stage LUT data value.
bits : 0 - 7 (8 bit)
access : read-write
DATA9 : Final stage LUT data value.
bits : 8 - 15 (8 bit)
access : read-write
DATA10 : Final stage LUT data value.
bits : 16 - 23 (8 bit)
access : read-write
DATA11 : Final stage LUT data value.
bits : 24 - 31 (8 bit)
access : read-write
Final stage lookup value Register
address_offset : 0x16B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA12 : Final stage LUT data value.
bits : 0 - 7 (8 bit)
access : read-write
DATA13 : Final stage LUT data value.
bits : 8 - 15 (8 bit)
access : read-write
DATA14 : Final stage LUT data value.
bits : 16 - 23 (8 bit)
access : read-write
DATA15 : Final stage LUT data value.
bits : 24 - 31 (8 bit)
access : read-write
Alpha Surface Pitch
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PITCH : Indicates the number of bytes in memory between two vertically adjacent pixels.
bits : 0 - 15 (16 bit)
access : read-write
RSVD : Reserved, always set to zero.
bits : 16 - 31 (16 bit)
access : read-only
Overlay Color Key Low
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIXEL : Low range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable.
bits : 0 - 23 (24 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 24 - 31 (8 bit)
access : read-only
Overlay Color Key High
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIXEL : High range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable.
bits : 0 - 23 (24 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 24 - 31 (8 bit)
access : read-only
Color Space Conversion Coefficient Register 0
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Y_OFFSET : Two's compliment amplitude offset implicit in the Y data
bits : 0 - 8 (9 bit)
access : read-write
UV_OFFSET : Two's compliment phase offset implicit for CbCr data
bits : 9 - 17 (9 bit)
access : read-write
C0 : Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164)
bits : 18 - 28 (11 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 29 - 29 (1 bit)
access : read-only
BYPASS : Bypass the CSC unit in the scaling engine
bits : 30 - 30 (1 bit)
access : read-write
YCBCR_MODE : Set to 1 when performing YCbCr conversion to RGB
bits : 31 - 31 (1 bit)
access : read-write
Color Space Conversion Coefficient Register 1
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C4 : Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017)
bits : 0 - 10 (11 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 11 - 15 (5 bit)
access : read-only
C1 : Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596)
bits : 16 - 26 (11 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 27 - 31 (5 bit)
access : read-only
Color Space Conversion Coefficient Register 2
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C3 : Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392)
bits : 0 - 10 (11 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 11 - 15 (5 bit)
access : read-only
C2 : Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813)
bits : 16 - 26 (11 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 27 - 31 (5 bit)
access : read-only
Color Space Conversion Control Register.
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYPASS : This bit controls whether the pixels entering the CSC2 unit get converted or not
bits : 0 - 0 (1 bit)
access : read-write
CSC_MODE : This field controls how the CSC unit operates on pixels when the CSC is not bypassed.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : YUV2RGB
Convert from YUV to RGB.
0x1 : YCbCr2RGB
Convert from YCbCr to RGB.
0x2 : RGB2YUV
Convert from RGB to YUV.
0x3 : RGB2YCbCr
Convert from RGB to YCbCr.
End of enumeration elements list.
RSVD : Reserved, always set to zero.
bits : 3 - 31 (29 bit)
access : read-only
Color Space Conversion Coefficient Register 0
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A1 : Two's compliment coefficient offset
bits : 0 - 10 (11 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 11 - 15 (5 bit)
access : read-only
A2 : Two's compliment coefficient offset
bits : 16 - 26 (11 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 27 - 31 (5 bit)
access : read-only
Color Space Conversion Coefficient Register 1
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A3 : Two's compliment coefficient offset
bits : 0 - 10 (11 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 11 - 15 (5 bit)
access : read-only
B1 : Two's compliment coefficient offset
bits : 16 - 26 (11 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 27 - 31 (5 bit)
access : read-only
Output Buffer Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORMAT : Output framebuffer format
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ARGB8888
32-bit pixels
0x4 : RGB888
32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
0x5 : RGB888P
24-bit pixels (packed 24-bit format)
0x8 : ARGB1555
16-bit pixels
0x9 : ARGB4444
16-bit pixels
0xC : RGB555
16-bit pixels
0xD : RGB444
16-bit pixels
0xE : RGB565
16-bit pixels
0x10 : YUV1P444
32-bit pixels (1-plane XYUV unpacked)
0x12 : UYVY1P422
16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
0x13 : VYUY1P422
16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
0x14 : Y8
8-bit monochrome pixels (1-plane Y luma output)
0x15 : Y4
4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
0x18 : YUV2P422
16-bit pixels (2-plane UV interleaved bytes)
0x19 : YUV2P420
16-bit pixels (2-plane UV)
0x1A : YVU2P422
16-bit pixels (2-plane VU interleaved bytes)
0x1B : YVU2P420
16-bit pixels (2-plane VU)
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 5 - 7 (3 bit)
access : read-only
INTERLACED_OUTPUT : Determines how the PXP writes it's output data
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PROGRESSIVE
All data written in progressive format to the OUTBUF Pointer.
0x1 : FIELD0
Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
0x2 : FIELD1
Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
0x3 : INTERLACED
Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 10 - 22 (13 bit)
access : read-only
ALPHA_OUTPUT : Indicates that alpha component in output buffer pixels should be overwritten by REG_OUT_CTRL[ALPHA] register
bits : 23 - 23 (1 bit)
access : read-write
ALPHA : When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline
bits : 24 - 31 (8 bit)
access : read-write
Color Space Conversion Coefficient Register 2
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B2 : Two's compliment coefficient offset
bits : 0 - 10 (11 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 11 - 15 (5 bit)
access : read-only
B3 : Two's compliment coefficient offset
bits : 16 - 26 (11 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 27 - 31 (5 bit)
access : read-only
Color Space Conversion Coefficient Register 3
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C1 : Two's compliment coefficient offset
bits : 0 - 10 (11 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 11 - 15 (5 bit)
access : read-only
C2 : Two's compliment coefficient offset
bits : 16 - 26 (11 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 27 - 31 (5 bit)
access : read-only
Color Space Conversion Coefficient Register 4
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C3 : Two's compliment coefficient offset
bits : 0 - 10 (11 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 11 - 15 (5 bit)
access : read-only
D1 : Two's compliment coefficient integer offset to be added.
bits : 16 - 24 (9 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 25 - 31 (7 bit)
access : read-only
Color Space Conversion Coefficient Register 5
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D2 : Two's compliment D1 coefficient integer offset to be added.
bits : 0 - 8 (9 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 9 - 15 (7 bit)
access : read-only
D3 : Two's compliment coefficient integer offset to be added.
bits : 16 - 24 (9 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 25 - 31 (7 bit)
access : read-only
Lookup Table Control Register.
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_START : Setting this bit will result in the DMA operation to load the PXP LUT memory based on REG_LUT_ADDR_NUM_BYTES, REG_LUT_ADDR_ADDR, and REG_LUT_MEM_ADDR
bits : 0 - 0 (1 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 1 - 7 (7 bit)
access : read-only
INVALID : Invalidate the cache LRU and valid bits. This bit will automatically reset when set to a logic 1.
bits : 8 - 8 (1 bit)
access : read-write
LRU_UPD : Least Recently Used Policy Update Control: 1=> block LRU update for hit after miss
bits : 9 - 9 (1 bit)
access : read-write
SEL_8KB : Selects which 8KB bank of memory to use for direct 12bpp lookup modes
bits : 10 - 10 (1 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 11 - 15 (5 bit)
access : read-only
OUT_MODE : Select the output mode of operation for the LUT resource
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x1 : Y8
R/Y byte lane 2 lookup, bytes 1,0 bypassed.
0x2 : RGBW4444CFA
Byte lane 2 = CFA_Y8, byte lane 1,0 = RGBW4444.
0x3 : RGB888
RGB565->RGB888 conversion for Gamma correction.
End of enumeration elements list.
RSVD2 : Reserved, always set to zero.
bits : 18 - 23 (6 bit)
access : read-only
LOOKUP_MODE : Configure the input address for the 16KB LUT memory
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : CACHE_RGB565
LUT ADDR = R[7:3],G[7:2],B[7:3]. Use all 16KB of LUT for indirect cached 128KB lookup.
0x1 : DIRECT_Y8
LUT ADDR = 16'b0,Y[7:0]. Use only the first 256 bytes of LUT. Only the Y, or third data path byte, is tranformed.
0x2 : DIRECT_RGB444
LUT ADDR = R[7:4],G[7:4],B[7:4]. Use one 8KB bank of LUT selected by SEL_8KB.
0x3 : DIRECT_RGB454
LUT ADDR = R[7:4],G[7:3],B[7:4]. Use all 16KB of LUT.
End of enumeration elements list.
RSVD3 : Reserved, always set to zero.
bits : 26 - 30 (5 bit)
access : read-only
BYPASS : Setting this bit will bypass the LUT memory resource completely
bits : 31 - 31 (1 bit)
access : read-write
Lookup Table Control Register.
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : LUT indexed address pointer
bits : 0 - 13 (14 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
NUM_BYTES : Indicates the number of bytes to load via a DMA operation
bits : 16 - 30 (15 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 31 - 31 (1 bit)
access : read-only
Lookup Table Data Register.
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Writing this field will load 4 bytes, aligned to four byte boundaries, of data indexed by the ADDR field of the REG_LUT_CTRL register
bits : 0 - 31 (32 bit)
access : read-write
Lookup Table External Memory Address Register.
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : This register contains the external memory address used for LUT memory operation.
bits : 0 - 31 (32 bit)
access : read-write
Color Filter Array Register.
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This register contains the Color Filter Array pattern for decimation of RGBW4444 16 bit pixels to individual R, G, B, W values
bits : 0 - 31 (32 bit)
access : read-write
PXP Alpha Engine A Control Register.
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POTER_DUFF_ENABLE : poter_duff enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
porter duff disable.
0x1 : 1
porter duff enable.
End of enumeration elements list.
S0_S1_FACTOR_MODE : s0 to s1 factor mode
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : 0
using 1.
0x1 : 1
using 0.
0x2 : 2
using straight alpha.
0x3 : 3
using inverse alpha.
End of enumeration elements list.
S0_GLOBAL_ALPHA_MODE : s0 global alpha mode
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : 0
using global alpha.
0x1 : 1
using local alpha.
0x2 : 2
using scaled alpha.
0x3 : 3
using scaled alpha.
End of enumeration elements list.
S0_ALPHA_MODE : s0 alpha mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : 0
straight mode for s0 alpha
0x1 : 1
inversed mode for s0 alpha
End of enumeration elements list.
S0_COLOR_MODE : s0 color mode
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : 0
straight mode for s0 color
0x1 : 1
multiply mode for s0 color
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 7 - 7 (1 bit)
access : read-only
S1_S0_FACTOR_MODE : s1 to s0 factor mode
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : 0
using 1.
0x1 : 1
using 0.
0x2 : 2
using straight alpha.
0x3 : 3
using inverse alpha.
End of enumeration elements list.
S1_GLOBAL_ALPHA_MODE : s1 global alpha mode
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : 0
using global alpha.
End of enumeration elements list.
S1_ALPHA_MODE : s1 alpha mode
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : 0
straight mode for s1 alpha
0x1 : 1
inversed mode for s1 alpha
End of enumeration elements list.
S1_COLOR_MODE : s1 color mode
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : 0
straight mode for s1 color
0x1 : 1
multiply mode for s1 color
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
S0_GLOBAL_ALPHA : s0 global alpha
bits : 16 - 23 (8 bit)
access : read-write
S1_GLOBAL_ALPHA : s1 global alpha
bits : 24 - 31 (8 bit)
access : read-write
PXP Alpha Engine B Control Register.
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POTER_DUFF_ENABLE : poter_duff enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
porter duff disable.
0x1 : 1
porter duff enable.
End of enumeration elements list.
S0_S1_FACTOR_MODE : s0 to s1 factor mode
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : 0
using 1.
0x1 : 1
using 0.
0x2 : 2
using straight alpha.
0x3 : 3
using inverse alpha.
End of enumeration elements list.
S0_GLOBAL_ALPHA_MODE : s0 global alpha mode
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : 0
using global alpha.
0x1 : 1
using local alpha.
0x2 : 2
using scaled alpha.
0x3 : 3
using scaled alpha.
End of enumeration elements list.
S0_ALPHA_MODE : s0 alpha mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : 0
straight mode for s0 alpha
0x1 : 1
inversed mode for s0 alpha
End of enumeration elements list.
S0_COLOR_MODE : s0 color mode
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : 0
straight mode for s0 color
0x1 : 1
multiply mode for s0 color
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 7 - 7 (1 bit)
access : read-only
S1_S0_FACTOR_MODE : s1 to s0 factor mode
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : 0
using 1.
0x1 : 1
using 0.
0x2 : 2
using straight alpha.
0x3 : 3
using inverse alpha.
End of enumeration elements list.
S1_GLOBAL_ALPHA_MODE : s1 global alpha mode
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : 0
using global alpha.
0x1 : 1
using local alpha.
0x2 : 2
using scaled alpha.
0x3 : 3
using scaled alpha.
End of enumeration elements list.
S1_ALPHA_MODE : s1 alpha mode
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : 0
straight mode for s1 alpha
0x1 : 1
inversed mode for s1 alpha
End of enumeration elements list.
S1_COLOR_MODE : s1 color mode
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : 0
straight mode for s1 color
0x1 : 1
multiply mode for s1 color
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
S0_GLOBAL_ALPHA : s0 global alpha
bits : 16 - 23 (8 bit)
access : read-write
S1_GLOBAL_ALPHA : s1 global alpha
bits : 24 - 31 (8 bit)
access : read-write
Histogram Control Register.
address_offset : 0x2A00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable the Histogram Engine
bits : 0 - 0 (1 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 1 - 3 (3 bit)
access : read-only
CLEAR : Write 1 to clear the histogram result and will be self-clear after clear function finished
bits : 4 - 4 (1 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 5 - 7 (3 bit)
access : read-only
STATUS : Indicates which histogram matched the processed bitmap
bits : 8 - 12 (5 bit)
access : read-only
RSVD2 : Reserved, always set to zero.
bits : 13 - 15 (3 bit)
access : read-only
PIXEL_OFFSET : The offset of the pixel to be used for histogram calculation
bits : 16 - 22 (7 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 23 - 23 (1 bit)
access : read-only
PIXEL_WIDTH : The width of the pixel to be used for histogram calculation
bits : 24 - 26 (3 bit)
access : read-write
RSVD4 : Reserved, always set to zero.
bits : 27 - 31 (5 bit)
access : read-only
Histogram Pixel Mask Register.
address_offset : 0x2A10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK_EN : Enable the Pixel Mask Function in Histogram
bits : 0 - 0 (1 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 1 - 3 (3 bit)
access : read-only
MASK_MODE : Operation mode of pixel mask function
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : EQUAL
Run histogram for pixels equal to value0
0x1 : NOT_EQUAL
Run histogram for pixels not equal to value0
0x2 : INSIDE
Run histogram for pixels within the range of value0 to value1
0x3 : OUTSIDE
Run histogram for pixels outside of the rang of value0 to value1
End of enumeration elements list.
MASK_OFFSET : The offset of the field to be checked against mask condition
bits : 6 - 12 (7 bit)
access : read-write
MASK_WIDTH : The width of the field to be checked against mask condition
bits : 13 - 15 (3 bit)
access : read-write
MASK_VALUE0 : The value0 for mask condition checking
bits : 16 - 23 (8 bit)
access : read-write
MASK_VALUE1 : The value1 for mask condition checking
bits : 24 - 31 (8 bit)
access : read-write
Histogram Pixel Buffer Size Register.
address_offset : 0x2A20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : This indicate the buffer width in pixels
bits : 0 - 11 (12 bit)
access : read-write
RSVD1 : Reserved. This field always reads 0.
bits : 12 - 15 (4 bit)
access : read-only
HEIGHT : This indicate the buffer height in pixels
bits : 16 - 27 (12 bit)
access : read-write
RSVD0 : Reserved. This field always reads 0.
bits : 28 - 31 (4 bit)
access : read-only
Total Number of Pixels Used by Histogram Engine.
address_offset : 0x2A30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TOTAL_PIXEL : Total number of pixels used by histogram engine, the pixels got masked will be skipped
bits : 0 - 23 (24 bit)
access : read-only
RSVD0 : Reserved. This field always reads 0.
bits : 24 - 31 (8 bit)
access : read-only
The X Coordinate Offset for Active Area.
address_offset : 0x2A40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MIN_X_OFFSET : Minimul X coordinate offset for the active area in histogram processing
bits : 0 - 11 (12 bit)
access : read-only
RSVD0 : Reserved. This field always reads 0.
bits : 12 - 15 (4 bit)
access : read-only
MAX_X_OFFSET : Maximum X coordinate offset for the active area in histogram processing
bits : 16 - 27 (12 bit)
access : read-only
RSVD1 : Reserved. This field always reads 0.
bits : 28 - 31 (4 bit)
access : read-only
The Y Coordinate Offset for Active Area.
address_offset : 0x2A50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MIN_Y_OFFSET : Minimul Y coordinate offset for the active area in histogram processing
bits : 0 - 11 (12 bit)
access : read-only
RSVD0 : Reserved. This field always reads 0.
bits : 12 - 15 (4 bit)
access : read-only
MAX_Y_OFFSET : Maximum Y coordinate offset for the active area in histogram processing
bits : 16 - 27 (12 bit)
access : read-only
RSVD1 : Reserved. This field always reads 0.
bits : 28 - 31 (4 bit)
access : read-only
Histogram Result Based on RAW Pixel Value.
address_offset : 0x2A60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STAT0 : Lower 32-bit result fo the histogram calculation
bits : 0 - 31 (32 bit)
access : read-only
Histogram Result Based on RAW Pixel Value.
address_offset : 0x2A70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STAT1 : Higher 32-bit result fo the histogram calculation
bits : 0 - 31 (32 bit)
access : read-only
Histogram Control Register.
address_offset : 0x2A80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable the Histogram Engine
bits : 0 - 0 (1 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 1 - 3 (3 bit)
access : read-only
CLEAR : Write 1 to clear the histogram result and will be self-clear after clear function finished
bits : 4 - 4 (1 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 5 - 7 (3 bit)
access : read-only
STATUS : Indicates which histogram matched the processed bitmap
bits : 8 - 12 (5 bit)
access : read-only
RSVD2 : Reserved, always set to zero.
bits : 13 - 15 (3 bit)
access : read-only
PIXEL_OFFSET : The offset of the pixel to be used for histogram calculation
bits : 16 - 22 (7 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 23 - 23 (1 bit)
access : read-only
PIXEL_WIDTH : The width of the pixel to be used for histogram calculation
bits : 24 - 26 (3 bit)
access : read-write
RSVD4 : Reserved, always set to zero.
bits : 27 - 31 (5 bit)
access : read-only
Histogram Pixel Mask Register.
address_offset : 0x2A90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK_EN : Enable the Pixel Mask Function in Histogram
bits : 0 - 0 (1 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 1 - 3 (3 bit)
access : read-only
MASK_MODE : Operation mode of pixel mask function
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : EQUAL
Run histogram for pixels equal to value0
0x1 : NOT_EQUAL
Run histogram for pixels not equal to value0
0x2 : INSIDE
Run histogram for pixels within the range of value0 to value1
0x3 : OUTSIDE
Run histogram for pixels outside of the rang of value0 to value1
End of enumeration elements list.
MASK_OFFSET : The offset of the field to be checked against mask condition
bits : 6 - 12 (7 bit)
access : read-write
MASK_WIDTH : The width of the field to be checked against mask condition
bits : 13 - 15 (3 bit)
access : read-write
MASK_VALUE0 : The value0 for mask condition checking
bits : 16 - 23 (8 bit)
access : read-write
MASK_VALUE1 : The value1 for mask condition checking
bits : 24 - 31 (8 bit)
access : read-write
Histogram Pixel Buffer Size Register.
address_offset : 0x2AA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : This indicate the buffer width in pixels
bits : 0 - 11 (12 bit)
access : read-write
RSVD1 : Reserved. This field always reads 0.
bits : 12 - 15 (4 bit)
access : read-only
HEIGHT : This indicate the buffer height in pixels
bits : 16 - 27 (12 bit)
access : read-write
RSVD0 : Reserved. This field always reads 0.
bits : 28 - 31 (4 bit)
access : read-only
Total Number of Pixels Used by Histogram Engine.
address_offset : 0x2AB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TOTAL_PIXEL : Total number of pixels used by histogram engine, the pixels got masked will be skipped
bits : 0 - 23 (24 bit)
access : read-only
RSVD0 : Reserved. This field always reads 0.
bits : 24 - 31 (8 bit)
access : read-only
The X Coordinate Offset for Active Area.
address_offset : 0x2AC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MIN_X_OFFSET : Minimul X coordinate offset for the active area in histogram processing
bits : 0 - 11 (12 bit)
access : read-only
RSVD0 : Reserved. This field always reads 0.
bits : 12 - 15 (4 bit)
access : read-only
MAX_X_OFFSET : Maximum X coordinate offset for the active area in histogram processing
bits : 16 - 27 (12 bit)
access : read-only
RSVD1 : Reserved. This field always reads 0.
bits : 28 - 31 (4 bit)
access : read-only
The Y Coordinate Offset for Active Area.
address_offset : 0x2AD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MIN_Y_OFFSET : Minimul Y coordinate offset for the active area in histogram processing
bits : 0 - 11 (12 bit)
access : read-only
RSVD0 : Reserved. This field always reads 0.
bits : 12 - 15 (4 bit)
access : read-only
MAX_Y_OFFSET : Maximum Y coordinate offset for the active area in histogram processing
bits : 16 - 27 (12 bit)
access : read-only
RSVD1 : Reserved. This field always reads 0.
bits : 28 - 31 (4 bit)
access : read-only
Histogram Result Based on RAW Pixel Value.
address_offset : 0x2AE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STAT0 : Lower 32-bit result fo the histogram calculation
bits : 0 - 31 (32 bit)
access : read-only
Histogram Result Based on RAW Pixel Value.
address_offset : 0x2AF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STAT1 : Higher 32-bit result fo the histogram calculation
bits : 0 - 31 (32 bit)
access : read-only
no description available
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROP_ENABLE : ROP ENABLE
bits : 0 - 0 (1 bit)
access : read-write
OL_CLRKEY_ENABLE : Indicates that colorkey functionality is enabled for this alpha surface
bits : 1 - 1 (1 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 2 - 3 (2 bit)
access : read-only
ROP : Indicates a raster operation to perform when enabled.
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : MASKAS
AS AND PS
0x1 : MASKNOTAS
nAS AND PS
0x2 : MASKASNOT
AS AND nPS
0x3 : MERGEAS
AS OR PS
0x4 : MERGENOTAS
nAS OR PS
0x5 : MERGEASNOT
AS OR nPS
0x6 : NOTCOPYAS
nAS
0x7 : NOT
nPS
0x8 : NOTMASKAS
AS NAND PS
0x9 : NOTMERGEAS
AS NOR PS
0xA : XORAS
AS XOR PS
0xB : NOTXORAS
AS XNOR PS
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 8 - 31 (24 bit)
access : read-only
2-level Histogram Parameter Register.
address_offset : 0x2B00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE0 : Black value for 2-level histogram
bits : 0 - 5 (6 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
VALUE1 : White value for 2-level histogram
bits : 8 - 13 (6 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
RSVD : Reserved, always set to zero.
bits : 16 - 31 (16 bit)
access : read-only
4-level Histogram Parameter Register.
address_offset : 0x2B10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE0 : GRAY0 (Black) value for 4-level histogram
bits : 0 - 5 (6 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
VALUE1 : GRAY1 value for 4-level histogram
bits : 8 - 13 (6 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
VALUE2 : GRAY2 value for 4-level histogram
bits : 16 - 21 (6 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 22 - 23 (2 bit)
access : read-only
VALUE3 : GRAY3 (White) value for 4-level histogram
bits : 24 - 29 (6 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
8-level Histogram Parameter 0 Register.
address_offset : 0x2B20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE0 : GRAY0 (Black) value for 8-level histogram
bits : 0 - 5 (6 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
VALUE1 : GRAY1 value for 8-level histogram
bits : 8 - 13 (6 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
VALUE2 : GRAY2 value for 8-level histogram
bits : 16 - 21 (6 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 22 - 23 (2 bit)
access : read-only
VALUE3 : GRAY3 value for 8-level histogram
bits : 24 - 29 (6 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
8-level Histogram Parameter 1 Register.
address_offset : 0x2B30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE4 : GRAY4 value for 8-level histogram
bits : 0 - 5 (6 bit)
access : read-write
RSVD4 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
VALUE5 : GRAY5 value for 8-level histogram
bits : 8 - 13 (6 bit)
access : read-write
RSVD5 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
VALUE6 : GRAY6 value for 8-level histogram
bits : 16 - 21 (6 bit)
access : read-write
RSVD6 : Reserved, always set to zero.
bits : 22 - 23 (2 bit)
access : read-only
VALUE7 : GRAY7 (White) value for 8-level histogram
bits : 24 - 29 (6 bit)
access : read-write
RSVD7 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
16-level Histogram Parameter 0 Register.
address_offset : 0x2B40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE0 : GRAY0 (Black) value for 16-level histogram
bits : 0 - 5 (6 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
VALUE1 : GRAY1 value for 16-level histogram
bits : 8 - 13 (6 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
VALUE2 : GRAY2 value for 16-level histogram
bits : 16 - 21 (6 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 22 - 23 (2 bit)
access : read-only
VALUE3 : GRAY3 value for 16-level histogram
bits : 24 - 29 (6 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
16-level Histogram Parameter 1 Register.
address_offset : 0x2B50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE4 : GRAY4 value for 16-level histogram
bits : 0 - 5 (6 bit)
access : read-write
RSVD4 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
VALUE5 : GRAY5 value for 16-level histogram
bits : 8 - 13 (6 bit)
access : read-write
RSVD5 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
VALUE6 : GRAY6 value for 16-level histogram
bits : 16 - 21 (6 bit)
access : read-write
RSVD6 : Reserved, always set to zero.
bits : 22 - 23 (2 bit)
access : read-only
VALUE7 : GRAY7 value for 16-level histogram
bits : 24 - 29 (6 bit)
access : read-write
RSVD7 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
16-level Histogram Parameter 2 Register.
address_offset : 0x2B60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE8 : GRAY8 value for 16-level histogram
bits : 0 - 5 (6 bit)
access : read-write
RSVD8 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
VALUE9 : GRAY9 value for 16-level histogram
bits : 8 - 13 (6 bit)
access : read-write
RSVD9 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
VALUE10 : GRAY10 value for 16-level histogram
bits : 16 - 21 (6 bit)
access : read-write
RSVD10 : Reserved, always set to zero.
bits : 22 - 23 (2 bit)
access : read-only
VALUE11 : GRAY11 value for 16-level histogram
bits : 24 - 29 (6 bit)
access : read-write
RSVD11 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
16-level Histogram Parameter 3 Register.
address_offset : 0x2B70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE12 : GRAY12 value for 16-level histogram
bits : 0 - 5 (6 bit)
access : read-write
RSVD12 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
VALUE13 : GRAY13 value for 16-level histogram
bits : 8 - 13 (6 bit)
access : read-write
RSVD13 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
VALUE14 : GRAY14 value for 16-level histogram
bits : 16 - 21 (6 bit)
access : read-write
RSVD14 : Reserved, always set to zero.
bits : 22 - 23 (2 bit)
access : read-only
VALUE15 : GRAY15 (White) value for 16-level histogram
bits : 24 - 29 (6 bit)
access : read-write
RSVD15 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
32-level Histogram Parameter 0 Register.
address_offset : 0x2B80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE0 : GRAY0 (Black) value for 32-level histogram
bits : 0 - 5 (6 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
VALUE1 : GRAY1 value for 32-level histogram
bits : 8 - 13 (6 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
VALUE2 : GRAY2 value for 32-level histogram
bits : 16 - 21 (6 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 22 - 23 (2 bit)
access : read-only
VALUE3 : GRAY3 value for 32-level histogram
bits : 24 - 29 (6 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
32-level Histogram Parameter 1 Register.
address_offset : 0x2B90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE4 : GRAY4 value for 32-level histogram
bits : 0 - 5 (6 bit)
access : read-write
RSVD4 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
VALUE5 : GRAY5 value for 32-level histogram
bits : 8 - 13 (6 bit)
access : read-write
RSVD5 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
VALUE6 : GRAY6 value for 32-level histogram
bits : 16 - 21 (6 bit)
access : read-write
RSVD6 : Reserved, always set to zero.
bits : 22 - 23 (2 bit)
access : read-only
VALUE7 : GRAY7 value for 32-level histogram
bits : 24 - 29 (6 bit)
access : read-write
RSVD7 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
32-level Histogram Parameter 2 Register.
address_offset : 0x2BA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE8 : GRAY8 value for 32-level histogram
bits : 0 - 5 (6 bit)
access : read-write
RSVD8 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
VALUE9 : GRAY9 value for 32-level histogram
bits : 8 - 13 (6 bit)
access : read-write
RSVD9 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
VALUE10 : GRAY10 value for 32-level histogram
bits : 16 - 21 (6 bit)
access : read-write
RSVD10 : Reserved, always set to zero.
bits : 22 - 23 (2 bit)
access : read-only
VALUE11 : GRAY11 value for 32-level histogram
bits : 24 - 29 (6 bit)
access : read-write
RSVD11 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
32-level Histogram Parameter 3 Register.
address_offset : 0x2BB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE12 : GRAY12 value for 32-level histogram
bits : 0 - 5 (6 bit)
access : read-write
RSVD12 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
VALUE13 : GRAY13 value for 32-level histogram
bits : 8 - 13 (6 bit)
access : read-write
RSVD13 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
VALUE14 : GRAY14 value for 32-level histogram
bits : 16 - 21 (6 bit)
access : read-write
RSVD14 : Reserved, always set to zero.
bits : 22 - 23 (2 bit)
access : read-only
VALUE15 : GRAY15 (White) value for 32-level histogram
bits : 24 - 29 (6 bit)
access : read-write
RSVD15 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
32-level Histogram Parameter 0 Register.
address_offset : 0x2BC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE16 : GRAY16 (Black) value for 32-level histogram
bits : 0 - 5 (6 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
VALUE17 : GRAY17 value for 32-level histogram
bits : 8 - 13 (6 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
VALUE18 : GRAY18 value for 32-level histogram
bits : 16 - 21 (6 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 22 - 23 (2 bit)
access : read-only
VALUE19 : GRAY19 value for 32-level histogram
bits : 24 - 29 (6 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
32-level Histogram Parameter 1 Register.
address_offset : 0x2BD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE20 : GRAY20 value for 32-level histogram
bits : 0 - 5 (6 bit)
access : read-write
RSVD4 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
VALUE21 : GRAY21 value for 32-level histogram
bits : 8 - 13 (6 bit)
access : read-write
RSVD5 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
VALUE22 : GRAY22 value for 32-level histogram
bits : 16 - 21 (6 bit)
access : read-write
RSVD6 : Reserved, always set to zero.
bits : 22 - 23 (2 bit)
access : read-only
VALUE23 : GRAY23 value for 32-level histogram
bits : 24 - 29 (6 bit)
access : read-write
RSVD7 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
32-level Histogram Parameter 2 Register.
address_offset : 0x2BE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE24 : GRAY24 value for 32-level histogram
bits : 0 - 5 (6 bit)
access : read-write
RSVD8 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
VALUE25 : GRAY25 value for 32-level histogram
bits : 8 - 13 (6 bit)
access : read-write
RSVD9 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
VALUE26 : GRAY26 value for 32-level histogram
bits : 16 - 21 (6 bit)
access : read-write
RSVD10 : Reserved, always set to zero.
bits : 22 - 23 (2 bit)
access : read-only
VALUE27 : GRAY27 value for 32-level histogram
bits : 24 - 29 (6 bit)
access : read-write
RSVD11 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
32-level Histogram Parameter 3 Register.
address_offset : 0x2BF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE28 : GRAY28 value for 32-level histogram
bits : 0 - 5 (6 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 6 - 7 (2 bit)
access : read-only
VALUE29 : GRAY29 value for 32-level histogram
bits : 8 - 13 (6 bit)
access : read-write
RSVD13 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
VALUE30 : GRAY30 value for 32-level histogram
bits : 16 - 21 (6 bit)
access : read-write
RSVD14 : Reserved, always set to zero.
bits : 22 - 23 (2 bit)
access : read-only
VALUE31 : GRAY31 (White) value for 32-level histogram
bits : 24 - 29 (6 bit)
access : read-write
RSVD15 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
PS Background Color 1
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COLOR : Background color (in 24bpp format) for any pixels not within the buffer range specified by the PS ULC/LRC
bits : 0 - 23 (24 bit)
access : read-write
RSVD : Reserved, always set to zero.
bits : 24 - 31 (8 bit)
access : read-only
no description available
address_offset : 0x2C00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Write to 1 to start operation, self-clear
bits : 0 - 0 (1 bit)
access : read-write
RSVD1 : Reserved. This field always reads 0.
bits : 1 - 7 (7 bit)
access : read-only
SW_RESET : Write to 1 to do a software reset to the engine, self-clear.
bits : 8 - 8 (1 bit)
access : read-write
RSVD0 : Reserved. This field always reads 0.
bits : 9 - 31 (23 bit)
access : read-only
no description available
address_offset : 0x2C10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLAG_32B : 1 indicate 32-bit for one pixel, 0 for 16-bit
bits : 0 - 0 (1 bit)
access : read-write
RSVD3 : Reserved. This field always reads 0.
bits : 1 - 3 (3 bit)
access : read-only
FIELD_NUM : indicate how many fields in one pixel,0 for only A;3 for ABCD
bits : 4 - 5 (2 bit)
access : read-write
RSVD2 : Reserved. This field always reads 0.
bits : 6 - 7 (2 bit)
access : read-only
MASK_INDEX : which field is the mask,0 for A, 3 for D
bits : 8 - 9 (2 bit)
access : read-write
RSVD1 : Reserved. This field always reads 0.
bits : 10 - 15 (6 bit)
access : read-only
PIXEL_PITCH_64B : extend each line to be 64-bit aligned
bits : 16 - 25 (10 bit)
access : read-write
ERR_PRONE : step1 write fifo full. If detected, this bit is 1, there is data error in current frame.
bits : 26 - 26 (1 bit)
access : read-only
FIFOFULL : step1 write fifo full
bits : 27 - 27 (1 bit)
access : read-only
RSVD0 : Reserved. This field always reads 0.
bits : 28 - 31 (4 bit)
access : read-only
no description available
address_offset : 0x2C20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A_OFFSET : offset for field A, 0 means A start from bit0
bits : 0 - 4 (5 bit)
access : read-write
A_LEN : length of field A, 0 for 1 byte, 7 for 8 bytes, length of the field plus the length of RLE(*_runlen) should not more than 16-bit
bits : 5 - 7 (3 bit)
access : read-write
B_OFFSET : offset for field B, 0 means B start from bit0
bits : 8 - 12 (5 bit)
access : read-write
B_LEN : length of field B, 0 for 1 byte, 7 for 8 bytes, length of the field plus the length of RLE(*_runlen) should not more than 16-bit
bits : 13 - 15 (3 bit)
access : read-write
C_OFFSET : offset for field C, 0 means C start from bit0
bits : 16 - 20 (5 bit)
access : read-write
C_LEN : length of field C, 0 for 1 byte, 7 for 8 bytes, length of the field plus the length of RLE(*_runlen) should not more than 16-bit
bits : 21 - 23 (3 bit)
access : read-write
D_OFFSET : offset for field D, 0 means D start from bit0
bits : 24 - 28 (5 bit)
access : read-write
D_LEN : length of field D, 0 for 1 byte, 7 for 8 bytes, length of the field plus the length of RLE(*_runlen) should not more than 16-bit
bits : 29 - 31 (3 bit)
access : read-write
no description available
address_offset : 0x2C30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A_RUNLEN : length of the RLE for field A, 12-bit(4095) max
bits : 0 - 3 (4 bit)
access : read-write
B_RUNLEN : length of the RLE for field B, 12-bit(4095) max
bits : 4 - 7 (4 bit)
access : read-write
C_RUNLEN : length of the RLE for field C, 12-bit(4095) max
bits : 8 - 11 (4 bit)
access : read-write
D_RUNLEN : length of the RLE for field D, 12-bit(4095) max
bits : 12 - 15 (4 bit)
access : read-write
RSVD : Reserved. This field always reads 0.
bits : 16 - 31 (16 bit)
access : read-only
no description available
address_offset : 0x2C40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD_MASK_LOW : low 32bit of the valid mask, one of ABCD will be vld_flag,1 left shifted by vld_flag anded with vld_mask will be used to check whether this pixel is valid
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x2C50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD_MASK_HIGH : high 32bit of the valid mask
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x2C60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIXEL_LENGTH : pixel length of the input frame, 4096 max
bits : 0 - 12 (13 bit)
access : read-write
RSVD1 : Reserved. This field always reads 0.
bits : 13 - 15 (3 bit)
access : read-only
PIXEL_WIDTH : pixel width of the input frame, 4096 max
bits : 16 - 28 (13 bit)
access : read-write
RSVD0 : Reserved. This field always reads 0.
bits : 29 - 31 (3 bit)
access : read-only
no description available
address_offset : 0x2C70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE_ADDR : source address of the input frame that located in the memory, should be 32-byte aligned
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x2C80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TARGET_ADDR : taget address of the output frmae that the pxp compress engine should write to the memory, should be 32-byte aligned
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x2C90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A_SRAM_ADDR : sram address used for inter-data saving of A filed,should be 32-bit aligned, SW should make sure the SRAM addr for 4 field will not overlap
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x2CA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B_SRAM_ADDR : sram address used for inter-data saving of B filed,should be 32-bit aligned, SW should make sure the SRAM addr for 4 field will not overlap
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x2CB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C_SRAM_ADDR : sram address used for inter-data saving of C filed,should be 32-bit aligned, SW should make sure the SRAM addr for 4 field will not overlap
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x2CC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_SRAM_ADDR : sram address used for inter-data saving of D filed,should be 32-bit aligned, SW should make sure the SRAM addr for 4 field will not overlap
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x2CD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEBUG_SEL : debug selection
bits : 0 - 7 (8 bit)
access : read-write
DEBUG_VALUE : value of selected debug signal
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x2CE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_SEL : Subblock BUS to AXI MUX, setting 0 to axi0 and setting 1 to axi1
bits : 0 - 7 (8 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 8 - 15 (8 bit)
access : read-only
WR_SEL : Subblock BUS to AXI MUX, setting 0 to axi0 and setting 1 to axi1
bits : 16 - 23 (8 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 24 - 31 (8 bit)
access : read-only
no description available
address_offset : 0x2CF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSK0 : Subblock double buffer handshake signals MUX 0: Ready signal source is from pxp_control; 1: Ready signal source is from pxp_store_wfe_B CH0; 2: Ready signal source is from pxp_store_wfe_B CH1; 3: Ready signal source is from pxp_store_pre_ditering CH0; 4: Ready signal source is from pxp_store_pre_ditering CH1; 5: Ready signal source is from pxp_store_dithering CH0; 6: Ready signal source is from pxp_store_dithering CH1; 7: Ready signal source is from pxp_store_wfe_a CH0; 8: Ready signal source is from pxp_store_wfe_a CH1; 9: Ready signal source is from cpu_fetch_sw0_ready; A: Ready signal source is from cpu_fetch_sw1_ready; B: Ready signal source is from cpu_store_sw0_ready; C: Ready signal source is from cpu_store_sw1_ready;
bits : 0 - 3 (4 bit)
access : read-write
HSK1 : Subblock double buffer handshake signals MUX
bits : 4 - 7 (4 bit)
access : read-write
HSK2 : Subblock double buffer handshake signals MUX
bits : 8 - 11 (4 bit)
access : read-write
HSK3 : Subblock double buffer handshake signals MUX
bits : 12 - 15 (4 bit)
access : read-write
HSK4 : Subblock double buffer handshake signals MUX
bits : 16 - 19 (4 bit)
access : read-write
HSK5 : Subblock double buffer handshake signals MUX
bits : 20 - 23 (4 bit)
access : read-write
HSK6 : Subblock double buffer handshake signals MUX
bits : 24 - 27 (4 bit)
access : read-write
HSK7 : Subblock double buffer handshake signals MUX
bits : 28 - 31 (4 bit)
access : read-write
PS Color Key Low 1
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIXEL : Low range of color key applied to PS buffer
bits : 0 - 23 (24 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 24 - 31 (8 bit)
access : read-only
no description available
address_offset : 0x2D00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSK8 : Subblock double buffer handshake signals MUX
bits : 0 - 3 (4 bit)
access : read-write
HSK9 : Subblock double buffer handshake signals MUX
bits : 4 - 7 (4 bit)
access : read-write
HSK10 : Subblock double buffer handshake signals MUX
bits : 8 - 11 (4 bit)
access : read-write
HSK11 : Subblock double buffer handshake signals MUX
bits : 12 - 15 (4 bit)
access : read-write
HSK12 : Subblock double buffer handshake signals MUX
bits : 16 - 19 (4 bit)
access : read-write
HSK13 : Subblock double buffer handshake signals MUX
bits : 20 - 23 (4 bit)
access : read-write
HSK14 : Subblock double buffer handshake signals MUX
bits : 24 - 27 (4 bit)
access : read-write
HSK15 : Subblock double buffer handshake signals MUX
bits : 28 - 31 (4 bit)
access : read-write
no description available
address_offset : 0x2D10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSK0 : Subblock double buffer handshake signals MUX 0: Done signal source is from LCDIF; 1: Done signal source is from pxp_fetch_input CH0; 2: Done signal source is from pxp_fetch_input CH1; 3: Done signal source is from pxp_fetch_dithering CH0; 4: Done signal source is from pxp_fetch_dithering CH1; 5: Done signal source is from pxp_fetch_wfe_a CH0; 6: Done signal source is from pxp_fetch_wfe_a CH1; 7: Done signal source is from pxp_fetch_wfe_b CH0; 8: Done signal source is from pxp_fetch_wfe_b CH1; 9: Done signal source is from cpu_fetch_sw0_done; A: Done signal source is from cpu_fetch_sw1_done; B: Done signal source is from cpu_store_sw0_done; C: Done signal source is from cpu_store_sw1_done;
bits : 0 - 3 (4 bit)
access : read-write
HSK1 : Subblock double buffer handshake signals MUX
bits : 4 - 7 (4 bit)
access : read-write
HSK2 : Subblock double buffer handshake signals MUX
bits : 8 - 11 (4 bit)
access : read-write
HSK3 : Subblock double buffer handshake signals MUX
bits : 12 - 15 (4 bit)
access : read-write
HSK4 : Subblock double buffer handshake signals MUX
bits : 16 - 19 (4 bit)
access : read-write
HSK5 : Subblock double buffer handshake signals MUX
bits : 20 - 23 (4 bit)
access : read-write
HSK6 : Subblock double buffer handshake signals MUX
bits : 24 - 27 (4 bit)
access : read-write
HSK7 : Subblock double buffer handshake signals MUX
bits : 28 - 31 (4 bit)
access : read-write
no description available
address_offset : 0x2D20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSK8 : Subblock double buffer handshake signals MUX
bits : 0 - 3 (4 bit)
access : read-write
HSK9 : Subblock double buffer handshake signals MUX
bits : 4 - 7 (4 bit)
access : read-write
HSK10 : Subblock double buffer handshake signals MUX
bits : 8 - 11 (4 bit)
access : read-write
HSK11 : Subblock double buffer handshake signals MUX
bits : 12 - 15 (4 bit)
access : read-write
HSK12 : Subblock double buffer handshake signals MUX
bits : 16 - 19 (4 bit)
access : read-write
HSK13 : Subblock double buffer handshake signals MUX
bits : 20 - 23 (4 bit)
access : read-write
HSK14 : Subblock double buffer handshake signals MUX
bits : 24 - 27 (4 bit)
access : read-write
HSK15 : Subblock double buffer handshake signals MUX
bits : 28 - 31 (4 bit)
access : read-write
no description available
address_offset : 0x2D30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW0_B0_READY : PXP b0 buffer ready to CPU
bits : 0 - 0 (1 bit)
access : read-only
SW0_B1_READY : PXP b1 buffer ready to CPU
bits : 1 - 1 (1 bit)
access : read-only
SW0_B0_DONE : CPU b0 buffer done to PXP
bits : 2 - 2 (1 bit)
access : read-write
SW0_B1_DONE : CPU b1 buffer done to PXP
bits : 3 - 3 (1 bit)
access : read-write
SW0_BUF_LINES : Buffer lines for software handshake
bits : 4 - 5 (2 bit)
access : read-only
Enumeration:
0 : LINE_4
Buffer lines is 4 lines.
0x1 : LINE_8
Buffer lines is 8 lines.
0x2 : LINE_16
Buffer lines is 16 lines.
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 6 - 14 (9 bit)
access : read-only
SW0_HSK_EN : Enable software handshake 0 with CPU
bits : 15 - 15 (1 bit)
access : read-write
SW1_B0_READY : PXP b0 buffer ready to CPU
bits : 16 - 16 (1 bit)
access : read-only
SW1_B1_READY : PXP b1 buffer ready to CPU
bits : 17 - 17 (1 bit)
access : read-only
SW1_B0_DONE : CPU b0 buffer done to PXP
bits : 18 - 18 (1 bit)
access : read-write
SW1_B1_DONE : CPU b1 buffer done to PXP
bits : 19 - 19 (1 bit)
access : read-write
SW1_BUF_LINES : Buffer lines for software handshake
bits : 20 - 21 (2 bit)
access : read-only
Enumeration:
0 : LINE_4
Buffer lines is 4 lines.
0x1 : LINE_8
Buffer lines is 8 lines.
0x2 : LINE_16
Buffer lines is 16 lines.
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 22 - 30 (9 bit)
access : read-only
SW1_HSK_EN : Enable software handshake 1 with CPU
bits : 31 - 31 (1 bit)
access : read-write
no description available
address_offset : 0x2D40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW0_B0_READY : PXP b0 buffer ready to CPU
bits : 0 - 0 (1 bit)
access : read-write
SW0_B1_READY : PXP b1 buffer ready to CPU
bits : 1 - 1 (1 bit)
access : read-write
SW0_B0_DONE : CPU b0 buffer done to PXP
bits : 2 - 2 (1 bit)
access : read-only
SW0_B1_DONE : CPU b1 buffer done to PXP
bits : 3 - 3 (1 bit)
access : read-only
SW0_BUF_LINES : Buffer lines for software handshake
bits : 4 - 5 (2 bit)
access : read-only
Enumeration:
0 : LINE_4
Buffer lines is 4 lines.
0x1 : LINE_8
Buffer lines is 8 lines.
0x2 : LINE_16
Buffer lines is 16 lines.
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 6 - 14 (9 bit)
access : read-only
SW0_HSK_EN : Enable software handshake 0 with CPU
bits : 15 - 15 (1 bit)
access : read-write
SW1_B0_READY : PXP b0 buffer ready to CPU
bits : 16 - 16 (1 bit)
access : read-write
SW1_B1_READY : PXP b1 buffer ready to CPU
bits : 17 - 17 (1 bit)
access : read-write
SW1_B0_DONE : CPU b0 buffer done to PXP
bits : 18 - 18 (1 bit)
access : read-only
SW1_B1_DONE : CPU b1 buffer done to PXP
bits : 19 - 19 (1 bit)
access : read-only
SW1_BUF_LINES : Buffer lines for software handshake
bits : 20 - 21 (2 bit)
access : read-only
Enumeration:
0 : LINE_4
Buffer lines is 4 lines.
0x1 : LINE_8
Buffer lines is 8 lines.
0x2 : LINE_16
Buffer lines is 16 lines.
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 22 - 30 (9 bit)
access : read-only
SW1_HSK_EN : Enable software handshake 1 with CPU
bits : 31 - 31 (1 bit)
access : read-write
PS Color Key High 1
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIXEL : High range of color key applied to PS buffer
bits : 0 - 23 (24 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 24 - 31 (8 bit)
access : read-only
Overlay Color Key Low
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIXEL : Low range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable.
bits : 0 - 23 (24 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 24 - 31 (8 bit)
access : read-only
Output Frame Buffer Pointer
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Current address pointer for the output frame buffer
bits : 0 - 31 (32 bit)
access : read-write
Overlay Color Key High
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIXEL : High range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable.
bits : 0 - 23 (24 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 24 - 31 (8 bit)
access : read-only
Control Register 2
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enables PXP secondary data processing flow with specified parameters
bits : 0 - 0 (1 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 1 - 7 (7 bit)
access : read-only
ROTATE0 : Indicates the clockwise rotation to be applied at the output buffer
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ROT_0
ROT_0
0x1 : ROT_90
ROT_90
0x2 : ROT_180
ROT_180
0x3 : ROT_270
ROT_270
End of enumeration elements list.
HFLIP0 : Indicates that the output buffer should be flipped horizontally (effect applied before rotation).
bits : 10 - 10 (1 bit)
access : read-write
VFLIP0 : Indicates that the output buffer should be flipped vertically (effect applied before rotation).
bits : 11 - 11 (1 bit)
access : read-write
ROTATE1 : Indicates the clockwise rotation to be applied at the input buffer
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ROT_0
ROT_0
0x1 : ROT_90
ROT_90
0x2 : ROT_180
ROT_180
0x3 : ROT_270
ROT_270
End of enumeration elements list.
HFLIP1 : Indicates that the input should be flipped horizontally (effect applied before rotation).
bits : 14 - 14 (1 bit)
access : read-write
VFLIP1 : Indicates that the input should be flipped vertically (effect applied before rotation).
bits : 15 - 15 (1 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 16 - 16 (1 bit)
access : read-only
ENABLE_DITHER : Enable the Dithering engine in the PXP secondary processing flow.
bits : 17 - 17 (1 bit)
access : read-write
ENABLE_WFE_A : Enable the WFE-A engine in the PXP secondary processing flow.
bits : 18 - 18 (1 bit)
access : read-write
ENABLE_WFE_B : Enable the WFE-B engine in the PXP secondary processing flow.
bits : 19 - 19 (1 bit)
access : read-write
ENABLE_INPUT_FETCH_STORE : Enable the Input Fetch and Store engine in the PXP secondary processing flow.
bits : 20 - 20 (1 bit)
access : read-write
ENABLE_ALPHA_B : Enable the Alpha-B engine in the PXP secondary processing flow.
bits : 21 - 21 (1 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 22 - 22 (1 bit)
access : read-only
BLOCK_SIZE : Select the block size to process through the Rotate block.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : 8X8
Process 8x8 pixel blocks.
0x1 : 16X16
Process 16x16 pixel blocks.
End of enumeration elements list.
ENABLE_CSC2 : Enable the CSC2 engine in the PXP secondary processing flow.
bits : 24 - 24 (1 bit)
access : read-write
ENABLE_LUT : Enable the LUT engine in the PXP secondary processing flow.
bits : 25 - 25 (1 bit)
access : read-write
ENABLE_ROTATE0 : Enable the ROTATE0 engine in the PXP secondary processing flow.
bits : 26 - 26 (1 bit)
access : read-write
ENABLE_ROTATE1 : Enable the ROTATE1 engine in the PXP secondary processing flow.
bits : 27 - 27 (1 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 28 - 31 (4 bit)
access : read-only
PXP Power Control Register.
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LUT_LP_STATE_WAY0_BANK0 : Select the low power state of the LUT's WAY0-BANK0 memory.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
Memory is not in low power state.
0x1 : LS
Light Sleep Mode. Low leakage mode, maintain memory contents.
0x2 : DS
Deep Sleep Mode. Low leakage mode, maintain memory contents.
0x4 : SD
Shut Down Mode. Shut Down periphery and core, no memory retention.
End of enumeration elements list.
LUT_LP_STATE_WAY0_BANKN : Select the low power state of the LUT's WAY0-BANK1,2,3 memory.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : NONE
Memory is not in low power state.
0x1 : LS
Light Sleep Mode. Low leakage mode, maintain memory contents.
0x2 : DS
Deep Sleep Mode. Low leakage mode, maintain memory contents.
0x4 : SD
Shut Down Mode. Shut Down periphery and core, no memory retention.
End of enumeration elements list.
LUT_LP_STATE_WAY1_BANKN : Select the low power state of the LUT's WAY0-BANK0,1,2,3 memory.
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : NONE
Memory is not in low power state.
0x1 : LS
Light Sleep Mode. Low leakage mode, maintain memory contents.
0x2 : DS
Deep Sleep Mode. Low leakage mode, maintain memory contents.
0x4 : SD
Shut Down Mode. Shut Down periphery and core, no memory retention.
End of enumeration elements list.
ROT0_MEM_LP_STATE : Select the low power state of the ROT 0 memory.
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : NONE
Memory is not in low power state.
0x1 : LS
Light Sleep Mode. Low leakage mode, maintain memory contents.
0x2 : DS
Deep Sleep Mode. Low leakage mode, maintain memory contents.
0x4 : SD
Shut Down Mode. Shut Down periphery and core, no memory retention.
End of enumeration elements list.
CTRL : This register contains power control for the PXP.
bits : 12 - 31 (20 bit)
access : read-write
PXP Power Control Register 1.
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROT1_MEM_LP_STATE : Select the low power state of the ROT 1 memory.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
Memory is not in low power state.
0x1 : LS
Light Sleep Mode. Low leakage mode, maintain memory contents.
0x2 : DS
Deep Sleep Mode. Low leakage mode, maintain memory contents.
0x4 : SD
Shut Down Mode. Shut Down periphery and core, no memory retention.
End of enumeration elements list.
DITH0_LUT_MEM_LP_STATE : Select the low power state of the dither0 LUT memory.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : NONE
Memory is not in low power state.
0x1 : LS
Light Sleep Mode. Low leakage mode, maintain memory contents.
0x2 : DS
Deep Sleep Mode. Low leakage mode, maintain memory contents.
0x4 : SD
Shut Down Mode. Shut Down periphery and core, no memory retention.
End of enumeration elements list.
DITH0_ERR0_MEM_LP_STATE : Select the low power state of the dither0 ERR0 memory.
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : NONE
Memory is not in low power state.
0x1 : LS
Light Sleep Mode. Low leakage mode, maintain memory contents.
0x2 : DS
Deep Sleep Mode. Low leakage mode, maintain memory contents.
0x4 : SD
Shut Down Mode. Shut Down periphery and core, no memory retention.
End of enumeration elements list.
DITH0_ERR1_MEM_LP_STATE : Select the low power state of the dither0 ERR1 memory.
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : NONE
Memory is not in low power state.
0x1 : LS
Light Sleep Mode. Low leakage mode, maintain memory contents.
0x2 : DS
Deep Sleep Mode. Low leakage mode, maintain memory contents.
0x4 : SD
Shut Down Mode. Shut Down periphery and core, no memory retention.
End of enumeration elements list.
DITH1_LUT_MEM_LP_STATE : Select the low power state of the dither1 LUT memory.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : NONE
Memory is not in low power state.
0x1 : LS
Light Sleep Mode. Low leakage mode, maintain memory contents.
0x2 : DS
Deep Sleep Mode. Low leakage mode, maintain memory contents.
0x4 : SD
Shut Down Mode. Shut Down periphery and core, no memory retention.
End of enumeration elements list.
DITH2_LUT_MEM_LP_STATE : Select the low power state of the dither2 LUT memory.
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
0 : NONE
Memory is not in low power state.
0x1 : LS
Light Sleep Mode. Low leakage mode, maintain memory contents.
0x2 : DS
Deep Sleep Mode. Low leakage mode, maintain memory contents.
0x4 : SD
Shut Down Mode. Shut Down periphery and core, no memory retention.
End of enumeration elements list.
ALU_A_MEM_LP_STATE : Select the low power state of the ALU A memory.
bits : 18 - 20 (3 bit)
access : read-write
Enumeration:
0 : NONE
Memory is not in low power state.
0x1 : LS
Light Sleep Mode. Low leakage mode, maintain memory contents.
0x2 : DS
Deep Sleep Mode. Low leakage mode, maintain memory contents.
0x4 : SD
Shut Down Mode. Shut Down periphery and core, no memory retention.
End of enumeration elements list.
ALU_B_MEM_LP_STATE : Select the low power state of the ALU B memory.
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0 : NONE
Memory is not in low power state.
0x1 : LS
Light Sleep Mode. Low leakage mode, maintain memory contents.
0x2 : DS
Deep Sleep Mode. Low leakage mode, maintain memory contents.
0x4 : SD
Shut Down Mode. Shut Down periphery and core, no memory retention.
End of enumeration elements list.
RSVD0 : This register contains power control for the PXP.
bits : 24 - 31 (8 bit)
access : read-only
no description available
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX16_SEL : This mux chooses the data path through MUX 16.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : 0
Output of ALU A Engine
0x1 : 1
histogram_pixel output from output
0x2 : 2
Output of ALU B Engine
0x3 : 3
No output
End of enumeration elements list.
MUX17_SEL : This field chooses the data path through MUX 17.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : 0
Output of ALU A
0x1 : 1
Output of ALU B
0x2 : 2
No output
0x3 : 3
No Output
End of enumeration elements list.
RSVD0 : Reserved. This field always reads 0.
bits : 4 - 31 (28 bit)
access : read-only
Initialize memory buffer control Register
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Base address to start writing
bits : 0 - 15 (16 bit)
access : read-write
RSVD0 : Reserved.
bits : 16 - 26 (11 bit)
access : read-only
SELECT : Select which memory to write.
bits : 27 - 30 (4 bit)
access : read-write
Enumeration:
0 : DITHER0_LUT
Select the LUT memory for access
0x1 : DITHER0_ERR0
Select the ERR0 memory for access
0x2 : DITHER0_ERR1
Select the ERR1 memory for access
0x3 : DITHER1_LUT
Select the LUT memory for access
0x4 : DITHER2_LUT
Select the LUT memory for access
0x5 : ALU_A
Select the ALU instr memory for access
0x6 : ALU_B
Select the ALU instr memory for access
0x7 : WFE_A_FETCH
Select the WFE-A fetch memory for access
0x8 : WFE_B_FETCH
Select the WFE-B fetch memory for access
End of enumeration elements list.
START : Enable writing to the memory.
bits : 31 - 31 (1 bit)
access : read-write
Write data Register
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data value to be written to the memory
bits : 0 - 31 (32 bit)
access : read-write
Write data Register
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data value to be written to the most significant 32 bits of the fetch memories
bits : 0 - 31 (32 bit)
access : read-write
PXP IRQ Mask Register
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIRST_CH0_PREFETCH_IRQ_EN : Enable First ch0 prefetch engine interrupt detection
bits : 0 - 0 (1 bit)
access : read-write
FIRST_CH1_PREFETCH_IRQ_EN : Enable First ch1 prefetch engine interrupt detection
bits : 1 - 1 (1 bit)
access : read-write
FIRST_CH0_STORE_IRQ_EN : Enable First ch0 store engine interrupt detection
bits : 2 - 2 (1 bit)
access : read-write
FIRST_CH1_STORE_IRQ_EN : Enable First ch1 store engine interrupt detection
bits : 3 - 3 (1 bit)
access : read-write
DITHER_CH0_PREFETCH_IRQ_EN : Enable Dither ch0 prefetch engine interrupt detection
bits : 4 - 4 (1 bit)
access : read-write
DITHER_CH1_PREFETCH_IRQ_EN : Enable Dither ch1 prefetch engine interrupt detection
bits : 5 - 5 (1 bit)
access : read-write
DITHER_CH0_STORE_IRQ_EN : Enable dither ch0 store engine interrupt detection.
bits : 6 - 6 (1 bit)
access : read-write
DITHER_CH1_STORE_IRQ_EN : Enable dither ch1 store engine interrupt detection.
bits : 7 - 7 (1 bit)
access : read-write
WFE_A_CH0_STORE_IRQ_EN : Enable WFE A ch0 store engine interrupt detection.
bits : 8 - 8 (1 bit)
access : read-write
WFE_A_CH1_STORE_IRQ_EN : Enable WFE A ch1 store engine interrupt detection.
bits : 9 - 9 (1 bit)
access : read-write
WFE_B_CH0_STORE_IRQ_EN : Enable WFE B ch0 store engine interrupt detection.
bits : 10 - 10 (1 bit)
access : read-write
WFE_B_CH1_STORE_IRQ_EN : Enable WFE B ch1 store engine interrupt detection.
bits : 11 - 11 (1 bit)
access : read-write
FIRST_STORE_IRQ_EN : Enable First store engine interrupt detection
bits : 12 - 12 (1 bit)
access : read-write
DITHER_STORE_IRQ_EN : Enable dither store engine interrupt detection.
bits : 13 - 13 (1 bit)
access : read-write
WFE_A_STORE_IRQ_EN : Enable WFE A store engine interrupt detection.
bits : 14 - 14 (1 bit)
access : read-write
WFE_B_STORE_IRQ_EN : Enable WFE B store engine interrupt detection.
bits : 15 - 15 (1 bit)
access : read-write
RSVD1 : Reserved.
bits : 16 - 30 (15 bit)
access : read-only
COMPRESS_DONE_IRQ_EN : Enable compression done interrupt detection.
bits : 31 - 31 (1 bit)
access : read-write
PXP Interrupt Register
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIRST_CH0_PREFETCH_IRQ : Initial ch0 prefetch engine interrupt
bits : 0 - 0 (1 bit)
access : read-write
FIRST_CH1_PREFETCH_IRQ : Initial ch1 prefetch engine interrupt
bits : 1 - 1 (1 bit)
access : read-write
FIRST_CH0_STORE_IRQ : Initial ch0 store engine interrupt
bits : 2 - 2 (1 bit)
access : read-write
FIRST_CH1_STORE_IRQ : Initial ch1 store engine interrupt
bits : 3 - 3 (1 bit)
access : read-write
DITHER_CH0_PREFETCH_IRQ : Dither ch0 prefetch engine interrupt
bits : 4 - 4 (1 bit)
access : read-write
DITHER_CH1_PREFETCH_IRQ : Dither ch1 prefetch engine interrupt
bits : 5 - 5 (1 bit)
access : read-write
DITHER_CH0_STORE_IRQ : Dither ch0 store engine Interrupt
bits : 6 - 6 (1 bit)
access : read-write
DITHER_CH1_STORE_IRQ : Dither ch1 store engine Interrupt
bits : 7 - 7 (1 bit)
access : read-write
WFE_A_CH0_STORE_IRQ : WFE A ch0 store engine Interrupt.
bits : 8 - 8 (1 bit)
access : read-write
WFE_A_CH1_STORE_IRQ : WFE A ch1 store engine Interrupt.
bits : 9 - 9 (1 bit)
access : read-write
WFE_B_CH0_STORE_IRQ : WFE B ch0 store engine Interrupt
bits : 10 - 10 (1 bit)
access : read-write
WFE_B_CH1_STORE_IRQ : WFE B ch1 store engine Interrupt
bits : 11 - 11 (1 bit)
access : read-write
FIRST_STORE_IRQ : Initial store engine interrupt
bits : 12 - 12 (1 bit)
access : read-write
DITHER_STORE_IRQ : Dither store engine Interrupt
bits : 13 - 13 (1 bit)
access : read-write
WFE_A_STORE_IRQ : WFE A store engine Interrupt.
bits : 14 - 14 (1 bit)
access : read-write
WFE_B_STORE_IRQ : WFE B store engine Interrupt
bits : 15 - 15 (1 bit)
access : read-write
RSVD1 : Reserved.
bits : 16 - 30 (15 bit)
access : read-only
COMPRESS_DONE_IRQ : compression done Interrupt
bits : 31 - 31 (1 bit)
access : read-write
Output Frame Buffer Pointer #2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Current address pointer for the output frame buffer
bits : 0 - 31 (32 bit)
access : read-write
Next Frame Pointer
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLED : Indicates that the "next frame" functionality has been enabled
bits : 0 - 0 (1 bit)
access : read-only
RSVD : Reserved, always set to zero.
bits : 1 - 1 (1 bit)
access : read-only
POINTER : A pointer to a data structure containing register values to be used when processing the next frame
bits : 2 - 31 (30 bit)
access : read-write
Pre-fetch engine Control Channel 0 Register
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_EN : Channel enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
Prefetch function is disable
0x1 : 1
Prefetch function is enable
End of enumeration elements list.
BLOCK_EN : Choses the prefetch mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : 0
Prefetch in scan mode
0x1 : 1
Prefetch in block mode
End of enumeration elements list.
BLOCK_16 : Determines the block sixe.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : 8x8
Block size is 8x8
0x1 : 16x16
Block size is 16x16
End of enumeration elements list.
HANDSHAKE_EN : Enable bit for handshake with the store engine.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : 0
Handshake with the store engine is disabled
0x1 : 1
Handshake with the store engine is enabled
End of enumeration elements list.
BYPASS_PIXEL_EN : Selects Channel 0 pixel source
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : 0
Channel 0 is from memory
0x1 : 1
Channel 0 is from previous process engine
End of enumeration elements list.
HIGH_BYTE : channel 0 high byte selection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : 0
In 64 bit mode, the output high byte will use channel1.
0x1 : 1
In 64 bit mode, the output high byte will use channel0
End of enumeration elements list.
RSVD4 : Reserved, always set to zero.
bits : 6 - 8 (3 bit)
access : read-only
HFLIP : Enables HFLIP.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : 0
HFLIP disable
0x1 : 1
VFLIP enable
End of enumeration elements list.
VFLIP : Enables VFLIP
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : 0
VFLIP disable
0x1 : 1
VFLIP enable
End of enumeration elements list.
RSVD3 : Reserved, always set to zero.
bits : 11 - 11 (1 bit)
access : read-only
ROTATION_ANGLE : no description available
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ROT_0
Rotate image by 0 degrees.
0x1 : ROT_90
Rotate image by 90 degrees.
0x2 : ROT_180
Rotate image by 180 degrees.
0x3 : ROT_270
Rotate image by 270 degrees.
End of enumeration elements list.
RSVD2 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
RD_NUM_BYTES : Bytes in a read burst
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : 8_bytes
8 bytes.
0x1 : 16_bytes
16 bytes.
0x2 : 32_bytes
32 bytes.
0x3 : 64_bytes
64 bytes.
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 18 - 23 (6 bit)
access : read-only
HANDSHAKE_SCAN_LINE_NUM : scan handshake line number
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : 0
1 line.
0x1 : 1
8 lines
0x2 : 2
16 lines
0x3 : 3
16 lines
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 26 - 30 (5 bit)
access : read-only
ARBIT_EN : Enables Arbitration
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : 0
Arbitration disable. If using 2 channels, will output 2 axi bus sets.
0x1 : 1
Arbitration enable. If using 2 channel, will only output 1 axi bus sets
End of enumeration elements list.
Pre-fetch engine Control Channel 1 Register
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_EN : Channel enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
prefetch function is disable
0x1 : 1
prefetch function is enable
End of enumeration elements list.
BLOCK_EN : Choses the prefetch mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : 0
Prefetch in scan mode
0x1 : 1
Prefetch in block mode
End of enumeration elements list.
BLOCK_16 : Determines the block sixe.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : 8x8
Block size is 8x8
0x1 : 16x16
Block size is 16x16
End of enumeration elements list.
HANDSHAKE_EN : Enable bit for handshake with the store engine.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : 0
Handshake with the store engine is disabled
0x1 : 1
Handshake with the store engine is enabled
End of enumeration elements list.
BYPASS_PIXEL_EN : Selects Channel 1 pixel source
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : 0
Channel 1 is from memory
0x1 : 1
Channel 1 is from previous process engine
End of enumeration elements list.
RSVD4 : Reserved, always set to zero.
bits : 5 - 8 (4 bit)
access : read-only
HFLIP : Enables HFLIP.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : 0
HFLIP disable
0x1 : 1
VFLIP enable
End of enumeration elements list.
VFLIP : Enables VFLIP
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : 0
VFLIP disable
0x1 : 1
VFLIP enable
End of enumeration elements list.
RSVD3 : Reserved, always set to zero.
bits : 11 - 11 (1 bit)
access : read-only
ROTATION_ANGLE : no description available
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ROT_0
Rotate image by 0 degrees.
0x1 : ROT_90
Rotate image by 90 degrees.
0x2 : ROT_180
Rotate image by 180 degrees.
0x3 : ROT_270
Rotate image by 270 degrees.
End of enumeration elements list.
RSVD2 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
RD_NUM_BYTES : Bytes in a read burst
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : 8_bytes
8 bytes.
0x1 : 16_bytes
16 bytes.
0x2 : 32_bytes
32 bytes.
0x3 : 64_bytes
64 bytes.
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 18 - 23 (6 bit)
access : read-only
HANDSHAKE_SCAN_LINE_NUM : scan handshake line number
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : 0
1 line.
0x1 : 1
8 lines
0x2 : 2
16 lines
0x3 : 3
16 lines
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 26 - 31 (6 bit)
access : read-only
Pre-fetch engine status Channel 0 Register
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREFETCH_BLOCK_X : When in scan mode, this field is always 0
bits : 0 - 15 (16 bit)
access : read-only
PREFETCH_BLOCK_Y : When in scan mode, this field indicates the current Y coordinate of the frame
bits : 16 - 31 (16 bit)
access : read-only
Store engine status Channel 1 Register
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREFETCH_BLOCK_X : When in scan mode, this field is always 0
bits : 0 - 15 (16 bit)
access : read-only
PREFETCH_BLOCK_Y : When in scan mode, this field indicates the current Y coordinate of the frame
bits : 16 - 31 (16 bit)
access : read-only
no description available
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE_SIZE_ULC_X : This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory
bits : 0 - 15 (16 bit)
access : read-write
ACTIVE_SIZE_ULC_Y : This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE_SIZE_LRC_X : This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory
bits : 0 - 15 (16 bit)
access : read-write
ACTIVE_SIZE_LRC_Y : This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE_SIZE_ULC_X : This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory
bits : 0 - 15 (16 bit)
access : read-write
ACTIVE_SIZE_ULC_Y : This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE_SIZE_LRC_X : This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory
bits : 0 - 15 (16 bit)
access : read-write
ACTIVE_SIZE_LRC_Y : This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_TOTAL_WIDTH : actual total width -1
bits : 0 - 15 (16 bit)
access : read-write
INPUT_TOTAL_HEIGHT : actual total height - 1
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_TOTAL_WIDTH : actual total width -1
bits : 0 - 15 (16 bit)
access : read-write
INPUT_TOTAL_HEIGHT : actual total height -1
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKGROUND_COLOR : background color(in 32bpp format) for any pixels not within the bufffer range specified by the ULC/LRC
bits : 0 - 31 (32 bit)
access : read-write
Output Buffer Pitch
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PITCH : Indicates the number of bytes in memory between two vertically adjacent pixels.
bits : 0 - 15 (16 bit)
access : read-write
RSVD : Reserved, always set to zero.
bits : 16 - 31 (16 bit)
access : read-only
no description available
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKGROUND_COLOR : background color(in 32bpp format) for any pixels not within the bufffer range specified by the ULC/LRC
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_INPUT_PITCH : This field indicates the channel 0 input pitch
bits : 0 - 15 (16 bit)
access : read-write
CH1_INPUT_PITCH : This field indicates the channel 1 input pitch
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_ACTIVE_BPP : no description available
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : 0
8 bits
0x1 : 1
16 bits
0x2 : 2
32 bits
0x3 : 3
32 bits
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 2 - 7 (6 bit)
access : read-only
EXPAND_FORMAT : Select Pixel format
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : 0
RGB 565
0x1 : 1
RGB 555
0x2 : 2
ARGB 1555
0x3 : 3
RGB 444
0x4 : 4
ARGB 4444
0x5 : 5
YUYV/YVYU
0x6 : 6
UYVY/VYUY
0x7 : 7
YUV422_2P
End of enumeration elements list.
EXPAND_EN : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : 0
channel0 format expanding disable
0x1 : 1
channel0 format expanding enable
End of enumeration elements list.
SHIFT_BYPASS : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : 0
channel0 data will do shift function
0x1 : 1
channel0 will bypass shift function
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 13 - 31 (19 bit)
access : read-only
no description available
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_ACTIVE_BPP : no description available
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : 0
8 bits
0x1 : 1
16 bits
0x2 : 2
32 bits
0x3 : 3
32 bits
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 2 - 7 (6 bit)
access : read-only
EXPAND_FORMAT : Select Pixel format
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : 0
RGB 565
0x1 : 1
RGB 555
0x2 : 2
ARGB 1555
0x3 : 3
RGB 444
0x4 : 4
ARGB 4444
0x5 : 5
YUYV/YVYU
0x6 : 6
UYVY/VYUY
0x7 : 7
YUV422_2P
End of enumeration elements list.
EXPAND_EN : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : 0
channel1 format expanding disable
0x1 : 1
channel1 format expanding enable
End of enumeration elements list.
SHIFT_BYPASS : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : 0
channel1 data will do shift function
0x1 : 1
channel1 will bypass shift function
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 13 - 31 (19 bit)
access : read-only
no description available
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET0 : Shift Offset for channel 0 componnent 0.
bits : 0 - 4 (5 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 5 - 7 (3 bit)
access : read-only
OFFSET1 : Shift Offset for channel 0 componnent 1.
bits : 8 - 12 (5 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 13 - 15 (3 bit)
access : read-only
OFFSET2 : Shift Offset for channel 0 componnent 2.
bits : 16 - 20 (5 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 21 - 23 (3 bit)
access : read-only
OFFSET3 : Shift Offset for channel 0 componnent 3.
bits : 24 - 28 (5 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 29 - 31 (3 bit)
access : read-only
no description available
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET0 : Shift Offset for channel 1 componnent 0.
bits : 0 - 4 (5 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 5 - 7 (3 bit)
access : read-only
OFFSET1 : Shift Offset for channel 1 componnent 1.
bits : 8 - 12 (5 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 13 - 15 (3 bit)
access : read-only
OFFSET2 : Shift Offset for channel 1 componnent 2.
bits : 16 - 20 (5 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 21 - 23 (3 bit)
access : read-only
OFFSET3 : Shift Offset for channel 1 componnent 3.
bits : 24 - 28 (5 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 29 - 31 (3 bit)
access : read-only
no description available
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH0 : Shift Width for channel 0 componnent 0.
bits : 0 - 3 (4 bit)
access : read-write
WIDTH1 : Shift Width for channel 0 componnent 1.
bits : 4 - 7 (4 bit)
access : read-write
WIDTH2 : Shift Width for channel 0 componnent 2.
bits : 8 - 11 (4 bit)
access : read-write
WIDTH3 : Shift Width for channel 0 componnent 3.
bits : 12 - 15 (4 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 16 - 31 (16 bit)
access : read-only
no description available
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH0 : Shift Width for channel 1 componnent 0.
bits : 0 - 3 (4 bit)
access : read-write
WIDTH1 : Shift Width for channel 1 componnent 1.
bits : 4 - 7 (4 bit)
access : read-write
WIDTH2 : Shift Width for channel 1 componnent 2.
bits : 8 - 11 (4 bit)
access : read-write
WIDTH3 : Shift Width for channel 1 componnent 3.
bits : 12 - 15 (4 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 16 - 31 (16 bit)
access : read-only
no description available
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_BASE_ADDR0 : input base address0
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_BASE_ADDR1 : input base address1
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_BASE_ADDR0 : input base address0
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_BASE_ADDR1 : input base address1
bits : 0 - 31 (32 bit)
access : read-write
Store engine Control Channel 0 Register
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_EN : Channel enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
Store function is disable
0x1 : 1
Store function is enable
End of enumeration elements list.
BLOCK_EN : Choses the store mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : 0
Store in scan mode
0x1 : 1
Store in block mode
End of enumeration elements list.
BLOCK_16 : Determines the block sixe.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : 8x8
Block size is 8x8
0x1 : 16x16
Block size is 16x16
End of enumeration elements list.
HANDSHAKE_EN : Enable bit for handshake with the store engine.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : 0
Handshake with the prefetch engine is disabled
0x1 : 1
Handshake with the prefetch engine is enabled
End of enumeration elements list.
ARRAY_EN : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : 0
Array Handshake Disabled
0x1 : 1
Array Handshake Enabled
End of enumeration elements list.
ARRAY_LINE_NUM : Selects Array Size
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : 0
Using 1x1 Array
0x1 : 1
Using 3x3 Array
0x2 : 2
Using 5x5 Array
0x3 : 3
Using 5x5 Array
End of enumeration elements list.
RSVD3 : Reserved, always set to zero.
bits : 7 - 7 (1 bit)
access : read-only
STORE_BYPASS_EN : store bypass enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : 0
store bypass mode disable.
0x1 : 1
store bypass mode enable. Data will bypass to store output.
End of enumeration elements list.
STORE_MEMORY_EN : store memory enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : 0
store memory mode disable.
0x1 : 1
store memory mode enable. Data will store to memory
End of enumeration elements list.
PACK_IN_SEL : pack_in_sel
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : 0
select 64 shift out data to pack
0x1 : 1
select low 32 bit shift out data to pack
End of enumeration elements list.
FILL_DATA_EN : fill data enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : 0
Fill data mode disable.
0x1 : 1
Fill data mode enable. When using fill_data mode, store_engine will store fixed data defined in fill_data register
End of enumeration elements list.
RSVD2 : Reserved, always set to zero.
bits : 12 - 15 (4 bit)
access : read-only
WR_NUM_BYTES : Bytes in a write burst
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : 8_bytes
8 bytes
0x1 : 16_bytes
16 bytes
0x2 : 32_bytes
32 bytes
0x3 : 64_bytes
64 bytes
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 18 - 23 (6 bit)
access : read-only
COMBINE_2CHANNEL : Combine 2 channel Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : 0
combine 2 channel disable
0x1 : 1
combine 2 channel enable
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 25 - 30 (6 bit)
access : read-only
ARBIT_EN : Arbitration Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : 0
Arbitration disable. If using 2 channels, will output 2 axi bus sets
0x1 : 1
Arbitration enable. If using 2 channel, will only output 1 axi bus sets
End of enumeration elements list.
Store engine Control Channel 1 Register
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_EN : Channel enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
Store function is disable
0x1 : 1
Store function is enable
End of enumeration elements list.
BLOCK_EN : Choses the store mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : 0
Store in scan mode
0x1 : 1
Store in block mode
End of enumeration elements list.
BLOCK_16 : Determines the block sixe.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : 8x8
Block size is 8x8
0x1 : 16x16
Block size is 16x16
End of enumeration elements list.
HANDSHAKE_EN : Enable bit for handshake with the fetch engine.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : 0
Handshake with the fetch engine is disabled
0x1 : 1
Handshake with the fetch engine is enabled
End of enumeration elements list.
ARRAY_EN : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : 0
Array Handshake Disabled
0x1 : 1
Array Handshake Enabled
End of enumeration elements list.
ARRAY_LINE_NUM : Selects Array Size
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : 0
Using 1x1 Array
0x1 : 1
Using 3x3 Array
0x2 : 2
Using 5x5 Array
0x3 : 3
Using 5x5 Array
End of enumeration elements list.
RSVD3 : Reserved, always set to zero.
bits : 7 - 7 (1 bit)
access : read-only
STORE_BYPASS_EN : enable bit for store bypass
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : 0
store bypass mode disable.
0x1 : 1
store bypass mode enable. Data will bypass to store output.
End of enumeration elements list.
STORE_MEMORY_EN : store memory enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : 0
store memory mode disable.
0x1 : 1
store memory mode enable. Data will store to memory.
End of enumeration elements list.
PACK_IN_SEL : pack_in_sel
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : 0
select 64 shift out data to pack
0x1 : 1
select channel 0 high 32 bit shift out data to pack
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 11 - 15 (5 bit)
access : read-only
WR_NUM_BYTES : Bytes in a write burst
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : 8_bytes
8 bytes
0x1 : 16_bytes
16 bytes
0x2 : 32_bytes
32 bytes
0x3 : 64_bytes
64 bytes
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 18 - 31 (14 bit)
access : read-only
Store engine status Channel 0 Register
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STORE_BLOCK_X : When in scan mode, this field is always 0
bits : 0 - 15 (16 bit)
access : read-only
STORE_BLOCK_Y : When in scan mode, this field indicates the current Y coordinate of the frame
bits : 16 - 31 (16 bit)
access : read-only
Store engine status Channel 1 Register
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STORE_BLOCK_X : When in scan mode, this field is always 0
bits : 0 - 15 (16 bit)
access : read-only
STORE_BLOCK_Y : When in scan mode, this field indicates the current Y coordinate of the frame
bits : 16 - 31 (16 bit)
access : read-only
Output Surface Lower Right Coordinate
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Y : Indicates the number of vertical PIXELS in the output surface (non-rotated)
bits : 0 - 13 (14 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
X : Indicates number of horizontal PIXELS in the output surface (non-rotated)
bits : 16 - 29 (14 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
no description available
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_WIDTH : actual output width -1
bits : 0 - 15 (16 bit)
access : read-write
OUT_HEIGHT : actual output height -1
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_WIDTH : actual output width -1
bits : 0 - 15 (16 bit)
access : read-write
OUT_HEIGHT : actual output height -1
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_OUT_PITCH : This field indicates the channel 0 input pitch
bits : 0 - 15 (16 bit)
access : read-write
CH1_OUT_PITCH : This field indicates the channel 1 input pitch
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD2 : Reserved, always set to zero.
bits : 0 - 1 (2 bit)
access : read-only
OUTPUT_ACTIVE_BPP : no description available
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : 0
8 bits
0x1 : 1
16 bits
0x2 : 2
32 bits
0x3 : 3
32 bits
End of enumeration elements list.
OUT_YUV422_1P_EN : Enable for YUV422 1 plane
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : 0
YUYV422 2 plane disabled.
0x1 : 1
YUYV422 2 plane enabled.
End of enumeration elements list.
OUT_YUV422_2P_EN : Enable for YUV422 2 plane
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : 0
YUYV422 2 plane disabled.
0x1 : 1
YUYV422 2 plane enabled.
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 6 - 6 (1 bit)
access : read-only
SHIFT_BYPASS : CH0 shift bypass
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : 0
data will do shift processing.
0x1 : 1
data will bypass shift module.
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD2 : Reserved, always set to zero.
bits : 0 - 1 (2 bit)
access : read-only
OUTPUT_ACTIVE_BPP : no description available
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : 0
8 bits
0x1 : 1
16 bits
0x2 : 2
32 bits
0x3 : 3
32 bits
End of enumeration elements list.
OUT_YUV422_1P_EN : Enable for YUV422 1 plane
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : 0
YUYV422 2 plane disabled.
0x1 : 1
YUYV422 2 plane enabled.
End of enumeration elements list.
OUT_YUV422_2P_EN : Enable for YUV422 2 plane
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : 0
YUYV422 2 plane disabled.
0x1 : 1
YUYV422 2 plane enabled.
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 6 - 31 (26 bit)
access : read-only
no description available
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_BASE_ADDR0 : input base address0
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_BASE_ADDR1 : input base address1
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x6B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILL_DATA_CH0 : when using fill_data mode,store engine channel0 will store the fill_data value defined here.
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x6C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_BASE_ADDR0 : input base address0
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_BASE_ADDR1 : input base address1
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x6E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK0_H_CH0 : data mask0 high byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x6F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK0_L_CH0 : data mask0 low byte
bits : 0 - 31 (32 bit)
access : read-write
Processed Surface Upper Left Coordinate
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Y : This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output buffer
bits : 0 - 13 (14 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
X : This field indicates the upper left X-coordinate (in pixels) of the processed surface (PS) in the output buffer
bits : 16 - 29 (14 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
no description available
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK1_H_CH0 : data mask1 high byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK1_L_CH0 : data mask1 low byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK2_H_CH0 : data mask2 high byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK2_L_CH0 : data mask2 low byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK3_H_CH0 : data mask3 high byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK3_L_CH0 : data mask3 low byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x760 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK4_H_CH0 : data mask4 high byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK4_L_CH0 : data mask4 low byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK5_H_CH0 : data mask5 high byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK5_L_CH0 : data mask5 low byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK6_H_CH0 : data mask6 high byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK6_L_CH0 : data mask6 low byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK7_H_CH0 : data mask7 high byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x7E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK7_L_CH0 : data mask7 low byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_SHIFT_WIDTH0 : data shift width 0
bits : 0 - 5 (6 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 6 - 6 (1 bit)
access : read-only
D_SHIFT_FLAG0 : data shift flag 0
bits : 7 - 7 (1 bit)
access : read-write
D_SHIFT_WIDTH1 : data shift width 1
bits : 8 - 13 (6 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 14 - 14 (1 bit)
access : read-only
D_SHIFT_FLAG1 : data shift flag 1
bits : 15 - 15 (1 bit)
access : read-write
D_SHIFT_WIDTH2 : data shift width 2
bits : 16 - 21 (6 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 22 - 22 (1 bit)
access : read-only
D_SHIFT_FLAG2 : data shift flag 2
bits : 23 - 23 (1 bit)
access : read-write
D_SHIFT_WIDTH3 : data shift width 3
bits : 24 - 29 (6 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 30 - 30 (1 bit)
access : read-only
D_SHIFT_FLAG3 : data shift flag 3
bits : 31 - 31 (1 bit)
access : read-write
Processed Surface Lower Right Coordinate
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Y : This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer
bits : 0 - 13 (14 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
X : This field indicates the lower right X-coordinate (in pixels) of the processed surface (PS) in the output frame buffer
bits : 16 - 29 (14 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
no description available
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_SHIFT_WIDTH4 : data shift width 4
bits : 0 - 5 (6 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 6 - 6 (1 bit)
access : read-only
D_SHIFT_FLAG4 : data shift flag 4
bits : 7 - 7 (1 bit)
access : read-write
D_SHIFT_WIDTH5 : data shift width 5
bits : 8 - 13 (6 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 14 - 14 (1 bit)
access : read-only
D_SHIFT_FLAG5 : data shift flag 5
bits : 15 - 15 (1 bit)
access : read-write
D_SHIFT_WIDTH6 : data shift width 6
bits : 16 - 21 (6 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 22 - 22 (1 bit)
access : read-only
D_SHIFT_FLAG6 : data shift flag 6
bits : 23 - 23 (1 bit)
access : read-write
D_SHIFT_WIDTH7 : data shift width 3
bits : 24 - 29 (6 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 30 - 30 (1 bit)
access : read-only
D_SHIFT_FLAG7 : data shift flag 7
bits : 31 - 31 (1 bit)
access : read-write
no description available
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F_SHIFT_WIDTH0 : flag shift width 0
bits : 0 - 5 (6 bit)
access : read-write
F_SHIFT_FLAG0 : flag shift flag0
bits : 6 - 6 (1 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 7 - 7 (1 bit)
access : read-only
F_SHIFT_WIDTH1 : flag shift width 1
bits : 8 - 13 (6 bit)
access : read-write
F_SHIFT_FLAG1 : flag shift flag1
bits : 14 - 14 (1 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 15 - 15 (1 bit)
access : read-only
F_SHIFT_WIDTH2 : flag shift width 2
bits : 16 - 21 (6 bit)
access : read-write
F_SHIFT_FLAG2 : flag shift flag2
bits : 22 - 22 (1 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 23 - 23 (1 bit)
access : read-only
F_SHIFT_WIDTH3 : flag shift width 3
bits : 24 - 29 (6 bit)
access : read-write
F_SHIFT_FLAG3 : flag shift flag3
bits : 30 - 30 (1 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 31 - 31 (1 bit)
access : read-only
no description available
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F_SHIFT_WIDTH4 : flag shift width 4
bits : 0 - 5 (6 bit)
access : read-write
F_SHIFT_FLAG4 : flag shift flag4
bits : 6 - 6 (1 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 7 - 7 (1 bit)
access : read-only
F_SHIFT_WIDTH5 : flag shift width 5
bits : 8 - 13 (6 bit)
access : read-write
F_SHIFT_FLAG5 : flag shift flag5
bits : 14 - 14 (1 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 15 - 15 (1 bit)
access : read-only
F_SHIFT_WIDTH6 : flag shift width 5
bits : 16 - 21 (6 bit)
access : read-write
F_SHIFT_FLAG6 : flag shift flag6
bits : 22 - 22 (1 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 23 - 23 (1 bit)
access : read-only
F_SHIFT_WIDTH7 : flag shift width 7
bits : 24 - 29 (6 bit)
access : read-write
F_SHIFT_FLAG7 : flag shift flag7
bits : 30 - 30 (1 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 31 - 31 (1 bit)
access : read-only
no description available
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F_MASK0 : flag mask0
bits : 0 - 7 (8 bit)
access : read-write
F_MASK1 : flag mask1
bits : 8 - 15 (8 bit)
access : read-write
F_MASK2 : flag mask2
bits : 16 - 23 (8 bit)
access : read-write
F_MASK3 : flag mask3
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F_MASK4 : flag mask4
bits : 0 - 7 (8 bit)
access : read-write
F_MASK5 : flag mask5
bits : 8 - 15 (8 bit)
access : read-write
F_MASK6 : flag mask6
bits : 16 - 23 (8 bit)
access : read-write
F_MASK7 : flag mask7
bits : 24 - 31 (8 bit)
access : read-write
Pre-fetch engine Control Channel 0 Register
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_EN : Channel enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
Prefetch function is disable
0x1 : 1
Prefetch function is enable
End of enumeration elements list.
BLOCK_EN : Choses the prefetch mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : 0
Prefetch in scan mode
0x1 : 1
Prefetch in block mode
End of enumeration elements list.
BLOCK_16 : Determines the block sixe.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : 8x8
Block size is 8x8
0x1 : 16x16
Block size is 16x16
End of enumeration elements list.
HANDSHAKE_EN : Enable bit for handshake with the store engine.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : 0
Handshake with the store engine is disabled
0x1 : 1
Handshake with the store engine is enabled
End of enumeration elements list.
BYPASS_PIXEL_EN : Selects Channel 0 pixel source
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : 0
Channel 0 is from memory
0x1 : 1
Channel 0 is from previous process engine
End of enumeration elements list.
HIGH_BYTE : channel 0 high byte selection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : 0
In 64 bit mode, the output high byte will use channel1.
0x1 : 1
In 64 bit mode, the output high byte will use channel0
End of enumeration elements list.
RSVD4 : Reserved, always set to zero.
bits : 6 - 8 (3 bit)
access : read-only
HFLIP : Enables HFLIP.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : 0
HFLIP disable
0x1 : 1
VFLIP enable
End of enumeration elements list.
VFLIP : Enables VFLIP
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : 0
VFLIP disable
0x1 : 1
VFLIP enable
End of enumeration elements list.
RSVD3 : Reserved, always set to zero.
bits : 11 - 11 (1 bit)
access : read-only
ROTATION_ANGLE : no description available
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ROT_0
Rotate image by 0 degrees.
0x1 : ROT_90
Rotate image by 90 degrees.
0x2 : ROT_180
Rotate image by 180 degrees.
0x3 : ROT_270
Rotate image by 270 degrees.
End of enumeration elements list.
RSVD2 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
RD_NUM_BYTES : Bytes in a read burst
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : 8_bytes
8 bytes.
0x1 : 16_bytes
16 bytes.
0x2 : 32_bytes
32 bytes.
0x3 : 64_bytes
64 bytes.
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 18 - 23 (6 bit)
access : read-only
HANDSHAKE_SCAN_LINE_NUM : scan handshake line number
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : 0
1 line.
0x1 : 1
8 lines
0x2 : 2
16 lines
0x3 : 3
16 lines
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 26 - 30 (5 bit)
access : read-only
ARBIT_EN : Enables Arbitration
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : 0
Arbitration disable. If using 2 channels, will output 2 axi bus sets.
0x1 : 1
Arbitration enable. If using 2 channel, will only output 1 axi bus sets
End of enumeration elements list.
Pre-fetch engine Control Channel 1 Register
address_offset : 0x860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_EN : Channel enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
Prefetch function is disable
0x1 : 1
Prefetch function is enable
End of enumeration elements list.
BLOCK_EN : Choses the prefetch mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : 0
Prefetch in scan mode
0x1 : 1
Prefetch in block mode
End of enumeration elements list.
BLOCK_16 : Determines the block sixe.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : 8x8
Block size is 8x8
0x1 : 16x16
Block size is 16x16
End of enumeration elements list.
HANDSHAKE_EN : Enable bit for handshake with the store engine.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : 0
Handshake with the store engine is disabled
0x1 : 1
Handshake with the store engine is enabled
End of enumeration elements list.
BYPASS_PIXEL_EN : Selects Channel 1 pixel source
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : 0
Channel 1 is from memory
0x1 : 1
Channel 1 is from previous process engine
End of enumeration elements list.
RSVD4 : Reserved, always set to zero.
bits : 5 - 8 (4 bit)
access : read-only
HFLIP : Enables HFLIP.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : 0
HFLIP disable
0x1 : 1
VFLIP enable
End of enumeration elements list.
VFLIP : Enables VFLIP
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : 0
VFLIP disable
0x1 : 1
VFLIP enable
End of enumeration elements list.
RSVD3 : Reserved, always set to zero.
bits : 11 - 11 (1 bit)
access : read-only
ROTATION_ANGLE : no description available
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ROT_0
Rotate image by 0 degrees.
0x1 : ROT_90
Rotate image by 90 degrees.
0x2 : ROT_180
Rotate image by 180 degrees.
0x3 : ROT_270
Rotate image by 270 degrees.
End of enumeration elements list.
RSVD2 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
RD_NUM_BYTES : Bytes in a read burst
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : 8_bytes
8 bytes.
0x1 : 16_bytes
16 bytes.
0x2 : 32_bytes
32 bytes.
0x3 : 64_bytes
64 bytes.
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 18 - 23 (6 bit)
access : read-only
HANDSHAKE_SCAN_LINE_NUM : scan handshake line number
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : 0
1 line.
0x1 : 1
8 lines
0x2 : 2
16 lines
0x3 : 3
16 lines
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 26 - 31 (6 bit)
access : read-only
Pre-fetch engine status Channel 0 Register
address_offset : 0x870 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREFETCH_BLOCK_X : When in scan mode, this field is always 0
bits : 0 - 15 (16 bit)
access : read-only
PREFETCH_BLOCK_Y : When in scan mode, this field indicates the current Y coordinate of the frame
bits : 16 - 31 (16 bit)
access : read-only
Store engine status Channel 1 Register
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREFETCH_BLOCK_X : When in scan mode, this field is always 0
bits : 0 - 15 (16 bit)
access : read-only
PREFETCH_BLOCK_Y : When in scan mode, this field indicates the current Y coordinate of the frame
bits : 16 - 31 (16 bit)
access : read-only
no description available
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE_SIZE_ULC_X : This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory
bits : 0 - 15 (16 bit)
access : read-write
ACTIVE_SIZE_ULC_Y : This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x8A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE_SIZE_LRC_X : This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory
bits : 0 - 15 (16 bit)
access : read-write
ACTIVE_SIZE_LRC_Y : This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x8B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE_SIZE_ULC_X : This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory
bits : 0 - 15 (16 bit)
access : read-write
ACTIVE_SIZE_ULC_Y : This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE_SIZE_LRC_X : This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory
bits : 0 - 15 (16 bit)
access : read-write
ACTIVE_SIZE_LRC_Y : This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_TOTAL_WIDTH : actual total widht -1
bits : 0 - 15 (16 bit)
access : read-write
INPUT_TOTAL_HEIGHT : actual total height -1
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_TOTAL_WIDTH : actual_total_width -1
bits : 0 - 15 (16 bit)
access : read-write
INPUT_TOTAL_HEIGHT : acutal total height -1
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKGROUND_COLOR : background color(in 32bpp format) for any pixels not within the bufffer range specified by the ULC/LRC
bits : 0 - 31 (32 bit)
access : read-write
Alpha Surface Upper Left Coordinate
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Y : This field indicates the upper left Y-coordinate (in pixels) of the alpha surface in the output frame buffer
bits : 0 - 13 (14 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
X : This field indicates the upper left X-coordinate (in pixels) of the alpha surface (AS) in the output frame buffer
bits : 16 - 29 (14 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
no description available
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKGROUND_COLOR : background color(in 32bpp format) for any pixels not within the bufffer range specified by the ULC/LRC
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_INPUT_PITCH : This field indicates the channel 0 input pitch
bits : 0 - 15 (16 bit)
access : read-write
CH1_INPUT_PITCH : This field indicates the channel 1 input pitch
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0x920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_ACTIVE_BPP : no description available
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : 0
8 bits
0x1 : 1
16 bits
0x2 : 2
32 bits
0x3 : 3
32 bits
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 2 - 7 (6 bit)
access : read-only
EXPAND_FORMAT : Select Pixel format
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : 0
RGB 565
0x1 : 1
RGB 555
0x2 : 2
ARGB 1555
0x3 : 3
RGB 444
0x4 : 4
ARGB 4444
0x5 : 5
YUYV/YVYU
0x6 : 6
UYVY/VYUY
0x7 : 7
YUV422_2P
End of enumeration elements list.
EXPAND_EN : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : 0
channel0 format expanding disable
0x1 : 1
channel0 format expanding enable
End of enumeration elements list.
SHIFT_BYPASS : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : 0
channel0 data will do shift function
0x1 : 1
channel0 will bypass shift function
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 13 - 31 (19 bit)
access : read-only
no description available
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_ACTIVE_BPP : no description available
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : 0
8 bits
0x1 : 1
16 bits
0x2 : 2
32 bits
0x3 : 3
32 bits
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 2 - 7 (6 bit)
access : read-only
EXPAND_FORMAT : Select Pixel format
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : 0
RGB 565
0x1 : 1
RGB 555
0x2 : 2
ARGB 1555
0x3 : 3
RGB 444
0x4 : 4
ARGB 4444
0x5 : 5
YUYV/YVYU
0x6 : 6
UYVY/VYUY
0x7 : 7
YUV422_2P
End of enumeration elements list.
EXPAND_EN : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : 0
channel1 format expanding disable
0x1 : 1
channel1 format expanding enable
End of enumeration elements list.
SHIFT_BYPASS : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : 0
channel1 data will do shift function
0x1 : 1
channel1 will bypass shift function
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 13 - 31 (19 bit)
access : read-only
no description available
address_offset : 0x940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET0 : Shift Offset for channel 0 componnent 0.
bits : 0 - 4 (5 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 5 - 7 (3 bit)
access : read-only
OFFSET1 : Shift Offset for channel 0 componnent 1.
bits : 8 - 12 (5 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 13 - 15 (3 bit)
access : read-only
OFFSET2 : Shift Offset for channel 0 componnent 2.
bits : 16 - 20 (5 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 21 - 23 (3 bit)
access : read-only
OFFSET3 : Shift Offset for channel 0 componnent 3.
bits : 24 - 28 (5 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 29 - 31 (3 bit)
access : read-only
no description available
address_offset : 0x950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET0 : Shift Offset for channel 1 componnent 0.
bits : 0 - 4 (5 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 5 - 7 (3 bit)
access : read-only
OFFSET1 : Shift Offset for channel 1 componnent 1.
bits : 8 - 12 (5 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 13 - 15 (3 bit)
access : read-only
OFFSET2 : Shift Offset for channel 1 componnent 2.
bits : 16 - 20 (5 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 21 - 23 (3 bit)
access : read-only
OFFSET3 : Shift Offset for channel 1 componnent 3.
bits : 24 - 28 (5 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 29 - 31 (3 bit)
access : read-only
no description available
address_offset : 0x960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH0 : Shift Width for channel 0 componnent 0.
bits : 0 - 3 (4 bit)
access : read-write
WIDTH1 : Shift Width for channel 0 componnent 1.
bits : 4 - 7 (4 bit)
access : read-write
WIDTH2 : Shift Width for channel 0 componnent 2.
bits : 8 - 11 (4 bit)
access : read-write
WIDTH3 : Shift Width for channel 0 componnent 3.
bits : 12 - 15 (4 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 16 - 31 (16 bit)
access : read-only
no description available
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH0 : Shift Width for channel 1 componnent 0.
bits : 0 - 3 (4 bit)
access : read-write
WIDTH1 : Shift Width for channel 1 componnent 1.
bits : 4 - 7 (4 bit)
access : read-write
WIDTH2 : Shift Width for channel 1 componnent 2.
bits : 8 - 11 (4 bit)
access : read-write
WIDTH3 : Shift Width for channel 1 componnent 3.
bits : 12 - 15 (4 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 16 - 31 (16 bit)
access : read-only
no description available
address_offset : 0x980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_BASE_ADDR0 : input base address0
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_BASE_ADDR1 : input base address1
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x9A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_BASE_ADDR0 : input base address0
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0x9B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_BASE_ADDR1 : input base address1
bits : 0 - 31 (32 bit)
access : read-write
Store engine Control Channel 0 Register
address_offset : 0x9C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_EN : Channel enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
Store function is disable
0x1 : 1
Store function is enable
End of enumeration elements list.
BLOCK_EN : Choses the store mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : 0
Store in scan mode
0x1 : 1
Store in block mode
End of enumeration elements list.
BLOCK_16 : Determines the block sixe.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : 8x8
Block size is 8x8
0x1 : 16x16
Block size is 16x16
End of enumeration elements list.
HANDSHAKE_EN : Enable bit for handshake with the store engine.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : 0
Handshake with the prefetch engine is disabled
0x1 : 1
Handshake with the prefetch engine is enabled
End of enumeration elements list.
ARRAY_EN : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : 0
Array Handshake Disabled
0x1 : 1
Array Handshake Enabled
End of enumeration elements list.
ARRAY_LINE_NUM : Selects Array Size
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : 0
Using 1x1 Array
0x1 : 1
Using 3x3 Array
0x2 : 2
Using 5x5 Array
0x3 : 3
Using 5x5 Array
End of enumeration elements list.
RSVD3 : Reserved, always set to zero.
bits : 7 - 7 (1 bit)
access : read-only
STORE_BYPASS_EN : enable bit for store bypass
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : 0
store bypass mode disable.
0x1 : 1
store bypass mode enable. Data will bypass to store output.
End of enumeration elements list.
STORE_MEMORY_EN : store memory enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : 0
store memory mode disable.
0x1 : 1
store memory mode enable. Data will store to memory
End of enumeration elements list.
PACK_IN_SEL : pack_in_sel
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : 0
select 64 shift out data to pack
0x1 : 1
select low 32 bit shift out data to pack
End of enumeration elements list.
FILL_DATA_EN : enable bit for fill data
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : 0
Fill data mode disable.
0x1 : 1
Fill data mode enable. When using fill_data mode, store_engine will store fixed data defined in fill_data register
End of enumeration elements list.
RSVD2 : Reserved, always set to zero.
bits : 12 - 15 (4 bit)
access : read-only
WR_NUM_BYTES : Bytes in a write burst
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : 8_bytes
8 bytes
0x1 : 16_bytes
16 bytes
0x2 : 32_bytes
32 bytes
0x3 : 64_bytes
64 bytes
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 18 - 23 (6 bit)
access : read-only
COMBINE_2CHANNEL : Combine 2 channel Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : 0
combine 2 channel disable
0x1 : 1
combine 2 channel enable
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 25 - 30 (6 bit)
access : read-only
ARBIT_EN : Arbitration Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : 0
Arbitration disable. If using 2 channels, will output 2 axi bus sets
0x1 : 1
Arbitration enable. If using 2 channel, will only output 1 axi bus sets
End of enumeration elements list.
Store engine Control Channel 1 Register
address_offset : 0x9D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_EN : Channel enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : 0
Store function is disable
0x1 : 1
Store function is enable
End of enumeration elements list.
BLOCK_EN : Choses the store mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : 0
Store in scan mode
0x1 : 1
Store in block mode
End of enumeration elements list.
BLOCK_16 : Determines the block sixe.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : 8x8
Block size is 8x8
0x1 : 16x16
Block size is 16x16
End of enumeration elements list.
HANDSHAKE_EN : Enable bit for handshake with the fetch engine.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : 0
Handshake with the fetch engine is disabled
0x1 : 1
Handshake with the fetch engine is enabled
End of enumeration elements list.
ARRAY_EN : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : 0
Array Handshake Disabled
0x1 : 1
Array Handshake Enabled
End of enumeration elements list.
ARRAY_LINE_NUM : Selects Array Size
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : 0
Using 1x1 Array
0x1 : 1
Using 3x3 Array
0x2 : 2
Using 5x5 Array
0x3 : 3
Using 5x5 Array
End of enumeration elements list.
RSVD3 : Reserved, always set to zero.
bits : 7 - 7 (1 bit)
access : read-only
STORE_BYPASS_EN : enable bit for store bypass
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : 0
store bypass mode disable.
0x1 : 1
store bypass mode enable. Data will bypass to store output.
End of enumeration elements list.
STORE_MEMORY_EN : store memory enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : 0
store memory mode disable.
0x1 : 1
store memory mode enable. Data will store to memory
End of enumeration elements list.
PACK_IN_SEL : pack_in_sel
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : 0
select 64 shift out data to pack
0x1 : 1
select channel 0 high 32 bit shift out data to pack
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 11 - 15 (5 bit)
access : read-only
WR_NUM_BYTES : Bytes in a write burst
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : 8_bytes
8 bytes
0x1 : 16_bytes
16 bytes
0x2 : 32_bytes
32 bytes
0x3 : 64_bytes
64 bytes
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 18 - 31 (14 bit)
access : read-only
Store engine status Channel 0 Register
address_offset : 0x9E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STORE_BLOCK_X : When in scan mode, this field is always 0
bits : 0 - 15 (16 bit)
access : read-only
STORE_BLOCK_Y : When in scan mode, this field indicates the current Y coordinate of the frame
bits : 16 - 31 (16 bit)
access : read-only
Store engine status Channel 1 Register
address_offset : 0x9F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STORE_BLOCK_X : When in scan mode, this field is always 0
bits : 0 - 15 (16 bit)
access : read-only
STORE_BLOCK_Y : When in scan mode, this field indicates the current Y coordinate of the frame
bits : 16 - 31 (16 bit)
access : read-only
Alpha Surface Lower Right Coordinate
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Y : This field indicates the lower right Y-coordinate (in pixels) of the alpha surface in the output frame buffer
bits : 0 - 13 (14 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 14 - 15 (2 bit)
access : read-only
X : This field indicates the lower right X-coordinate (in pixels) of the alpha surface (AS) in the output frame buffer
bits : 16 - 29 (14 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 30 - 31 (2 bit)
access : read-only
no description available
address_offset : 0xA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_WIDTH : actual output width -1
bits : 0 - 15 (16 bit)
access : read-write
OUT_HEIGHT : actual output height -1
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0xA10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_WIDTH : actual output width -1
bits : 0 - 15 (16 bit)
access : read-write
OUT_HEIGHT : actual output height -1
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0xA20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_OUT_PITCH : This field indicates the channel 0 input pitch
bits : 0 - 15 (16 bit)
access : read-write
CH1_OUT_PITCH : This field indicates the channel 1 input pitch
bits : 16 - 31 (16 bit)
access : read-write
no description available
address_offset : 0xA30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD2 : Reserved, always set to zero.
bits : 0 - 1 (2 bit)
access : read-only
OUTPUT_ACTIVE_BPP : no description available
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : 0
8 bits
0x1 : 1
16 bits
0x2 : 2
32 bits
0x3 : 3
32 bits
End of enumeration elements list.
OUT_YUV422_1P_EN : Enable for YUV422 1 plane
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : 0
YUYV422 2 plane disabled.
0x1 : 1
YUYV422 2 plane enabled.
End of enumeration elements list.
OUT_YUV422_2P_EN : Enable for YUV422 2 plane
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : 0
YUYV422 2 plane disabled.
0x1 : 1
YUYV422 2 plane enabled.
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 6 - 6 (1 bit)
access : read-only
SHIFT_BYPASS : CH0 shift bypass
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : 0
data will do shift processing.
0x1 : 1
data will bypass shift module.
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 8 - 31 (24 bit)
access : read-only
no description available
address_offset : 0xA40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD2 : Reserved, always set to zero.
bits : 0 - 1 (2 bit)
access : read-only
OUTPUT_ACTIVE_BPP : no description available
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : 0
8 bits
0x1 : 1
16 bits
0x2 : 2
32 bits
0x3 : 3
32 bits
End of enumeration elements list.
OUT_YUV422_1P_EN : Enable for YUV422 1 plane
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : 0
YUYV422 2 plane disabled.
0x1 : 1
YUYV422 2 plane enabled.
End of enumeration elements list.
OUT_YUV422_2P_EN : Enable for YUV422 2 plane
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : 0
YUYV422 2 plane disabled.
0x1 : 1
YUYV422 2 plane enabled.
End of enumeration elements list.
RSVD0 : Reserved, always set to zero.
bits : 6 - 31 (26 bit)
access : read-only
no description available
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_BASE_ADDR0 : input base address0
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xAA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_BASE_ADDR1 : input base address1
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xAB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILL_DATA_CH0 : when using fill_data mode,store engine channel0 will store the fill_data value defined here.
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xAC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_BASE_ADDR0 : input base address0
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xAD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_BASE_ADDR1 : input base address1
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xAE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK0_H_CH0 : data mask0 high byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xAF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK0_L_CH0 : data mask0 low byte
bits : 0 - 31 (32 bit)
access : read-write
Processed Surface (PS) Control Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORMAT : PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x4 : RGB888
32-bit pixels (unpacked 24-bit format)
0xC : RGB555
16-bit pixels
0xD : RGB444
16-bit pixels
0xE : RGB565
16-bit pixels
0x10 : YUV1P444
32-bit pixels (1-plane XYUV unpacked)
0x12 : UYVY1P422
16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
0x13 : VYUY1P422
16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
0x14 : Y8
8-bit monochrome pixels (1-plane Y luma output)
0x15 : Y4
4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
0x18 : YUV2P422
16-bit pixels (2-plane UV interleaved bytes)
0x19 : YUV2P420
16-bit pixels (2-plane UV)
0x1A : YVU2P422
16-bit pixels (2-plane VU interleaved bytes)
0x1B : YVU2P420
16-bit pixels (2-plane VU)
0x1E : YUV422
16-bit pixels (3-plane format)
0x1F : YUV420
16-bit pixels (3-plane format)
End of enumeration elements list.
WB_SWAP : Swap bytes in words. For each 16 bit word, the two bytes will be swapped.
bits : 6 - 6 (1 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 7 - 7 (1 bit)
access : read-only
DECY : Verticle pre decimation filter control.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable pre-decimation filter.
0x1 : DECY2
Decimate PS by 2.
0x2 : DECY4
Decimate PS by 4.
0x3 : DECY8
Decimate PS by 8.
End of enumeration elements list.
DECX : Horizontal pre decimation filter control.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable pre-decimation filter.
0x1 : DECX2
Decimate PS by 2.
0x2 : DECX4
Decimate PS by 4.
0x3 : DECX8
Decimate PS by 8.
End of enumeration elements list.
RSVD1 : Reserved, always set to zero.
bits : 12 - 31 (20 bit)
access : read-only
no description available
address_offset : 0xB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK1_H_CH0 : data mask1 high byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK1_L_CH0 : data mask1 low byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK2_H_CH0 : data mask2 high byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK2_L_CH0 : data mask2 low byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK3_H_CH0 : data mask3 high byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xB50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK3_L_CH0 : data mask3 low byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xB60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK4_H_CH0 : data mask4 high byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xB70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK4_L_CH0 : data mask4 low byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK5_H_CH0 : data mask5 high byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xB90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK5_L_CH0 : data mask5 low byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xBA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK6_H_CH0 : data mask6 high byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xBB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK6_L_CH0 : data mask6 low byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xBC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK7_H_CH0 : data mask7 high byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xBD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_MASK7_L_CH0 : data mask7 low byte
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xBE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_SHIFT_WIDTH0 : data shift width 0
bits : 0 - 5 (6 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 6 - 6 (1 bit)
access : read-only
D_SHIFT_FLAG0 : data shift flag 0
bits : 7 - 7 (1 bit)
access : read-write
D_SHIFT_WIDTH1 : data shift width 1
bits : 8 - 13 (6 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 14 - 14 (1 bit)
access : read-only
D_SHIFT_FLAG1 : data shift flag 1
bits : 15 - 15 (1 bit)
access : read-write
D_SHIFT_WIDTH2 : data shift width 2
bits : 16 - 21 (6 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 22 - 22 (1 bit)
access : read-only
D_SHIFT_FLAG2 : data shift flag 2
bits : 23 - 23 (1 bit)
access : read-write
D_SHIFT_WIDTH3 : data shift width 3
bits : 24 - 29 (6 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 30 - 30 (1 bit)
access : read-only
D_SHIFT_FLAG3 : data shift flag 3
bits : 31 - 31 (1 bit)
access : read-write
no description available
address_offset : 0xBF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_SHIFT_WIDTH4 : data shift width 4
bits : 0 - 5 (6 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 6 - 6 (1 bit)
access : read-only
D_SHIFT_FLAG4 : data shift flag 4
bits : 7 - 7 (1 bit)
access : read-write
D_SHIFT_WIDTH5 : data shift width 5
bits : 8 - 13 (6 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 14 - 14 (1 bit)
access : read-only
D_SHIFT_FLAG5 : data shift flag 5
bits : 15 - 15 (1 bit)
access : read-write
D_SHIFT_WIDTH6 : data shift width 6
bits : 16 - 21 (6 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 22 - 22 (1 bit)
access : read-only
D_SHIFT_FLAG6 : data shift flag 6
bits : 23 - 23 (1 bit)
access : read-write
D_SHIFT_WIDTH7 : data shift width 3
bits : 24 - 29 (6 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 30 - 30 (1 bit)
access : read-only
D_SHIFT_FLAG7 : data shift flag 7
bits : 31 - 31 (1 bit)
access : read-write
PS Input Buffer Address
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer for the PS RGB or Y (luma) input buffer.
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F_SHIFT_WIDTH0 : flag shift width 0
bits : 0 - 5 (6 bit)
access : read-write
F_SHIFT_FLAG0 : flag shift flag0
bits : 6 - 6 (1 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 7 - 7 (1 bit)
access : read-only
F_SHIFT_WIDTH1 : flag shift width 1
bits : 8 - 13 (6 bit)
access : read-write
F_SHIFT_FLAG1 : flag shift flag1
bits : 14 - 14 (1 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 15 - 15 (1 bit)
access : read-only
F_SHIFT_WIDTH2 : flag shift width 2
bits : 16 - 21 (6 bit)
access : read-write
F_SHIFT_FLAG2 : flag shift flag2
bits : 22 - 22 (1 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 23 - 23 (1 bit)
access : read-only
F_SHIFT_WIDTH3 : flag shift width 3
bits : 24 - 29 (6 bit)
access : read-write
F_SHIFT_FLAG3 : flag shift flag3
bits : 30 - 30 (1 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 31 - 31 (1 bit)
access : read-only
no description available
address_offset : 0xC10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F_SHIFT_WIDTH4 : flag shift width 4
bits : 0 - 5 (6 bit)
access : read-write
F_SHIFT_FLAG4 : flag shift flag4
bits : 6 - 6 (1 bit)
access : read-write
RSVD3 : Reserved, always set to zero.
bits : 7 - 7 (1 bit)
access : read-only
F_SHIFT_WIDTH5 : flag shift width 5
bits : 8 - 13 (6 bit)
access : read-write
F_SHIFT_FLAG5 : flag shift flag5
bits : 14 - 14 (1 bit)
access : read-write
RSVD2 : Reserved, always set to zero.
bits : 15 - 15 (1 bit)
access : read-only
F_SHIFT_WIDTH6 : flag shift width 5
bits : 16 - 21 (6 bit)
access : read-write
F_SHIFT_FLAG6 : flag shift flag6
bits : 22 - 22 (1 bit)
access : read-write
RSVD1 : Reserved, always set to zero.
bits : 23 - 23 (1 bit)
access : read-only
F_SHIFT_WIDTH7 : flag shift width 7
bits : 24 - 29 (6 bit)
access : read-write
F_SHIFT_FLAG7 : flag shift flag7
bits : 30 - 30 (1 bit)
access : read-write
RSVD0 : Reserved, always set to zero.
bits : 31 - 31 (1 bit)
access : read-only
no description available
address_offset : 0xC20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F_MASK0 : flag mask0
bits : 0 - 7 (8 bit)
access : read-write
F_MASK1 : flag mask1
bits : 8 - 15 (8 bit)
access : read-write
F_MASK2 : flag mask2
bits : 16 - 23 (8 bit)
access : read-write
F_MASK3 : flag mask3
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0xC30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F_MASK4 : flag mask4
bits : 0 - 7 (8 bit)
access : read-write
F_MASK5 : flag mask5
bits : 8 - 15 (8 bit)
access : read-write
F_MASK6 : flag mask6
bits : 16 - 23 (8 bit)
access : read-write
F_MASK7 : flag mask7
bits : 24 - 31 (8 bit)
access : read-write
PS U/Cb or 2 Plane UV Input Buffer Address
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer for the PS U/Cb or 2 plane UV Chroma input buffer.
bits : 0 - 31 (32 bit)
access : read-write
PS V/Cr Input Buffer Address
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address pointer for the PS V/Cr Chroma input buffer.
bits : 0 - 31 (32 bit)
access : read-write
Processed Surface Pitch
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PITCH : Indicates the number of bytes in memory between two vertically adjacent pixels.
bits : 0 - 15 (16 bit)
access : read-write
RSVD : Reserved, always set to zero.
bits : 16 - 31 (16 bit)
access : read-only
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