Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection : not protected
CSI Control Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIXEL_BIT : Pixel Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PIXEL_BIT_0
8-bit data for each pixel
0x1 : PIXEL_BIT_1
10-bit data for each pixel
End of enumeration elements list.
REDGE : Valid Pixel Clock Edge Select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : REDGE_0
Pixel data is latched at the falling edge of CSI_PIXCLK
0x1 : REDGE_1
Pixel data is latched at the rising edge of CSI_PIXCLK
End of enumeration elements list.
INV_PCLK : Invert Pixel Clock Input
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INV_PCLK_0
CSI_PIXCLK is directly applied to internal circuitry
0x1 : INV_PCLK_1
CSI_PIXCLK is inverted before applied to internal circuitry
End of enumeration elements list.
INV_DATA : Invert Data Input. This bit enables or disables internal inverters on the data lines.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : INV_DATA_0
CSI_D[7:0] data lines are directly applied to internal circuitry
0x1 : INV_DATA_1
CSI_D[7:0] data lines are inverted before applied to internal circuitry
End of enumeration elements list.
GCLK_MODE : Gated Clock Mode Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : GCLK_MODE_0
Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored.
0x1 : GCLK_MODE_1
Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
End of enumeration elements list.
CLR_RXFIFO : Asynchronous RXFIFO Clear
bits : 5 - 5 (1 bit)
access : read-write
CLR_STATFIFO : Asynchronous STATFIFO Clear
bits : 6 - 6 (1 bit)
access : read-write
PACK_DIR : Data Packing Direction
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PACK_DIR_0
Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO.
0x1 : PACK_DIR_1
Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
End of enumeration elements list.
FCC : FIFO Clear Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : FCC_0
Asynchronous FIFO clear is selected.
0x1 : FCC_1
Synchronous FIFO clear is selected.
End of enumeration elements list.
CCIR_EN : CCIR656 Interface Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : CCIR_EN_0
Traditional interface is selected. Timing interface logic is used to latch data.
0x1 : CCIR_EN_1
CCIR656 interface is selected.
End of enumeration elements list.
HSYNC_POL : HSYNC Polarity Select
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : HSYNC_POL_0
HSYNC is active low
0x1 : HSYNC_POL_1
HSYNC is active high
End of enumeration elements list.
SOF_INTEN : Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SOF_INTEN_0
SOF interrupt disable
0x1 : SOF_INTEN_1
SOF interrupt enable
End of enumeration elements list.
SOF_POL : SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SOF_POL_0
SOF interrupt is generated on SOF falling edge
0x1 : SOF_POL_1
SOF interrupt is generated on SOF rising edge
End of enumeration elements list.
RXFF_INTEN : RxFIFO Full Interrupt Enable. This bit enables the RxFIFO full interrupt.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : RXFF_INTEN_0
RxFIFO full interrupt disable
0x1 : RXFF_INTEN_1
RxFIFO full interrupt enable
End of enumeration elements list.
FB1_DMA_DONE_INTEN : Frame Buffer1 DMA Transfer Done Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : FB1_DMA_DONE_INTEN_0
Frame Buffer1 DMA Transfer Done interrupt disable
0x1 : FB1_DMA_DONE_INTEN_1
Frame Buffer1 DMA Transfer Done interrupt enable
End of enumeration elements list.
FB2_DMA_DONE_INTEN : Frame Buffer2 DMA Transfer Done Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : FB2_DMA_DONE_INTEN_0
Frame Buffer2 DMA Transfer Done interrupt disable
0x1 : FB2_DMA_DONE_INTEN_1
Frame Buffer2 DMA Transfer Done interrupt enable
End of enumeration elements list.
STATFF_INTEN : STATFIFO Full Interrupt Enable. This bit enables the STAT FIFO interrupt.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : STATFF_INTEN_0
STATFIFO full interrupt disable
0x1 : STATFF_INTEN_1
STATFIFO full interrupt enable
End of enumeration elements list.
SFF_DMA_DONE_INTEN : STATFIFO DMA Transfer Done Interrupt Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SFF_DMA_DONE_INTEN_0
STATFIFO DMA Transfer Done interrupt disable
0x1 : SFF_DMA_DONE_INTEN_1
STATFIFO DMA Transfer Done interrupt enable
End of enumeration elements list.
RF_OR_INTEN : RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : RF_OR_INTEN_0
RxFIFO overrun interrupt is disabled
0x1 : RF_OR_INTEN_1
RxFIFO overrun interrupt is enabled
End of enumeration elements list.
SF_OR_INTEN : STAT FIFO Overrun Interrupt Enable. This bit enables the STATFIFO overrun interrupt.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SF_OR_INTEN_0
STATFIFO overrun interrupt is disabled
0x1 : SF_OR_INTEN_1
STATFIFO overrun interrupt is enabled
End of enumeration elements list.
COF_INT_EN : Change Of Image Field (COF) Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : COF_INT_EN_0
COF interrupt is disabled
0x1 : COF_INT_EN_1
COF interrupt is enabled
End of enumeration elements list.
VIDEO_MODE : Video mode select. This bit controls the video mode in CCIR mode and TV decoder input.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : VIDEO_MODE_0
Progressive mode is selected
0x1 : VIDEO_MODE_1
Interlace mode is selected
End of enumeration elements list.
PrP_IF_EN : CSI-PrP Interface Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : PrP_IF_EN_0
CSI to PrP bus is disabled
0x1 : PrP_IF_EN_1
CSI to PrP bus is enabled
End of enumeration elements list.
EOF_INT_EN : End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : EOF_INT_EN_0
EOF interrupt is disabled.
0x1 : EOF_INT_EN_1
EOF interrupt is generated when RX count value is reached.
End of enumeration elements list.
EXT_VSYNC : External VSYNC Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : EXT_VSYNC_0
Internal VSYNC mode
0x1 : EXT_VSYNC_1
External VSYNC mode
End of enumeration elements list.
SWAP16_EN : SWAP 16-Bit Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SWAP16_EN_0
Disable swapping
0x1 : SWAP16_EN_1
Enable swapping
End of enumeration elements list.
CSI RX FIFO Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMAGE : Received image data
bits : 0 - 31 (32 bit)
access : read-only
CSI RX Count Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXCNT : RxFIFO Count
bits : 0 - 21 (22 bit)
access : read-write
CSI Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRDY : RXFIFO Data Ready
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DRDY_0
No data (word) is ready
0x1 : DRDY_1
At least 1 datum (word) is ready in RXFIFO.
End of enumeration elements list.
ECC_INT : CCIR Error Interrupt
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ECC_INT_0
No error detected
0x1 : ECC_INT_1
Error is detected in CCIR coding
End of enumeration elements list.
HRESP_ERR_INT : Hresponse Error Interrupt Status
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : HRESP_ERR_INT_0
No hresponse error.
0x1 : HRESP_ERR_INT_1
Hresponse error is detected.
End of enumeration elements list.
COF_INT : Change Of Field Interrupt Status
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : COF_INT_0
Video field has no change.
0x1 : COF_INT_1
Change of video field is detected.
End of enumeration elements list.
F1_INT : CCIR Field 1 Interrupt Status
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : F1_INT_0
Field 1 of video is not detected.
0x1 : F1_INT_1
Field 1 of video is about to start.
End of enumeration elements list.
F2_INT : CCIR Field 2 Interrupt Status
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : F2_INT_0
Field 2 of video is not detected
0x1 : F2_INT_1
Field 2 of video is about to start
End of enumeration elements list.
SOF_INT : Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1)
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SOF_INT_0
SOF is not detected.
0x1 : SOF_INT_1
SOF is detected.
End of enumeration elements list.
EOF_INT : End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1)
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : EOF_INT_0
EOF is not detected.
0x1 : EOF_INT_1
EOF is detected.
End of enumeration elements list.
RxFF_INT : RXFIFO Full Interrupt Status
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : RxFF_INT_0
RxFIFO is not full.
0x1 : RxFF_INT_1
RxFIFO is full.
End of enumeration elements list.
DMA_TSF_DONE_FB1 : DMA Transfer Done in Frame Buffer1
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DMA_TSF_DONE_FB1_0
DMA transfer is not completed.
0x1 : DMA_TSF_DONE_FB1_1
DMA transfer is completed.
End of enumeration elements list.
DMA_TSF_DONE_FB2 : DMA Transfer Done in Frame Buffer2
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DMA_TSF_DONE_FB2_0
DMA transfer is not completed.
0x1 : DMA_TSF_DONE_FB2_1
DMA transfer is completed.
End of enumeration elements list.
STATFF_INT : STATFIFO Full Interrupt Status
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : STATFF_INT_0
STATFIFO is not full.
0x1 : STATFF_INT_1
STATFIFO is full.
End of enumeration elements list.
DMA_TSF_DONE_SFF : DMA Transfer Done from StatFIFO
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DMA_TSF_DONE_SFF_0
DMA transfer is not completed.
0x1 : DMA_TSF_DONE_SFF_1
DMA transfer is completed.
End of enumeration elements list.
RF_OR_INT : RxFIFO Overrun Interrupt Status
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : RF_OR_INT_0
RXFIFO has not overflowed.
0x1 : RF_OR_INT_1
RXFIFO has overflowed.
End of enumeration elements list.
SF_OR_INT : STATFIFO Overrun Interrupt Status
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SF_OR_INT_0
STATFIFO has not overflowed.
0x1 : SF_OR_INT_1
STATFIFO has overflowed.
End of enumeration elements list.
DMA_FIELD1_DONE : When DMA field 0 is complete, this bit will be set to 1(clear by writing 1).
bits : 26 - 26 (1 bit)
access : read-write
DMA_FIELD0_DONE : When DMA field 0 is complete, this bit will be set to 1(clear by writing 1).
bits : 27 - 27 (1 bit)
access : read-write
BASEADDR_CHHANGE_ERROR : When using base address switching enable, this bit will be 1 when switching occur before DMA complete
bits : 28 - 28 (1 bit)
access : read-write
CSI DMA Start Address Register - for STATFIFO
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_START_ADDR_SFF : DMA Start Address for STATFIFO
bits : 2 - 31 (30 bit)
access : read-write
CSI DMA Transfer Size Register - for STATFIFO
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_TSF_SIZE_SFF : DMA Transfer Size for STATFIFO
bits : 0 - 31 (32 bit)
access : read-write
CSI DMA Start Address Register - for Frame Buffer1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_START_ADDR_FB1 : DMA Start Address in Frame Buffer1
bits : 2 - 31 (30 bit)
access : read-write
CSI DMA Transfer Size Register - for Frame Buffer2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_START_ADDR_FB2 : DMA Start Address in Frame Buffer2
bits : 2 - 31 (30 bit)
access : read-write
CSI Frame Buffer Parameter Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBUF_STRIDE : Frame Buffer Parameter
bits : 0 - 15 (16 bit)
access : read-write
DEINTERLACE_STRIDE : DEINTERLACE_STRIDE is only used in the deinterlace mode
bits : 16 - 31 (16 bit)
access : read-write
CSI Image Parameter Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMAGE_HEIGHT : Image Height. Indicates how many pixels in a column of the image from the sensor.
bits : 0 - 15 (16 bit)
access : read-write
IMAGE_WIDTH : Image Width
bits : 16 - 31 (16 bit)
access : read-write
CSI Control Register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSC : Horizontal Skip Count
bits : 0 - 7 (8 bit)
access : read-write
VSC : Vertical Skip Count. Contains the number of rows to skip. SCE must be 1, otherwise VSC is ignored.
bits : 8 - 15 (8 bit)
access : read-write
LVRM : Live View Resolution Mode. Selects the grid size used for live view resolution.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : LVRM_0
512 x 384
0x1 : LVRM_1
448 x 336
0x2 : LVRM_2
384 x 288
0x3 : LVRM_3
384 x 256
0x4 : LVRM_4
320 x 240
0x5 : LVRM_5
288 x 216
0x6 : LVRM_6
400 x 300
End of enumeration elements list.
BTS : Bayer Tile Start. Controls the Bayer pattern starting point.
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
0 : BTS_0
GR
0x1 : BTS_1
RG
0x2 : BTS_2
BG
0x3 : BTS_3
GB
End of enumeration elements list.
SCE : Skip Count Enable. Enables or disables the skip count feature.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SCE_0
Skip count disable
0x1 : SCE_1
Skip count enable
End of enumeration elements list.
AFS : Auto Focus Spread. Selects which green pixels are used for auto-focus.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : AFS_0
Abs Diff on consecutive green pixels
0x1 : AFS_1
Abs Diff on every third green pixels
End of enumeration elements list.
DRM : Double Resolution Mode. Controls size of statistics grid.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DRM_0
Stats grid of 8 x 6
0x1 : DRM_1
Stats grid of 8 x 12
End of enumeration elements list.
DMA_BURST_TYPE_SFF : Burst Type of DMA Transfer from STATFIFO. Selects the burst type of DMA transfer from STATFIFO.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x1 : DMA_BURST_TYPE_SFF_1
INCR4
0x3 : DMA_BURST_TYPE_SFF_3
INCR16
End of enumeration elements list.
DMA_BURST_TYPE_RFF : Burst Type of DMA Transfer from RxFIFO. Selects the burst type of DMA transfer from RxFIFO.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0x1 : DMA_BURST_TYPE_RFF_1
INCR4
0x3 : DMA_BURST_TYPE_RFF_3
INCR16
End of enumeration elements list.
CSI Control Register 18
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEINTERLACE_EN : This bit is used to select the output method When input is standard CCIR656 video.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DEINTERLACE_EN_0
Deinterlace disabled
0x1 : DEINTERLACE_EN_1
Deinterlace enabled
End of enumeration elements list.
PARALLEL24_EN : When input is parallel rgb888/yuv444 24bit, this bit can be enabled.
bits : 3 - 3 (1 bit)
access : read-write
BASEADDR_SWITCH_EN : When this bit is enabled, CSI DMA will switch the base address according to BASEADDR_SWITCH_SEL rather than atomically by DMA completed
bits : 4 - 4 (1 bit)
access : read-write
BASEADDR_SWITCH_SEL : CSI 2 base addresses switching method. When using this bit, BASEADDR_SWITCH_EN is 1.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : BASEADDR_SWITCH_SEL_0
Switching base address at the edge of the vsync
0x1 : BASEADDR_SWITCH_SEL_1
Switching base address at the edge of the first data of each frame
End of enumeration elements list.
FIELD0_DONE_IE : In interlace mode, fileld 0 means interrupt enabled.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : FIELD0_DONE_IE_0
Interrupt disabled
0x1 : FIELD0_DONE_IE_1
Interrupt enabled
End of enumeration elements list.
DMA_FIELD1_DONE_IE : When in interlace mode, field 1 done interrupt enable.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DMA_FIELD1_DONE_IE_0
Interrupt disabled
0x1 : DMA_FIELD1_DONE_IE_1
Interrupt enabled
End of enumeration elements list.
LAST_DMA_REQ_SEL : Choosing the last DMA request condition.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : LAST_DMA_REQ_SEL_0
fifo_full_level
0x1 : LAST_DMA_REQ_SEL_1
hburst_length
End of enumeration elements list.
BASEADDR_CHANGE_ERROR_IE : Base address change error interrupt enable signal.
bits : 9 - 9 (1 bit)
access : read-write
RGB888A_FORMAT_SEL : Output is 32-bit format.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : RGB888A_FORMAT_SEL_0
{8'h0, data[23:0]}
0x1 : RGB888A_FORMAT_SEL_1
{data[23:0], 8'h0}
End of enumeration elements list.
AHB_HPROT : Hprot value in AHB bus protocol.
bits : 12 - 15 (4 bit)
access : read-write
CSI_LCDIF_BUFFER_LINES : The number of lines are used in handshake mode with LCDIF.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : CSI_LCDIF_BUFFER_LINES_0
4 lines
0x1 : CSI_LCDIF_BUFFER_LINES_1
8 lines
0x2 : CSI_LCDIF_BUFFER_LINES_2
16 lines
0x3 : CSI_LCDIF_BUFFER_LINES_3
16 lines
End of enumeration elements list.
MASK_OPTION : These bits used to choose the method to mask the CSI input.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : MASK_OPTION_0
Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1.
0x1 : MASK_OPTION_1
Writing to memory when CSI_ENABLE is 1.
0x2 : MASK_OPTION_2
Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1.
0x3 : MASK_OPTION_3
Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0.
End of enumeration elements list.
MIPI_DOUBLE_CMPNT : Double component per clock cycle in YUV422 formats.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : MIPI_DOUBLE_CMPNT_0
Single component per clock cycle (half pixel per clock cycle)
0x1 : MIPI_DOUBLE_CMPNT_1
Double component per clock cycle (a pixel per clock cycle)
End of enumeration elements list.
MIPI_YU_SWAP : It only works in MIPI CSI YUV422 double component mode.
bits : 21 - 21 (1 bit)
access : read-write
DATA_FROM_MIPI : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DATA_FROM_MIPI_0
Data from parallel sensor
0x1 : DATA_FROM_MIPI_1
Data from MIPI
End of enumeration elements list.
LINE_STRIDE_EN : When the line width are not the multiple of the burst length, assert this bit.
bits : 24 - 24 (1 bit)
access : read-write
MIPI_DATA_FORMAT : Image Data Format
bits : 25 - 30 (6 bit)
access : read-only
CSI_ENABLE : CSI global enable signal
bits : 31 - 31 (1 bit)
access : read-write
CSI Control Register 3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC_AUTO_EN : Automatic Error Correction Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ECC_AUTO_EN_0
Auto Error correction is disabled.
0x1 : ECC_AUTO_EN_1
Auto Error correction is enabled.
End of enumeration elements list.
ECC_INT_EN : Error Detection Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ECC_INT_EN_0
No interrupt is generated when error is detected. Only the status bit ECC_INT is set.
0x1 : ECC_INT_EN_1
Interrupt is generated when error is detected.
End of enumeration elements list.
ZERO_PACK_EN : Dummy Zero Packing Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ZERO_PACK_EN_0
Zero packing disabled
0x1 : ZERO_PACK_EN_1
Zero packing enabled
End of enumeration elements list.
TWO_8BIT_SENSOR : Two 8-bit Sensor Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TWO_8BIT_SENSOR_0
Only one sensor is connected.
0x1 : TWO_8BIT_SENSOR_1
Two 8-bit sensors are connected or one 16-bit sensor is connected.
End of enumeration elements list.
RxFF_LEVEL : RxFIFO Full Level
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : RxFF_LEVEL_0
4 Double words
0x1 : RxFF_LEVEL_1
8 Double words
0x2 : RxFF_LEVEL_2
16 Double words
0x3 : RxFF_LEVEL_3
24 Double words
0x4 : RxFF_LEVEL_4
32 Double words
0x5 : RxFF_LEVEL_5
48 Double words
0x6 : RxFF_LEVEL_6
64 Double words
0x7 : RxFF_LEVEL_7
96 Double words
End of enumeration elements list.
HRESP_ERR_EN : Hresponse Error Enable. This bit enables the hresponse error interrupt.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : HRESP_ERR_EN_0
Disable hresponse error interrupt
0x1 : HRESP_ERR_EN_1
Enable hresponse error interrupt
End of enumeration elements list.
STATFF_LEVEL : STATFIFO Full Level
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : STATFF_LEVEL_0
4 Double words
0x1 : STATFF_LEVEL_1
8 Double words
0x2 : STATFF_LEVEL_2
12 Double words
0x3 : STATFF_LEVEL_3
16 Double words
0x4 : STATFF_LEVEL_4
24 Double words
0x5 : STATFF_LEVEL_5
32 Double words
0x6 : STATFF_LEVEL_6
48 Double words
0x7 : STATFF_LEVEL_7
64 Double words
End of enumeration elements list.
DMA_REQ_EN_SFF : DMA Request Enable for STATFIFO
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DMA_REQ_EN_SFF_0
Disable the dma request
0x1 : DMA_REQ_EN_SFF_1
Enable the dma request
End of enumeration elements list.
DMA_REQ_EN_RFF : DMA Request Enable for RxFIFO
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DMA_REQ_EN_RFF_0
Disable the dma request
0x1 : DMA_REQ_EN_RFF_1
Enable the dma request
End of enumeration elements list.
DMA_REFLASH_SFF : Reflash DMA Controller for STATFIFO
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DMA_REFLASH_SFF_0
No reflashing
0x1 : DMA_REFLASH_SFF_1
Reflash the embedded DMA controller
End of enumeration elements list.
DMA_REFLASH_RFF : Reflash DMA Controller for RxFIFO
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DMA_REFLASH_RFF_0
No reflashing
0x1 : DMA_REFLASH_RFF_1
Reflash the embedded DMA controller
End of enumeration elements list.
FRMCNT_RST : Frame Count Reset. Resets the Frame Counter. (Cleared automatically after reset is done)
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : FRMCNT_RST_0
Do not reset
0x1 : FRMCNT_RST_1
Reset frame counter immediately
End of enumeration elements list.
FRMCNT : Frame Counter
bits : 16 - 31 (16 bit)
access : read-write
CSI Statistic FIFO Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STAT : Static data from sensor
bits : 0 - 31 (32 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.