Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xBC byte (0x0)
mem_usage : registers
protection : not protected
UART Receiver Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX_DATA : Received Data
bits : 0 - 7 (8 bit)
access : read-only
PRERR : In RS-485 mode, it holds the ninth data bit (bit [8]) of received 9-bit RS-485 data In RS232/IrDA mode, it is the Parity Error flag
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : PRERR_0
= No parity error was detected for data in the RX_DATA field
0x1 : PRERR_1
= A parity error was detected for data in the RX_DATA field
End of enumeration elements list.
BRK : BREAK Detect
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : BRK_0
The current character is not a BREAK character
0x1 : BRK_1
The current character is a BREAK character
End of enumeration elements list.
FRMERR : Frame Error
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : FRMERR_0
The current character has no framing error
0x1 : FRMERR_1
The current character has a framing error
End of enumeration elements list.
OVRRUN : Receiver Overrun
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : OVRRUN_0
No RxFIFO overrun was detected
0x1 : OVRRUN_1
A RxFIFO overrun was detected
End of enumeration elements list.
ERR : Error Detect
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : ERR_0
No error status was detected
0x1 : ERR_1
An error status was detected
End of enumeration elements list.
CHARRDY : Character Ready
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : CHARRDY_0
Character in RX_DATA field and associated flags are invalid.
0x1 : CHARRDY_1
Character in RX_DATA field and associated flags valid and ready for reading.
End of enumeration elements list.
UART Transmitter Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_DATA : Transmit Data
bits : 0 - 7 (8 bit)
access : write-only
UART Control Register 1
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UARTEN : UART Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : UARTEN_0
Disable the UART
0x1 : UARTEN_1
Enable the UART
End of enumeration elements list.
DOZE : DOZE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DOZE_0
The UART is enabled when in DOZE state
0x1 : DOZE_1
The UART is disabled when in DOZE state
End of enumeration elements list.
ATDMAEN : Aging DMA Timer Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ATDMAEN_0
Disable AGTIM DMA request
0x1 : ATDMAEN_1
Enable AGTIM DMA request
End of enumeration elements list.
TXDMAEN : Transmitter Ready DMA Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TXDMAEN_0
Disable transmit DMA request
0x1 : TXDMAEN_1
Enable transmit DMA request
End of enumeration elements list.
SNDBRK : Send BREAK
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SNDBRK_0
Do not send a BREAK character
0x1 : SNDBRK_1
Send a BREAK character (continuous 0s)
End of enumeration elements list.
RTSDEN : RTS Delta Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : RTSDEN_0
Disable RTSD interrupt
0x1 : RTSDEN_1
Enable RTSD interrupt
End of enumeration elements list.
TXMPTYEN : Transmitter Empty Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : TXMPTYEN_0
Disable the transmitter FIFO empty interrupt
0x1 : TXMPTYEN_1
Enable the transmitter FIFO empty interrupt
End of enumeration elements list.
IREN : Infrared Interface Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : IREN_0
Disable the IR interface
0x1 : IREN_1
Enable the IR interface
End of enumeration elements list.
RXDMAEN : Receive Ready DMA Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : RXDMAEN_0
Disable DMA request
0x1 : RXDMAEN_1
Enable DMA request
End of enumeration elements list.
RRDYEN : Receiver Ready Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : RRDYEN_0
Disables the RRDY interrupt
0x1 : RRDYEN_1
Enables the RRDY interrupt
End of enumeration elements list.
ICD : Idle Condition Detect
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : ICD_0
Idle for more than 4 frames
0x1 : ICD_1
Idle for more than 8 frames
0x2 : ICD_2
Idle for more than 16 frames
0x3 : ICD_3
Idle for more than 32 frames
End of enumeration elements list.
IDEN : Idle Condition Detected Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : IDEN_0
Disable the IDLE interrupt
0x1 : IDEN_1
Enable the IDLE interrupt
End of enumeration elements list.
TRDYEN : Transmitter Ready Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : TRDYEN_0
Disable the transmitter ready interrupt
0x1 : TRDYEN_1
Enable the transmitter ready interrupt
End of enumeration elements list.
ADBR : Automatic Detection of Baud Rate
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : ADBR_0
Disable automatic detection of baud rate
0x1 : ADBR_1
Enable automatic detection of baud rate
End of enumeration elements list.
ADEN : Automatic Baud Rate Detection Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ADEN_0
Disable the automatic baud rate detection interrupt
0x1 : ADEN_1
Enable the automatic baud rate detection interrupt
End of enumeration elements list.
UART Control Register 2
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRST : Software Reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SRST_0
Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3].
0x1 : SRST_1
No reset
End of enumeration elements list.
RXEN : Receiver Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RXEN_0
Disable the receiver
0x1 : RXEN_1
Enable the receiver
End of enumeration elements list.
TXEN : Transmitter Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : TXEN_0
Disable the transmitter
0x1 : TXEN_1
Enable the transmitter
End of enumeration elements list.
ATEN : Aging Timer Enable. This bit is used to enable the aging timer interrupt (triggered with AGTIM)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : ATEN_0
AGTIM interrupt disabled
0x1 : ATEN_1
AGTIM interrupt enabled
End of enumeration elements list.
RTSEN : Request to Send Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : RTSEN_0
Disable request to send interrupt
0x1 : RTSEN_1
Enable request to send interrupt
End of enumeration elements list.
WS : Word Size
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : WS_0
7-bit transmit and receive character length (not including START, STOP or PARITY bits)
0x1 : WS_1
8-bit transmit and receive character length (not including START, STOP or PARITY bits)
End of enumeration elements list.
STPB : Stop
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : STPB_0
The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits.
0x1 : STPB_1
The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits.
End of enumeration elements list.
PROE : Parity Odd/Even
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PROE_0
Even parity
0x1 : PROE_1
Odd parity
End of enumeration elements list.
PREN : Parity Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : PREN_0
Disable parity generator and checker
0x1 : PREN_1
Enable parity generator and checker
End of enumeration elements list.
RTEC : Request to Send Edge Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
0 : RTEC_0
Trigger interrupt on a rising edge
0x1 : RTEC_1
Trigger interrupt on a falling edge
End of enumeration elements list.
ESCEN : Escape Enable. Enables/Disables the escape sequence detection logic.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ESCEN_0
Disable escape sequence detection
0x1 : ESCEN_1
Enable escape sequence detection
End of enumeration elements list.
CTS : Clear to Send
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : CTS_0
The CTS_B pin is high (inactive)
0x1 : CTS_1
The CTS_B pin is low (active)
End of enumeration elements list.
CTSC : CTS Pin Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : CTSC_0
The CTS_B pin is controlled by the CTS bit
0x1 : CTSC_1
The CTS_B pin is controlled by the receiver
End of enumeration elements list.
IRTS : Ignore RTS Pin
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : IRTS_0
Transmit only when the RTS pin is asserted
0x1 : IRTS_1
Ignore the RTS pin
End of enumeration elements list.
ESCI : Escape Sequence Interrupt Enable. Enables/Disables the ESCF bit to generate an interrupt.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ESCI_0
Disable the escape sequence interrupt
0x1 : ESCI_1
Enable the escape sequence interrupt
End of enumeration elements list.
UART Control Register 3
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACIEN : Autobaud Counter Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ACIEN_0
ACST interrupt disabled
0x1 : ACIEN_1
ACST interrupt enabled
End of enumeration elements list.
INVT : Invert TXD output in RS-232/RS-485 mode, set TXD active level in IrDA mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INVT_0
TXD is not inverted
0x1 : INVT_1
TXD is inverted
End of enumeration elements list.
RXDMUXSEL : RXD Muxed Input Selected
bits : 2 - 2 (1 bit)
access : read-write
DTRDEN : This bit is not used in this chip.
bits : 3 - 3 (1 bit)
access : read-write
AWAKEN : Asynchronous WAKE Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : AWAKEN_0
Disable the AWAKE interrupt
0x1 : AWAKEN_1
Enable the AWAKE interrupt
End of enumeration elements list.
AIRINTEN : Asynchronous IR WAKE Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : AIRINTEN_0
Disable the AIRINT interrupt
0x1 : AIRINTEN_1
Enable the AIRINT interrupt
End of enumeration elements list.
RXDSEN : Receive Status Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : RXDSEN_0
Disable the RXDS interrupt
0x1 : RXDSEN_1
Enable the RXDS interrupt
End of enumeration elements list.
ADNIMP : Autobaud Detection Not Improved-
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ADNIMP_0
Autobaud detection new features selected
0x1 : ADNIMP_1
Keep old autobaud detection mechanism
End of enumeration elements list.
RI : This bit is not used in this chip.
bits : 8 - 8 (1 bit)
access : read-write
DCD : This bit is not used in this chip.
bits : 9 - 9 (1 bit)
access : read-write
DSR : This bit is not used in this chip.
bits : 10 - 10 (1 bit)
access : read-write
FRAERREN : Frame Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : FRAERREN_0
Disable the frame error interrupt
0x1 : FRAERREN_1
Enable the frame error interrupt
End of enumeration elements list.
PARERREN : Parity Error Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : PARERREN_0
Disable the parity error interrupt
0x1 : PARERREN_1
Enable the parity error interrupt
End of enumeration elements list.
DTREN : This bit is not used in this chip.
bits : 13 - 13 (1 bit)
access : read-write
DPEC : This bit is not used in this chip.
bits : 14 - 15 (2 bit)
access : read-write
UART Control Register 4
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DREN : Receive Data Ready Interrupt Enable. Enables/Disables the RDR bit to generate an interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DREN_0
Disable RDR interrupt
0x1 : DREN_1
Enable RDR interrupt
End of enumeration elements list.
OREN : Receiver Overrun Interrupt Enable. Enables/Disables the ORE bit to generate an interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : OREN_0
Disable ORE interrupt
0x1 : OREN_1
Enable ORE interrupt
End of enumeration elements list.
BKEN : BREAK Condition Detected Interrupt Enable. Enables/Disables the BRCD bit to generate an interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : BKEN_0
Disable the BRCD interrupt
0x1 : BKEN_1
Enable the BRCD interrupt
End of enumeration elements list.
TCEN : Transmit Complete Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TCEN_0
Disable TXDC interrupt
0x1 : TCEN_1
Enable TXDC interrupt
End of enumeration elements list.
LPBYP : Low Power Bypass. Allows to bypass the low power new features in UART. To use during debug phase.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : LPBYP_0
Low power features enabled
0x1 : LPBYP_1
Low power features disabled
End of enumeration elements list.
IRSC : IR Special Case
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : IRSC_0
The vote logic uses the sampling clock (16x baud rate) for normal operation
0x1 : IRSC_1
The vote logic uses the UART reference clock
End of enumeration elements list.
IDDMAEN : DMA IDLE Condition Detected Interrupt Enable Enables/Disables the receive DMA request dma_req_rx for the IDLE interrupt (triggered with IDLE flag in USR2[12])
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : IDDMAEN_0
DMA IDLE interrupt disabled
0x1 : IDDMAEN_1
DMA IDLE interrupt enabled
End of enumeration elements list.
WKEN : WAKE Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : WKEN_0
Disable the WAKE interrupt
0x1 : WKEN_1
Enable the WAKE interrupt
End of enumeration elements list.
ENIRI : Serial Infrared Interrupt Enable. Enables/Disables the serial infrared interrupt.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : ENIRI_0
Serial infrared Interrupt disabled
0x1 : ENIRI_1
Serial infrared Interrupt enabled
End of enumeration elements list.
INVR : Invert RXD input in RS-232/RS-485 Mode, determine RXD input logic level being sampled in In IrDA mode
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : INVR_0
RXD input is not inverted
0x1 : INVR_1
RXD input is inverted
End of enumeration elements list.
CTSTL : CTS Trigger Level
bits : 10 - 15 (6 bit)
access : read-write
Enumeration:
0 : CTSTL_0
0 characters received
0x1 : CTSTL_1
1 characters in the RxFIFO
0x20 : CTSTL_32
32 characters in the RxFIFO (maximum)
End of enumeration elements list.
UART FIFO Control Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXTL : Receiver Trigger Level
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : RXTL_0
0 characters received
0x1 : RXTL_1
RxFIFO has 1 character
0x1F : RXTL_31
RxFIFO has 31 characters
0x20 : RXTL_32
RxFIFO has 32 characters (maximum)
End of enumeration elements list.
DCEDTE : DCE/DTE mode select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DCEDTE_0
DCE mode selected
0x1 : DCEDTE_1
DTE mode selected
End of enumeration elements list.
RFDIV : Reference Frequency Divider
bits : 7 - 9 (3 bit)
access : read-write
Enumeration:
0 : RFDIV_0
Divide input clock by 6
0x1 : RFDIV_1
Divide input clock by 5
0x2 : RFDIV_2
Divide input clock by 4
0x3 : RFDIV_3
Divide input clock by 3
0x4 : RFDIV_4
Divide input clock by 2
0x5 : RFDIV_5
Divide input clock by 1
0x6 : RFDIV_6
Divide input clock by 7
End of enumeration elements list.
TXTL : Transmitter Trigger Level
bits : 10 - 15 (6 bit)
access : read-write
Enumeration:
0x2 : TXTL_2
TxFIFO has 2 or fewer characters
0x1F : TXTL_31
TxFIFO has 31 or fewer characters
0x20 : TXTL_32
TxFIFO has 32 characters (maximum)
End of enumeration elements list.
UART Status Register 1
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAD : RS-485 Slave Address Detected Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SAD_0
No slave address detected
0x1 : SAD_1
Slave address detected
End of enumeration elements list.
AWAKE : Asynchronous WAKE Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : AWAKE_0
No falling edge was detected on the RXD Serial pin
0x1 : AWAKE_1
A falling edge was detected on the RXD Serial pin
End of enumeration elements list.
AIRINT : Asynchronous IR WAKE Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : AIRINT_0
No pulse was detected on the RXD IrDA pin
0x1 : AIRINT_1
A pulse was detected on the RXD IrDA pin
End of enumeration elements list.
RXDS : Receiver IDLE Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : RXDS_0
Receive in progress
0x1 : RXDS_1
Receiver is IDLE
End of enumeration elements list.
DTRD : This bit is not used in this chip.
bits : 7 - 7 (1 bit)
access : read-write
AGTIM : Ageing Timer Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : AGTIM_0
AGTIM is not active
0x1 : AGTIM_1
AGTIM is active (write 1 to clear)
End of enumeration elements list.
RRDY : Receiver Ready Interrupt / DMA Flag
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : RRDY_0
No character ready
0x1 : RRDY_1
Character(s) ready (interrupt posted)
End of enumeration elements list.
FRAMERR : Frame Error Interrupt Flag
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : FRAMERR_0
No frame error detected
0x1 : FRAMERR_1
Frame error detected (write 1 to clear)
End of enumeration elements list.
ESCF : Escape Sequence Interrupt Flag
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ESCF_0
No escape sequence detected
0x1 : ESCF_1
Escape sequence detected (write 1 to clear).
End of enumeration elements list.
RTSD : RTS Delta
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : RTSD_0
RTS_B pin did not change state since last cleared
0x1 : RTSD_1
RTS_B pin changed state (write 1 to clear)
End of enumeration elements list.
TRDY : Transmitter Ready Interrupt / DMA Flag
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : TRDY_0
The transmitter does not require data
0x1 : TRDY_1
The transmitter requires data (interrupt posted)
End of enumeration elements list.
RTSS : RTS_B Pin Status
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : RTSS_0
The RTS_B module input is high (inactive)
0x1 : RTSS_1
The RTS_B module input is low (active)
End of enumeration elements list.
PARITYERR : Parity Error Interrupt Flag
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : PARITYERR_0
No parity error detected
0x1 : PARITYERR_1
Parity error detected (write 1 to clear)
End of enumeration elements list.
UART Status Register 2
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDR : Receive Data Ready-Indicates that at least 1 character is received and written to the RxFIFO
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : RDR_0
No receive data ready
0x1 : RDR_1
Receive data ready
End of enumeration elements list.
ORE : Overrun Error
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ORE_0
No overrun error
0x1 : ORE_1
Overrun error (write 1 to clear)
End of enumeration elements list.
BRCD : BREAK Condition Detected
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : BRCD_0
No BREAK condition was detected
0x1 : BRCD_1
A BREAK condition was detected (write 1 to clear)
End of enumeration elements list.
TXDC : Transmitter Complete
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : TXDC_0
Transmit is incomplete
0x1 : TXDC_1
Transmit is complete
End of enumeration elements list.
RTSF : RTS Edge Triggered Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : RTSF_0
Programmed edge not detected on RTS_B
0x1 : RTSF_1
Programmed edge detected on RTS_B (write 1 to clear)
End of enumeration elements list.
DCDIN : This bit is not used in this chip.
bits : 5 - 5 (1 bit)
access : read-only
DCDDELT : This bit is not used in this chip.
bits : 6 - 6 (1 bit)
access : read-write
WAKE : Wake
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : WAKE_0
start bit not detected
0x1 : WAKE_1
start bit detected (write 1 to clear)
End of enumeration elements list.
IRINT : Serial Infrared Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : IRINT_0
no edge detected
0x1 : IRINT_1
valid edge detected (write 1 to clear)
End of enumeration elements list.
RIIN : This bit is not used in this chip.
bits : 9 - 9 (1 bit)
access : read-only
RIDELT : This bit is not used in this chip.
bits : 10 - 10 (1 bit)
access : read-write
ACST : Autobaud Counter Stopped
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ACST_0
Measurement of bit length not finished (in autobaud)
0x1 : ACST_1
Measurement of bit length finished (in autobaud). (write 1 to clear)
End of enumeration elements list.
IDLE : Idle Condition
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : IDLE_0
No idle condition detected
0x1 : IDLE_1
Idle condition detected (write 1 to clear)
End of enumeration elements list.
DTRF : This bit is not used in this chip.
bits : 13 - 13 (1 bit)
access : read-write
TXFE : Transmit Buffer FIFO Empty
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : TXFE_0
The transmit buffer (TxFIFO) is not empty
0x1 : TXFE_1
The transmit buffer (TxFIFO) is empty
End of enumeration elements list.
ADET : Automatic Baud Rate Detect Complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ADET_0
ASCII "A" or "a" was not received
0x1 : ADET_1
ASCII "A" or "a" was received (write 1 to clear)
End of enumeration elements list.
UART Escape Character Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ESC_CHAR : UART Escape Character
bits : 0 - 7 (8 bit)
access : read-write
UART Escape Timer Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM : UART Escape Timer
bits : 0 - 11 (12 bit)
access : read-write
UART BRM Incremental Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INC : Incremental Numerator
bits : 0 - 15 (16 bit)
access : read-write
UART BRM Modulator Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD : Modulator Denominator
bits : 0 - 15 (16 bit)
access : read-write
UART Baud Rate Count Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BCNT : Baud Rate Count Register
bits : 0 - 15 (16 bit)
access : read-only
UART One Millisecond Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ONEMS : One Millisecond Register
bits : 0 - 23 (24 bit)
access : read-write
UART Test Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFTRST : Software Reset. Indicates the status of the software reset (SRST_B bit of UCR2).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SOFTRST_0
Software reset inactive
0x1 : SOFTRST_1
Software reset active
End of enumeration elements list.
RXFULL : RxFIFO FULL. Indicates the RxFIFO is full.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RXFULL_0
The RxFIFO is not full
0x1 : RXFULL_1
The RxFIFO is full
End of enumeration elements list.
TXFULL : TxFIFO FULL. Indicates the TxFIFO is full.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : TXFULL_0
The TxFIFO is not full
0x1 : TXFULL_1
The TxFIFO is full
End of enumeration elements list.
RXEMPTY : RxFIFO Empty. Indicates the RxFIFO is empty.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : RXEMPTY_0
The RxFIFO is not empty
0x1 : RXEMPTY_1
The RxFIFO is empty
End of enumeration elements list.
TXEMPTY : TxFIFO Empty. Indicates that the TxFIFO is empty.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : TXEMPTY_0
The TxFIFO is not empty
0x1 : TXEMPTY_1
The TxFIFO is empty
End of enumeration elements list.
RXDBG : This bit is not used in this chip
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : RXDBG_0
rx fifo read pointer does not increment
0x1 : RXDBG_1
rx_fifo read pointer increments as normal
End of enumeration elements list.
LOOPIR : Loop TX and RX for IR Test (LOOPIR)
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : LOOPIR_0
No IR loop
0x1 : LOOPIR_1
Connect IR transmitter to IR receiver
End of enumeration elements list.
DBGEN : This bit is not used in this chip
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DBGEN_0
UART will go into debug mode when debug_req is HIGH
0x1 : DBGEN_1
UART will not go into debug mode even if debug_req is HIGH
End of enumeration elements list.
LOOP : Loop TX and RX for Test
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LOOP_0
Normal receiver operation
0x1 : LOOP_1
Internally connect the transmitter output to the receiver input
End of enumeration elements list.
FRCPERR : Force Parity Error
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : FRCPERR_0
Generate normal parity
0x1 : FRCPERR_1
Generate inverted parity (error)
End of enumeration elements list.
UART RS-485 Mode Control Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDEN : 9-bit data or Multidrop Mode (RS-485) Enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MDEN_0
Normal RS-232 or IrDA mode, see for detail.
0x1 : MDEN_1
Enable RS-485 mode, see for detail
End of enumeration elements list.
SLAM : RS-485 Slave Address Detect Mode Selection.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SLAM_0
Select Normal Address Detect mode
0x1 : SLAM_1
Select Automatic Address Detect mode
End of enumeration elements list.
TXB8 : Transmit RS-485 bit 8 (the ninth bit or 9th bit)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : TXB8_0
0 will be transmitted as the RS485 9th data bit
0x1 : TXB8_1
1 will be transmitted as the RS485 9th data bit
End of enumeration elements list.
SADEN : RS-485 Slave Address Detected Interrupt Enable.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SADEN_0
Disable RS-485 Slave Address Detected Interrupt
0x1 : SADEN_1
Enable RS-485 Slave Address Detected Interrupt
End of enumeration elements list.
SLADDR : RS-485 Slave Address Character
bits : 8 - 15 (8 bit)
access : read-write
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