Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
Processor A Transmit Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATR0 : Processor A Transmit Register 0
bits : 0 - 31 (32 bit)
access : read-write
Processor A Receive Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ARR0 : Processor A Receive Register 0
bits : 0 - 31 (32 bit)
access : read-only
Processor A Receive Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ARR1 : Processor A Receive Register 1
bits : 0 - 31 (32 bit)
access : read-only
Processor A Receive Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ARR2 : Processor A Receive Register 2
bits : 0 - 31 (32 bit)
access : read-only
Processor A Receive Register 3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ARR3 : Processor A Receive Register 3
bits : 0 - 31 (32 bit)
access : read-only
Processor A Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Fn : For n = {0, 1, 2} Processor A-Side Flag n
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : Fn_0
BAFn bit in BCR register is written 0 (default).
0x1 : Fn_1
BAFn bit in BCR register is written 1.
End of enumeration elements list.
EP : Processor A-Side Event Pending
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : EP_0
The Processor A-side event is not pending (default).
0x1 : EP_1
The Processor A-side event is pending.
End of enumeration elements list.
BRS : Processor B-side Reset State
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : BRS_0
The Processor B-side of the MU is not in reset.
0x1 : BRS_1
The Processor B-side of the MU is in reset.
End of enumeration elements list.
FUP : Processor A Flags Update Pending
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : FUP_0
No flags updated, initiated by the Processor A, in progress (default)
0x1 : FUP_1
Processor A initiated flags update, processing
End of enumeration elements list.
BRDIP : Processor B Reset De-asserted Interrupt Pending
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : BRDIP_0
The Processor A general purpose interrupt 3, because of a Processor B-side reset de-assertion, is cleared (default).
0x1 : BRDIP_1
The Processor B-side is out of reset.
End of enumeration elements list.
TEn : For n = {0, 1, 2, 3} Processor A Transmit Register n Empty
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0 : TEn_0
ATRn register is not empty.
0x1 : TEn_1
ATRn register is empty (default).
End of enumeration elements list.
RFn : For n = {0, 1, 2, 3} Processor A Receive Register n Full
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : RFn_0
ARRn register is not full (default).
0x1 : RFn_1
ARRn register has received data from BTRn register and is ready to be read by the Processor A.
End of enumeration elements list.
GIPn : For n = {0, 1, 2, 3} Processor A General Interrupt Request n Pending
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : GIPn_0
Processor A general purpose interrupt n is not pending. (default)
0x1 : GIPn_1
Processor A general purpose interrupt n is pending.
End of enumeration elements list.
Processor A Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABFn : For n = {0, 1, 2} Processor A to Processor B Flag n
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ABFn_0
N/A. Self clearing bit (default).
0x1 : ABFn_1
Asserts the Processor A MU reset.
End of enumeration elements list.
BHR : Processor B Hardware Reset
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : BHR_0
De-assert Hardware reset to the Processor B. (default)
0x1 : BHR_1
Assert Hardware reset to the Processor B.
End of enumeration elements list.
MUR : Processor A MU Reset
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MUR_0
N/A. Self clearing bit (default).
0x1 : MUR_1
Asserts the Processor A MU reset.
End of enumeration elements list.
BRDIE : Processor B Reset De-assertion Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : BRDIE_0
Disables the Processor A General Purpose Interrupt 3 request due to the Processor B reset de-assertion to the Processor A. Processor B reset deassertion causes Processor B and MU-Processor B side to come out of reset thus setting BRDIP bit to "1".
0x1 : BRDIE_1
Enables Processor A General Purpose Interrupt 3 request due to the Processor B reset de-assertion to the Processor A.
End of enumeration elements list.
GIRn : For n = {0, 1, 2, 3} Processor A General Purpose Interrupt Request n
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : GIRn_0
Processor A General Interrupt n is not requested to the Processor B (default).
0x1 : GIRn_1
Processor A General Interrupt n is requested to the Processor B.
End of enumeration elements list.
TIEn : For n = {0, 1, 2, 3} Processor A Transmit Interrupt Enable n
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0 : TIEn_0
Disables Processor A Transmit Interrupt n. (default)
0x1 : TIEn_1
Enables Processor A Transmit Interrupt n.
End of enumeration elements list.
RIEn : For n = {0, 1, 2, 3} Processor A Receive Interrupt Enable n
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : RIEn_0
Disables Processor A Receive Interrupt n. (default)
0x1 : RIEn_1
Enables Processor A Receive Interrupt n.
End of enumeration elements list.
GIEn : For n = {0, 1, 2, 3} Processor A General Purpose Interrupt Enable n
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : GIEn_0
Disables Processor A General Interrupt n. (default)
0x1 : GIEn_1
Enables Processor A General Interrupt n.
End of enumeration elements list.
Processor A Transmit Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATR1 : Processor A Transmit Register 1
bits : 0 - 31 (32 bit)
access : read-write
Processor A Transmit Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATR2 : Processor A Transmit Register 2
bits : 0 - 31 (32 bit)
access : read-write
Processor A Transmit Register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATR3 : Processor A Transmit Register 3
bits : 0 - 31 (32 bit)
access : read-write
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