\n

ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x134 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CH_A_CFG1

CH_A_CFG2

CHC_D_CNV_RSLT

CH_SW_CNV_RSLT

DMA_FIFO_DAT

ADC_CFG

CH_B_CFG1

CH_B_CFG2

CH_C_CFG1

CH_C_CFG2

CH_D_CFG1

CH_D_CFG2

CH_SW_CFG

TIMER_UNIT

DMA_FIFO

FIFO_STATUS

INT_SIG_EN

INT_EN

INT_STATUS

CHA_B_CNV_RSLT


CH_A_CFG1

Channel A configuration 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_A_CFG1 CH_A_CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHA_TIMER CHA_SEL CHA_AVG_EN CHA_SINGLE CHA_EN

CHA_TIMER : Channel A Timer
bits : 0 - 23 (24 bit)
access : read-write

CHA_SEL : Channel A Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0 : CHA_SEL_0

Channel 0

0x1 : CHA_SEL_1

Channel 1

0x2 : CHA_SEL_2

Channel 2

0x3 : CHA_SEL_3

Channel 3

0x4 : CHA_SEL_4

Channel 4

0x5 : CHA_SEL_5

Channel 5

0x6 : CHA_SEL_6

Channel 6

0x7 : CHA_SEL_7

Channel 7

0x8 : CHA_SEL_8

Channel 8

0x9 : CHA_SEL_9

Channel 9

0xA : CHA_SEL_10

Channel 10

0xB : CHA_SEL_11

Channel 11

0xC : CHA_SEL_12

Channel 12

0xD : CHA_SEL_13

Channel 13

0xE : CHA_SEL_14

Channel 14

0xF : CHA_SEL_15

Channel 15

End of enumeration elements list.

CHA_AVG_EN : Channel A Average Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : CHA_AVG_EN_0

Disable average function.

0x1 : CHA_AVG_EN_1

Enable average function.

End of enumeration elements list.

CHA_SINGLE : Channel A Signal Conversion
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CHA_SINGLE_0

No single conversion. Continuous conversion can start.

0x1 : CHA_SINGLE_1

Start a single conversion. Continuous conversion must stop.

End of enumeration elements list.

CHA_EN : Channel A Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : CHA_EN_0

Disable logical channel A. Prevent logical channel A from working.

0x1 : CHA_EN_1

Enable logical channel A. Logical channel A will work.

End of enumeration elements list.


CH_A_CFG2

Channel A configuration 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_A_CFG2 CH_A_CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHA_LOW_THRES CHA_AVG_NUMBER CHA_AUTO_DIS CHA_HIGH_THRES CHA_CMP_MODE

CHA_LOW_THRES : Channel A Low Threshold Value
bits : 0 - 11 (12 bit)
access : read-write

CHA_AVG_NUMBER : Channel A Average Number
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : CHA_AVG_NUMBER_0

Average number = 4

0x1 : CHA_AVG_NUMBER_1

Average number = 8

0x2 : CHA_AVG_NUMBER_2

Average number = 16

0x3 : CHA_AVG_NUMBER_3

Average number = 32

End of enumeration elements list.

CHA_AUTO_DIS : Channel A Auto Disable
bits : 15 - 15 (1 bit)
access : read-write

CHA_HIGH_THRES : Channel A High Threshold Value
bits : 16 - 27 (12 bit)
access : read-write

CHA_CMP_MODE : Channel A Compare Mode
bits : 29 - 31 (3 bit)
access : read-write

Enumeration:

0x1 : CHA_CMP_MODE_1

If channel A conversion result is greater than CHA_LOW_THRES, then an interrupt will be generated and the channel A flag will be set if they are enabled.

0x2 : CHA_CMP_MODE_2

If channel A conversion result is less than or equal to CHA_LOW_THRES, then an interrupt will be generated and channel A flag will be set if they are enabled.

0x3 : CHA_CMP_MODE_3

If channel A conversion result is greater than CHA_LOW_THRES and less than CHA_HIGH_THRES, then an interrupt will be generated and channel A flag will be set if they are enabled.

0x5 : CHA_CMP_MODE_5

If channel A conversion result is greater than or equal to CHA_HIGH_THRES, then an interrupt will be generated and channel A flag will be set if they are enabled.

0x6 : CHA_CMP_MODE_6

If channel A conversion result is less than CHA_HIGH_THRES, then an interrupt will be generated and channel A flag will be set if they are enabled.

0x7 : CHA_CMP_MODE_7

If channel A conversion result is less than or equal to CHA_LOW_THRES, and at the same time, greater than or equal to CHA_HIGH_THRES, then an interrupt will be generated and channel A flag will be set if they are enabled.

End of enumeration elements list.


CHC_D_CNV_RSLT

Channel C and D Conversion Result
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHC_D_CNV_RSLT CHC_D_CNV_RSLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHC_CNV_RSLT CHD_CNV_RSLT

CHC_CNV_RSLT : Channel C Conversion Result
bits : 0 - 11 (12 bit)
access : read-write

CHD_CNV_RSLT : Channel D Conversion Result
bits : 16 - 27 (12 bit)
access : read-write


CH_SW_CNV_RSLT

Channel Software Conversion Result
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SW_CNV_RSLT CH_SW_CNV_RSLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH_SW_CNV_RSLT

CH_SW_CNV_RSLT : Channel Software Conversion Result
bits : 0 - 11 (12 bit)
access : read-write


DMA_FIFO_DAT

DMA FIFO Data
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMA_FIFO_DAT DMA_FIFO_DAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_FIFO_0 DAT1_FLAG DMA_FIFO_1 DAT2_FLAG

DMA_FIFO_0 : The even number of data is in this field. This field is read-only
bits : 0 - 11 (12 bit)
access : read-only

DAT1_FLAG : Data 1 Flag
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0 : DAT1_FLAG_0

Default

0x1 : DAT1_FLAG_1

Valid Data. Indicate the data 1 is a valid data.

0x2 : DAT1_FLAG_2

Last Data. Indicate the last the data of a continuous batch.

0x3 : DAT1_FLAG_3

Invalid Data. Indicate the data 1 is a invalid data.

End of enumeration elements list.

DMA_FIFO_1 : The even number of data is in this field. This field is read-only
bits : 16 - 27 (12 bit)
access : read-only

DAT2_FLAG : Data 2 Flag
bits : 30 - 31 (2 bit)
access : read-only

Enumeration:

0 : DAT2_FLAG_0

Default

0x1 : DAT2_FLAG_1

Valid Data. Indicate the data 2 is a valid data.

0x2 : DAT2_FLAG_2

Last Data. Indicate the last the data of a continuous batch.

0x3 : DAT2_FLAG_3

Invalid Data. Indicate the data 2 is a invalid data.

End of enumeration elements list.


ADC_CFG

ADC Configuration
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CFG ADC_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_EN ADC_PD ADC_PD_OK ADC_CLK_DOWN

ADC_EN : ADC Level Shifter Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : ADC_EN_0

Disable level shifter, the ADC analogue core ports using 1.8 V voltage level.

0x1 : ADC_EN_1

Enable level shifter, the ADC analogue core ports using 1.1 V voltage level.

End of enumeration elements list.

ADC_PD : ADC Power Down
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : ADC_PD_0

Do not power down the ADC analogue core.

0x1 : ADC_PD_1

Power down the ADC analogue core.

End of enumeration elements list.

ADC_PD_OK : ADC Power Down OK
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : ADC_PD_OK_0

ADC has not power up completely. Cannot start a conversion.

0x1 : ADC_PD_OK_1

ADC power up completely. Can start a conversion.

End of enumeration elements list.

ADC_CLK_DOWN : ADC Clock Down
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ADC_CLK_DOWN_0

Clock running.

0x1 : ADC_CLK_DOWN_1

Clock down, no clock.

End of enumeration elements list.


CH_B_CFG1

no description available
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_B_CFG1 CH_B_CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHB_TIMER CHB_SEL CHB_AVG_EN CHB_SINGLE CHB_EN

CHB_TIMER : Channel B Timer
bits : 0 - 23 (24 bit)
access : read-write

CHB_SEL : Channel B Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0 : CHB_SEL_0

Channel 0

0x1 : CHB_SEL_1

Channel 1

0x2 : CHB_SEL_2

Channel 2

0x3 : CHB_SEL_3

Channel 3

0x4 : CHB_SEL_4

Channel 4

0x5 : CHB_SEL_5

Channel 5

0x6 : CHB_SEL_6

Channel 6

0x7 : CHB_SEL_7

Channel 7

0x8 : CHB_SEL_8

Channel 8

0x9 : CHB_SEL_9

Channel 9

0xA : CHB_SEL_10

Channel 10

0xB : CHB_SEL_11

Channel 11

0xC : CHB_SEL_12

Channel 12

0xD : CHB_SEL_13

Channel 13

0xE : CHB_SEL_14

Channel 14

0xF : CHB_SEL_15

Channel 15

End of enumeration elements list.

CHB_AVG_EN : Channel B Average Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : CHB_AVG_EN_0

Disable average function.

0x1 : CHB_AVG_EN_1

Enable average function.

End of enumeration elements list.

CHB_SINGLE : Channel B Single Conversion
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CHB_SINGLE_0

No single conversion. Continuous conversion can start.

0x1 : CHB_SINGLE_1

Start a single conversion. Continuous conversion must stop.

End of enumeration elements list.

CHB_EN : Channel B Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : CHB_EN_0

Disable logical channel B. Prevent logical channel B from working.

0x1 : CHB_EN_1

Enable logical channel B. Logical channel B will work.

End of enumeration elements list.


CH_B_CFG2

Channel B Configuration 2
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_B_CFG2 CH_B_CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHB_LOW_THRES CHB_AVG_NUMBER CHB_AUTO_DIS CHB_HIGH_THRES CHB_CMP_MODE

CHB_LOW_THRES : Channel B Low Threshold Value
bits : 0 - 11 (12 bit)
access : read-write

CHB_AVG_NUMBER : Channel B Average Number
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : CHB_AVG_NUMBER_0

Average number = 4

0x1 : CHB_AVG_NUMBER_1

Average number = 8

0x2 : CHB_AVG_NUMBER_2

Average number = 16

0x3 : CHB_AVG_NUMBER_3

Average number = 32

End of enumeration elements list.

CHB_AUTO_DIS : Channel B Auto Disable
bits : 15 - 15 (1 bit)
access : read-write

CHB_HIGH_THRES : Channel B High Threshold Value
bits : 16 - 27 (12 bit)
access : read-write

CHB_CMP_MODE : Channel B Compare Mode
bits : 29 - 31 (3 bit)
access : read-write

Enumeration:

0x1 : CHB_CMP_MODE_1

If channel B conversion result is greater than CHB_LOW_THRES, then an interrupt will be generated and the channel B flag will be set if they are enabled.

0x2 : CHB_CMP_MODE_2

If channel B conversion result is less than or equal to CHB_LOW_THRES, then an interrupt will be generated and channel B flag will be set if they are enabled.

0x3 : CHB_CMP_MODE_3

If channel B conversion result is greater than CHB_LOW_THRES and less than CHB_HIGH_THRES, then an interrupt will be generated and channel B flag will be set if they are enabled.

0x5 : CHB_CMP_MODE_5

If channel B conversion result is greater than or equal to CHB_HIGH_THRES, then an interrupt will be generated and channel B flag will be set if they are enabled.

0x6 : CHB_CMP_MODE_6

If channel B conversion result is less than CHB_HIGH_THRES, then an interrupt will be generated and channel B flag will be set if they are enabled.

0x7 : CHB_CMP_MODE_7

If channel B conversion result is less than or equal to CHB_LOW_THRES, and at the same time, is greater than or equal to CHB_HIGH_THRES, then an interrupt will be generated and channel B flag will be set.

End of enumeration elements list.


CH_C_CFG1

Channel C Configuration 1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_C_CFG1 CH_C_CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHC_TIMER CHC_SEL CHC_AVG_EN CHC_SINGLE CHC_EN

CHC_TIMER : Channel C Timer
bits : 0 - 23 (24 bit)
access : read-write

CHC_SEL : Channel C Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0 : CHC_SEL_0

Channel 0

0x1 : CHC_SEL_1

Channel 1

0x2 : CHC_SEL_2

Channel 2

0x3 : CHC_SEL_3

Channel 3

0x4 : CHC_SEL_4

Channel 4

0x5 : CHC_SEL_5

Channel 5

0x6 : CHC_SEL_6

Channel 6

0x7 : CHC_SEL_7

Channel 7

0x8 : CHC_SEL_8

Channel 8

0x9 : CHC_SEL_9

Channel 9

0xA : CHC_SEL_10

Channel 10

0xB : CHC_SEL_11

Channel 11

0xC : CHC_SEL_12

Channel 12

0xD : CHC_SEL_13

Channel 13

0xE : CHC_SEL_14

Channel 14

0xF : CHC_SEL_15

Channel 15

End of enumeration elements list.

CHC_AVG_EN : Channel C Average Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : CHC_AVG_EN_0

Disable average function.

0x1 : CHC_AVG_EN_1

Enable average function.

End of enumeration elements list.

CHC_SINGLE : Channel C Single Conversion Start a single conversion from logical channel C. Switch between single and continuous conversion, it must disable CHC_EN. When both CHC_EN and CHC_SINGLE are enabled, CHC_SIGNAL set CHC_EN to 0 and reset itself to 0.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CHC_SINGLE_0

No single conversion. Continuous conversion can start.

0x1 : CHC_SINGLE_1

Start a single conversion. Continuous conversion must stop.

End of enumeration elements list.

CHC_EN : Channel C Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : CHC_EN_0

Disable logical channel C. Prevent logical channel C from working.

0x1 : CHC_EN_1

Enable logical channel C. Logical channel C will work.

End of enumeration elements list.


CH_C_CFG2

Channel C Configuration 2
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_C_CFG2 CH_C_CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHC_LOW_THRES CHC_AVG_NUMBER CHC_AUTO_DIS CHC_HIGH_THRES CHC_CMP_MODE

CHC_LOW_THRES : Channel C Low Threshold Value
bits : 0 - 11 (12 bit)
access : read-write

CHC_AVG_NUMBER : Channel C Average Number
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : CHC_AVG_NUMBER_0

Average number = 4

0x1 : CHC_AVG_NUMBER_1

Average number = 8

0x2 : CHC_AVG_NUMBER_2

Average number = 16

0x3 : CHC_AVG_NUMBER_3

Average number = 32

End of enumeration elements list.

CHC_AUTO_DIS : Channel C Auto Disable
bits : 15 - 15 (1 bit)
access : read-write

CHC_HIGH_THRES : Channel C High Threshold Value
bits : 16 - 27 (12 bit)
access : read-write

CHC_CMP_MODE : Channel C Compare Mode
bits : 29 - 31 (3 bit)
access : read-write

Enumeration:

0x1 : CHC_CMP_MODE_1

If channel C conversion result bigger than CHC_LOW_THRES, then an interrupt will be generated and the channel C flag will be set if they are enabled.

0x2 : CHC_CMP_MODE_2

If channel C conversion result smaller or equal to CHC_LOW_THRES, then an interrupt will be generated and channel C flag will be set if they are enabled.

0x3 : CHC_CMP_MODE_3

If channel C conversion result bigger than CHC_LOW_THRES and smaller than CHC_HIGH_THRES, then an interrupt will be generated and channel C flag will be set if they are enabled.

0x5 : CHC_CMP_MODE_5

If channel C conversion result bigger or equal to CHC_HIGH_THRES, then an interrupt will be generated and channel C flag will be set if they are enabled.

0x6 : CHC_CMP_MODE_6

If channel C conversion result smaller than CHC_HIGH_THRES, then an interrupt will be generated and channel C flag will be set if they are enabled.

0x7 : CHC_CMP_MODE_7

If channel C conversion result smaller or equal to CHC_LOW_THRES, and at the same time, bigger or equal to CHC_HIGH_THRES, then an interrupt will be generated and channel C flag will be set if they are enabled.

End of enumeration elements list.


CH_D_CFG1

Channel D Configuration 1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_D_CFG1 CH_D_CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHD_TIMER CHD_SEL CHD_AVG_EN CHD_SINGLE CHD_EN

CHD_TIMER : Channel D Timer
bits : 0 - 23 (24 bit)
access : read-write

CHD_SEL : Channel D Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0 : CHD_SEL_0

Channel 0

0x1 : CHD_SEL_1

Channel 1

0x2 : CHD_SEL_2

Channel 2

0x3 : CHD_SEL_3

Channel 3

0x4 : CHD_SEL_4

Channel 4

0x5 : CHD_SEL_5

Channel 5

0x6 : CHD_SEL_6

Channel 6

0x7 : CHD_SEL_7

Channel 7

0x8 : CHD_SEL_8

Channel 8

0x9 : CHD_SEL_9

Channel 9

0xA : CHD_SEL_10

Channel 10

0xB : CHD_SEL_11

Channel 11

0xC : CHD_SEL_12

Channel 12

0xD : CHD_SEL_13

Channel 13

0xE : CHD_SEL_14

Channel 14

0xF : CHD_SEL_15

Channel 15

End of enumeration elements list.

CHD_AVG_EN : Channel D Average Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : CHD_AVG_EN_0

Disable average function.

0x1 : CHD_AVG_EN_1

Enable average function.

End of enumeration elements list.

CHD_SINGLE : Channel D Single Conversion
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CHD_SINGLE_0

No single conversion. Continuous conversion can start.

0x1 : CHD_SINGLE_1

Start a single conversion. Continuous conversion must stop.

End of enumeration elements list.

CHD_EN : Channel D Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : CHD_EN_0

Disable logical channel D. Prevent logical channel D from working.

0x1 : CHD_EN_1

Enable logical channel D. Logical channel D will work.

End of enumeration elements list.


CH_D_CFG2

Channel D Configuration 2
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_D_CFG2 CH_D_CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHD_LOW_THRES CHD_AVG_NUMBER CHD_AUTO_DIS CHD_HIGH_THRES CHD_CMP_MODE

CHD_LOW_THRES : Channel D Low Threshold Value
bits : 0 - 11 (12 bit)
access : read-write

CHD_AVG_NUMBER : Channel D Average Number
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : CHD_AVG_NUMBER_0

Average number = 4

0x1 : CHD_AVG_NUMBER_1

Average number = 8

0x2 : CHD_AVG_NUMBER_2

Average number = 16

0x3 : CHD_AVG_NUMBER_3

Average number = 32

End of enumeration elements list.

CHD_AUTO_DIS : Channel D Auto Disable
bits : 15 - 15 (1 bit)
access : read-write

CHD_HIGH_THRES : Channel D High Threshold Value
bits : 16 - 27 (12 bit)
access : read-write

CHD_CMP_MODE : Channel D Compare Mode
bits : 29 - 31 (3 bit)
access : read-write

Enumeration:

0x1 : CHD_CMP_MODE_1

If channel D conversion result bigger than CHD_LOW_THRES, then an interrupt will be generated and the channel D flag will be set if they are enabled.

0x2 : CHD_CMP_MODE_2

If channel D conversion result smaller or equal to CHD_LOW_THRES, then an interrupt will be generated and channel D flag will be set if they are enabled.

0x3 : CHD_CMP_MODE_3

If channel D conversion result bigger than CHD_LOW_THRES and smaller than CHD_HIGH_THRES, then an interrupt will be generated and channel D flag will be set if they are enabled.

0x5 : CHD_CMP_MODE_5

If channel D conversion result bigger or equal to CHD_HIGH_THRES, then an interrupt will be generated and channel D flag will be set if they are enabled.

0x6 : CHD_CMP_MODE_6

If channel D conversion result smaller than CHD_HIGH_THRES, then an interrupt will be generated and channel D flag will be set if they are enabled.

0x7 : CHD_CMP_MODE_7

If channel D conversion result smaller or equal to CHD_LOW_THRES, and at the same time, bigger or equal to CHD_HIGH_THRES, then an interrupt will be generated and channel D flag will be set if they are enabled.

End of enumeration elements list.


CH_SW_CFG

Channel Software Configuration
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SW_CFG CH_SW_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH_SW_AVG_NUMBER CH_SW_AVG_EN CH_SW_SEL START_CONV

CH_SW_AVG_NUMBER : Channel Software Average Number
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

0 : CH_SW_AVG_NUMBER_0

Average number = 4

0x1 : CH_SW_AVG_NUMBER_1

Average number = 8

0x2 : CH_SW_AVG_NUMBER_2

Average number = 16

0x3 : CH_SW_AVG_NUMBER_3

Average number = 32

End of enumeration elements list.

CH_SW_AVG_EN : Channel Software Average Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : CH_SW_AVG_EN_0

Disable average function.

0x1 : CH_SW_AVG_EN_1

Enable average function.

End of enumeration elements list.

CH_SW_SEL : Software Trigger Channel Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0 : CH_SW_SEL_0

Channel 0

0x1 : CH_SW_SEL_1

Channel 1

0x2 : CH_SW_SEL_2

Channel 2

0x3 : CH_SW_SEL_3

Channel 3

0x4 : CH_SW_SEL_4

Channel 4

0x5 : CH_SW_SEL_5

Channel 5

0x6 : CH_SW_SEL_6

Channel 6

0x7 : CH_SW_SEL_7

Channel 7

0x8 : CH_SW_SEL_8

Channel 8

0x9 : CH_SW_SEL_9

Channel 9

0xA : CH_SW_SEL_10

Channel 10

0xB : CH_SW_SEL_11

Channel 11

0xC : CH_SW_SEL_12

Channel 12

0xD : CH_SW_SEL_13

Channel 13

0xE : CH_SW_SEL_14

Channel 14

0xF : CH_SW_SEL_15

Channel 15

End of enumeration elements list.

START_CONV : Start Software Trigger Conversion
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : START_CONV_0

Not start a new software trigger conversion.

0x1 : START_CONV_1

Start a new software trigger conversion.

End of enumeration elements list.


TIMER_UNIT

Timer Unit
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER_UNIT TIMER_UNIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CORE_TIMER_UNIT PRE_DIV

CORE_TIMER_UNIT : Core_Timer_Unit
bits : 0 - 4 (5 bit)
access : read-write

PRE_DIV : Pre-divide
bits : 29 - 31 (3 bit)
access : read-write

Enumeration:

0 : PRE_DIV_0

No divide, analogue clock = 1/4 ADC digital input clock

0x1 : PRE_DIV_1

Divide 2, analogue clock = 1/8 ADC digital input clock

0x2 : PRE_DIV_2

Divide 4, analogue clock = 1/16 ADC digital input clock

0x3 : PRE_DIV_3

Divide 8, analogue clock = 1/32 ADC digital input clock

0x4 : PRE_DIV_4

Divide 16, analogue clock = 1/64 ADC digital input clock

0x5 : PRE_DIV_5

Divide 32, analogue clock = 1/128 ADC digital input clock

End of enumeration elements list.


DMA_FIFO

DMA FIFO
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_FIFO DMA_FIFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_WM_LVL DMA_CH_SEL DMA_EN DMA_FIFO_EN DMA_RST

DMA_WM_LVL : DMA Water Mark Level
bits : 0 - 4 (5 bit)
access : read-write

DMA_CH_SEL : DMA Channel Select
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

0 : DMA_CH_SEL_0

Channel A

0x1 : DMA_CH_SEL_1

Channel B

0x2 : DMA_CH_SEL_2

Channel C

0x3 : DMA_CH_SEL_3

Channel D

End of enumeration elements list.

DMA_EN : DMA Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DMA_EN_0

Disable DMA, the data in DMA FIFO can only move by CPU.

0x1 : DMA_EN_1

Enable DMA, the data in DMA FIFO should move by SDMA.

End of enumeration elements list.

DMA_FIFO_EN : DMA FIFO Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DMA_FIFO_EN_0

Disable DMA FIFO.

0x1 : DMA_FIFO_EN_1

Enable DMA FIFO.

End of enumeration elements list.

DMA_RST : DMA Reset
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DMA_RST_0

Not reset

0x1 : DMA_RST_1

Reset

End of enumeration elements list.


FIFO_STATUS

FIFO Status
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO_STATUS FIFO_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO_ENTRIES FIFO_EMPTY FIFO_FULL

FIFO_ENTRIES : FIFO Entries
bits : 0 - 5 (6 bit)
access : read-write

FIFO_EMPTY : FIFO Empty
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : FIFO_EMPTY_0

FIFO is not empty.

0x1 : FIFO_EMPTY_1

FIFO is empty.

End of enumeration elements list.

FIFO_FULL : This read-only bit represents the status of DMA FIFO
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : FIFO_FULL_0

FIFO is not full.

0x1 : FIFO_FULL_1

FIFIO is full.

End of enumeration elements list.


INT_SIG_EN

no description available
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_SIG_EN INT_SIG_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHA_CMP_INT_SIG_EN CHB_CMP_INT_SIG_EN CHC_CMP_INT_SIG_EN CHD_CMP_INT_SIG_EN DMA_REACH_WM_INT_SIG_EN FIFO_UNDERRUN_INT_SIG_EN FIFO_OVRRUN_INT_SIG_EN CHA_COV_INT_SIG_EN CHB_COV_INT_SIG_EN CHC_COV_INT_SIG_EN CHD_COV_INT_SIG_EN SW_CH_COV_INT_SIG_EN CHA_COV_TO_INT_SIG_EN CHB_COV_TO_INT_SIG_EN CHC_COV_TO_INT_SIG_EN CHD_COV_TO_INT_SIG_EN SW_CH_COV_TO_INT_SIG_EN LAST_FIFO_DATA_READ_SIG_EN

CHA_CMP_INT_SIG_EN : Channel A Compare Interrupt Signal Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CHA_CMP_INT_SIG_EN_0

Disable Channel A Compare Interrupt flag.

0x1 : CHA_CMP_INT_SIG_EN_1

Enable Channel A Compare Interrupt flag.

End of enumeration elements list.

CHB_CMP_INT_SIG_EN : Channel B Compare Interrupt Signal Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : CHB_CMP_INT_SIG_EN_0

Disable Channel B Compare Interrupt flag.

0x1 : CHB_CMP_INT_SIG_EN_1

Enable Channel B Compare Interrupt flag.

End of enumeration elements list.

CHC_CMP_INT_SIG_EN : Channel C Compare Interrupt Signal Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : CHC_CMP_INT_SIG_EN_0

Disable Channel C Compare Interrupt flag.

0x1 : CHC_CMP_INT_SIG_EN_1

Enable Channel C Compare Interrupt flag.

End of enumeration elements list.

CHD_CMP_INT_SIG_EN : Channel D Compare Interrupt Signal Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : CHD_CMP_INT_SIG_EN_0

Disable Channel D Compare Interrupt flag

0x1 : CHD_CMP_INT_SIG_EN_1

Enable Channel D Compare Interrupt flag

End of enumeration elements list.

DMA_REACH_WM_INT_SIG_EN : DMA Reach Watermark Level Interrupt Signal (Flag) Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DMA_REACH_WM_INT_SIG_EN_0

Enable DMA watermark level interrupt signal (flag).

0x1 : DMA_REACH_WM_INT_SIG_EN_1

Disable DMA watermark level interrupt signal (flag).

End of enumeration elements list.

FIFO_UNDERRUN_INT_SIG_EN : FIFO Underrrun Interrupt Signal Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : FIFO_UNDERRUN_INT_SIG_EN_0

Enable FIFO underrun Interrupt flag

0x1 : FIFO_UNDERRUN_INT_SIG_EN_1

Disable FIFO underrun Interrupt flag

End of enumeration elements list.

FIFO_OVRRUN_INT_SIG_EN : FIFO overrun Interrupt Signal Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : FIFO_OVRRUN_INT_SIG_EN_0

Enable FIFO Interrupt flag.

0x1 : FIFO_OVRRUN_INT_SIG_EN_1

Disable FIFO Interrupt flag.

End of enumeration elements list.

CHA_COV_INT_SIG_EN : Channel A Conversion Interrupt Signal Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : CHA_COV_INT_SIG_EN_0

Disable channel A conversion Interrupt flag.

0x1 : CHA_COV_INT_SIG_EN_1

Enable channel A conversion Interrupt flag.

End of enumeration elements list.

CHB_COV_INT_SIG_EN : Channel B Conversion Interrupt Signal Enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : CHB_COV_INT_SIG_EN_0

Disable channel B conversion Interrupt flag.

0x1 : CHB_COV_INT_SIG_EN_1

Enable channel B conversion Interrupt flag.

End of enumeration elements list.

CHC_COV_INT_SIG_EN : Channel C Conversion Interrupt Signal Enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : CHC_COV_INT_SIG_EN_0

Disable channel C conversion Interrupt flag.

0x1 : CHC_COV_INT_SIG_EN_1

Enable channel C conversion Interrupt flag.

End of enumeration elements list.

CHD_COV_INT_SIG_EN : Channel D Conversion Interrupt Signal Enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : CHD_COV_INT_SIG_EN_0

Disable channel D conversion Interrupt flag.

0x1 : CHD_COV_INT_SIG_EN_1

Enable channel D conversion Interrupt flag.

End of enumeration elements list.

SW_CH_COV_INT_SIG_EN : Software Channel Conversion Interrupt Signal Enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SW_CH_COV_INT_SIG_EN_0

Disable software channel conversion signal interrupt flag.

0x1 : SW_CH_COV_INT_SIG_EN_1

Enable software channel conversion signal interrupt flag.

End of enumeration elements list.

CHA_COV_TO_INT_SIG_EN : Channel A Conversion Time Out Interrupt Signal Enable
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : CHA_COV_TO_INT_SIG_EN_0

Disable logical channel A conversion time out interrupt signal.

0x1 : CHA_COV_TO_INT_SIG_EN_1

Enable logical channel A conversion time out interrupt signal.

End of enumeration elements list.

CHB_COV_TO_INT_SIG_EN : Channel B Conversion Time Out Interrupt Signal Enable
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : CHB_COV_TO_INT_SIG_EN_0

Disable logical channel B conversion time out interrupt signal.

0x1 : CHB_COV_TO_INT_SIG_EN_1

Enable logical channel B conversion time out interrupt signal.

End of enumeration elements list.

CHC_COV_TO_INT_SIG_EN : Channel C Conversion Time Out Interrupt Signal Enable
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : CHC_COV_TO_INT_SIG_EN_0

Disable logical channel C conversion time out interrupt signal.

0x1 : CHC_COV_TO_INT_SIG_EN_1

Enable logical channel C conversion time out interrupt signal.

End of enumeration elements list.

CHD_COV_TO_INT_SIG_EN : Channel D Conversion Time Out Interrupt Signal Enable
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : CHD_COV_TO_INT_SIG_EN_0

Disable logical channel D conversion time out interrupt signal.

0x1 : CHD_COV_TO_INT_SIG_EN_1

Enable logical channel D conversion time out interrupt signal.

End of enumeration elements list.

SW_CH_COV_TO_INT_SIG_EN : Software Channel Conversion Time Out Interrupt Signal Enable
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SW_CH_COV_TO_INT_SIG_EN_0

Disable software channel conversion time out interrupt signal.

0x1 : SW_CH_COV_TO_INT_SIG_EN_1

Enable software channel conversion time out interrupt signal.

End of enumeration elements list.

LAST_FIFO_DATA_READ_SIG_EN : Last FIFO Data Read Signal Enable
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : LAST_FIFO_DATA_READ_SIG_EN_0

Disable last FIFO read signal enable

0x1 : LAST_FIFO_DATA_READ_SIG_EN_1

Enable last FIFO read signal enable

End of enumeration elements list.


INT_EN

Interrupt Enable
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_EN INT_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHA_CMP_INT_EN CHB_CMP_INT_EN CHC_CMP_INT_EN CHD_CMP_INT_EN DMA_REACH_WM_INT_EN FIFO_UNDERRUN_INT_EN FIFO_OVERRUN_INT_EN CHA_COV_INT_EN CHB_COV_INT_EN CHC_COV_INT_EN CHD_COV_INT_EN SW_CH_COV_INT_EN CHA_COV_TO_INT_EN CHB_COV_TO_INT_EN CHC_COV_TO_INT_EN CHD_COV_TO_INT_EN SW_CH_COV_TO_INT_EN LAST_FIFO_DATA_READ_EN

CHA_CMP_INT_EN : Channel A Compare Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CHA_CMP_INT_EN_0

Disable Channel A Compare Interrupt.

0x1 : CHA_CMP_INT_EN_1

Enable Channel A Compare Interrupt.

End of enumeration elements list.

CHB_CMP_INT_EN : Channel B Compare Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : CHB_CMP_INT_EN_0

Disable Channel B Compare Interrupt.

0x1 : CHB_CMP_INT_EN_1

Enable Channel B Compare Interrupt.

End of enumeration elements list.

CHC_CMP_INT_EN : Channel C Compare Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : CHC_CMP_INT_EN_0

Disable Channel C Compare Interrupt.

0x1 : CHC_CMP_INT_EN_1

Enable Channel C Compare Interrupt .

End of enumeration elements list.

CHD_CMP_INT_EN : Channel D Compare Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : CHD_CMP_INT_EN_0

Disable Channel D Compare Interrupt.

0x1 : CHD_CMP_INT_EN_1

Enable Channel D Compare Interrupt.

End of enumeration elements list.

DMA_REACH_WM_INT_EN : DMA Reach Watermark Level Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DMA_REACH_WM_INT_EN_0

Enable DMA reach watermark level interrupt.

0x1 : DMA_REACH_WM_INT_EN_1

Disable DMA reach watermark level interrupt.

End of enumeration elements list.

FIFO_UNDERRUN_INT_EN : FIFO underrun Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : FIFO_UNDERRUN_INT_EN_0

Enable FIFO underrun Interrupt.

0x1 : FIFO_UNDERRUN_INT_EN_1

Disable FIFO underrun Interrupt.

End of enumeration elements list.

FIFO_OVERRUN_INT_EN : FIFO overrun Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : FIFO_OVERRUN_INT_EN_0

Enable FIFO Interrupt.

0x1 : FIFO_OVERRUN_INT_EN_1

Disable FIFO Interrupt.

End of enumeration elements list.

CHA_COV_INT_EN : Channel A Conversion Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : CHA_COV_INT_EN_0

Disable channel A conversion Interrupt.

0x1 : CHA_COV_INT_EN_1

Enable channel A conversion Interrupt.

End of enumeration elements list.

CHB_COV_INT_EN : Channel B Conversion Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : CHB_COV_INT_EN_0

Disable channel B conversion Interrupt.

0x1 : CHB_COV_INT_EN_1

Enable channel B conversion Interrupt.

End of enumeration elements list.

CHC_COV_INT_EN : Channel C Conversion Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : CHC_COV_INT_EN_0

Disable channel C conversion Interrupt.

0x1 : CHC_COV_INT_EN_1

Enable channel C conversion Interrupt.

End of enumeration elements list.

CHD_COV_INT_EN : Channel D Conversion Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : CHD_COV_INT_EN_0

Disable channel D conversion Interrupt.

0x1 : CHD_COV_INT_EN_1

Enable channel D conversion Interrupt.

End of enumeration elements list.

SW_CH_COV_INT_EN : Software Channel Conversion Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SW_CH_COV_INT_EN_0

Disable software channel conversion interrupt.

0x1 : SW_CH_COV_INT_EN_1

Enable software channel conversion interrupt.

End of enumeration elements list.

CHA_COV_TO_INT_EN : Channel A Conversion Time Out Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : CHA_COV_TO_INT_EN_0

Disable logical channel A conversion time out interrupt.

0x1 : CHA_COV_TO_INT_EN_1

Enable logical channel A conversion time out interrupt.

End of enumeration elements list.

CHB_COV_TO_INT_EN : Channel B Conversion Time Out Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : CHB_COV_TO_INT_EN_0

Disable logical channel B conversion time out interrupt.

0x1 : CHB_COV_TO_INT_EN_1

Enable logical channel B conversion time out interrupt.

End of enumeration elements list.

CHC_COV_TO_INT_EN : Channel C Conversion Time Out Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : CHC_COV_TO_INT_EN_0

Disable logical channel C conversion time out interrupt.

0x1 : CHC_COV_TO_INT_EN_1

Enable logical channel C conversion time out interrupt.

End of enumeration elements list.

CHD_COV_TO_INT_EN : Channel D Conversion Time Out Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : CHD_COV_TO_INT_EN_0

Disable logical channel D conversion time out interrupt.

0x1 : CHD_COV_TO_INT_EN_1

Enable logical channel D conversion time out interrupt.

End of enumeration elements list.

SW_CH_COV_TO_INT_EN : Software Channel Conversion Time Out Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SW_CH_COV_TO_INT_EN_0

Disable software channel conversion time out interrupt.

0x1 : SW_CH_COV_TO_INT_EN_1

Enable software channel conversion time out interrupt.

End of enumeration elements list.

LAST_FIFO_DATA_READ_EN : Last FIFO Data Read Enable
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : LAST_FIFO_DATA_READ_EN_0

Disable last FIFO read enable

0x1 : LAST_FIFO_DATA_READ_EN_1

Enable last FIFO read enable

End of enumeration elements list.


INT_STATUS

no description available
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_STATUS INT_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CBA_CMP CHB_CMP CHC_CMP CHD_CMP DMA_REACH_WM FIFO_UNDERRUN FIFO_OVERRUN CHA_COV CHB_COV CHC_COV CHD_COV SW_CH_COV CHA_COV_TO CHB_COV_TO CHC_COV_TO CHD_COV_TO SW_CH_COV_TO LAST_FIFO_DATA_READ

CBA_CMP : Channel A Compare (Flag)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CBA_CMP_0

Disable Channel A Compare (Flag).

0x1 : CBA_CMP_1

Enable Channel A Compare (Flag).

End of enumeration elements list.

CHB_CMP : Channel B Compare (Flag)
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : CHB_CMP_0

Disable Channel B Compare (Flag).

0x1 : CHB_CMP_1

Enable Channel B Compare (Flag).

End of enumeration elements list.

CHC_CMP : Channel C Compare (Flag)
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : CHC_CMP_0

Disable Channel C Compare (Flag).

0x1 : CHC_CMP_1

Enable Channel C Compare (Flag).

End of enumeration elements list.

CHD_CMP : Channel D Compare (Flag)
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : CHD_CMP_0

Disable Channel D Compare (Flag).

0x1 : CHD_CMP_1

Enable Channel D Compare (Flag).

End of enumeration elements list.

DMA_REACH_WM : DMA Reach Watermark Level (Flag)
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DMA_REACH_WM_0

The numbers of data in DMA FIFO has not reach the watermark level.

0x1 : DMA_REACH_WM_1

The numbers of data in DMA FIFO has reach the watermark level. Software clear / clear signal enable.

End of enumeration elements list.

FIFO_UNDERRUN : FIFO Underrun (Flag)
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : FIFO_UNDERRUN_0

Do not exist FIFO underrun (Flag).

0x1 : FIFO_UNDERRUN_1

Exist FIFO underrun (Flag). Software clear / clear signal enable.

End of enumeration elements list.

FIFO_OVERRUN : FIFO Overrun (Flag)
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : FIFO_OVERRUN_0

Disable FIFO overrun (Flag).

0x1 : FIFO_OVERRUN_1

Enable FIFO overrun (Flag).

End of enumeration elements list.

CHA_COV : Channel A Conversion (Flag)
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : CHA_COV_0

Disable channel A conversion (Flag).

0x1 : CHA_COV_1

Enable channel A conversion (Flag).

End of enumeration elements list.

CHB_COV : Channel B Conversion (Flag)
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : CHB_COV_0

Disable channel B conversion (Flag).

0x1 : CHB_COV_1

Enable channel B conversion (Flag).

End of enumeration elements list.

CHC_COV : Channel C Conversion (Flag)
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : CHC_COV_0

Disable channel C conversion (Flag).

0x1 : CHC_COV_1

Enable channel C conversion (Flag).

End of enumeration elements list.

CHD_COV : Channel D Conversion (Flag)
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : CHD_COV_0

Disable channel D conversion (Flag).

0x1 : CHD_COV_1

Enable channel D conversion (Flag).

End of enumeration elements list.

SW_CH_COV : Software Channel Conversion (Flag)
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SW_CH_COV_0

Disable software channel conversion (Flag).

0x1 : SW_CH_COV_1

Enable software channel conversion (Flag).

End of enumeration elements list.

CHA_COV_TO : Channel A Conversion Time Out
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : CHA_COV_TO_0

Logical channel A conversion time out does not exist.

0x1 : CHA_COV_TO_1

Exist logical channel A conversion time out. Software clear / clear signal enable.

End of enumeration elements list.

CHB_COV_TO : Channel B Conversion Time Out
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : CHB_COV_TO_0

Logical channel B conversion time out exist.

0x1 : CHB_COV_TO_1

Exist logical channel B conversion time out. Software clear/clear signal enable.

End of enumeration elements list.

CHC_COV_TO : Channel C Conversion Time Out
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : CHC_COV_TO_0

Logical channel C conversion time out does not exist.

0x1 : CHC_COV_TO_1

Exist logical channel C conversion time out. Software clear / clear signal enable.

End of enumeration elements list.

CHD_COV_TO : Channel D Conversion Time Out
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : CHD_COV_TO_0

Logical channel D conversion time out does not exist.

0x1 : CHD_COV_TO_1

Exist logical channel D conversion time out. Software clear / clear signal enable.

End of enumeration elements list.

SW_CH_COV_TO : Software Channel Conversion Time Out
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SW_CH_COV_TO_0

Software channel conversion time out does not exist.

0x1 : SW_CH_COV_TO_1

Exist software channel conversion time out. Software clear / clear signal enable.

End of enumeration elements list.

LAST_FIFO_DATA_READ : Last FIFO Data Read
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : LAST_FIFO_DATA_READ_0

Last FIFO data has not been read out

0x1 : LAST_FIFO_DATA_READ_1

Last FIFO data has been read out

End of enumeration elements list.


CHA_B_CNV_RSLT

Channel A and B Conversion Result
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHA_B_CNV_RSLT CHA_B_CNV_RSLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHA_CNV_RSLT CHB_CNV_RSLT

CHA_CNV_RSLT : Channel A Conversion Result
bits : 0 - 11 (12 bit)
access : read-write

CHB_CNV_RSLT : Channel B Conversion Result
bits : 16 - 27 (12 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.