Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x4000 byte (0x0)
mem_usage : registers
protection : not protected
no description available
address_offset : 0x16 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_EQ_SEL : RX Equalizer Select Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RX_EQ_SEL_0
no description available
0x1 : RX_EQ_SEL_1
Manual: Default
End of enumeration elements list.
RX_SS : RX Sense Control
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : RX_SS_0
Default
End of enumeration elements list.
RX_EQS : RX Equalizer Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : RX_EQS_0
no description available
0x1 : RX_EQS_1
Default
End of enumeration elements list.
RX_SS_PD : RX Sense Powerdown
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : RX_SS_PD_0
Default
0x1 : RX_SS_PD_1
Powerdown for Sense
End of enumeration elements list.
no description available
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXCDR : RX CDR BW Control
bits : 0 - 3 (4 bit)
access : read-write
no description available
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMP_LVL : TX De-emphasis Level Control
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : EMP_LVL_0
No de-emphasis
0x4 : EMP_LVL_4
Default for SATA
0x14 : EMP_LVL_20
3.5 dB de-emphasis
0x1E : EMP_LVL_30
-6 dB dB de-emphasis
0x1F : EMP_LVL_31
Max de-emphasis
End of enumeration elements list.
DRVR_PDH : TX Driver Option
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DRVR_PDH_0
Default for PCIe
0x1 : DRVR_PDH_1
Reduce Power consumption
End of enumeration elements list.
no description available
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDIMODE : TX BitWidth Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TDIMODE_0
20-bit Mode (Default)
0x1 : TDIMODE_1
40-bit Mode
End of enumeration elements list.
RDIMODE : RX BitWidth Select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RDIMODE_0
20-bit Mode (Default)
0x1 : RDIMODE_1
40-bit Mode
End of enumeration elements list.
COMDET_EN : Comma Detection Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : COMDET_EN_0
Comma Detection Disable
0x1 : COMDET_EN_1
Comma Detection Enable (Default)
End of enumeration elements list.
no description available
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DET_CNT : RX Detection Control
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : DET_CNT_0
No detection
0x4 : DET_CNT_4
Four K28.5 detection (Default)
End of enumeration elements list.
no description available
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRV_LVL : TX Differential Output (PCIE_TX_P/PCIE_TX_N) Amplitude Control
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : DRV_LVL_0
Minimum Swing
0x20 : DRV_LVL_32
Default Swing for SATA
0x2A : DRV_LVL_42
Default Swing for PCIe
0x3F : DRV_LVL_63
Maximum Swing
End of enumeration elements list.
no description available
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXEQS : RX Equalizer Setting
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x4 : RXEQS_4
Default
End of enumeration elements list.
RXEQ : RX Equalizer Control
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x4 : RXEQ_4
Default
End of enumeration elements list.
no description available
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQTH : RX Squelch Detect Threshold Control
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : SQTH_0
Min threshold
0x3 : SQTH_3
Default threshold voltage of squelch detect
0x7 : SQTH_7
Max threshold
End of enumeration elements list.
no description available
address_offset : 0x96 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BIAS : TRSV Bias Current Control
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x4 : BIAS_4
Default for SATA
0xC : BIAS_12
Default for PCIe
End of enumeration elements list.
no description available
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD_TSV : Transceiver Block All Powerdown Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PD_TSV_0
Transceiver Block powerdown disable
0x1 : PD_TSV_1
Transceiver Block powerdown enable
End of enumeration elements list.
no description available
address_offset : 0xB2 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
no description available
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SR_LVL : TX Slew-rate Control
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : SR_LVL_0
Default (~ 60 pS)
0x1 : SR_LVL_1
~ 90 pS
0x2 : SR_LVL_2
~ 120 pS
0x3 : SR_LVL_3
~ 150 pS
End of enumeration elements list.
TX_SWING : TX Driver Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TX_SWING_0
Full-swing (Default)
0x1 : TX_SWING_1
Half-swing
End of enumeration elements list.
DRVR_CNT : TX Driver Common Mode Control
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : DRVR_CNT_0
Default for SATA
0x3 : DRVR_CNT_3
Default for PCIe
End of enumeration elements list.
no description available
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
no description available
address_offset : 0xD2 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADD_ALIGN : Align Primitive Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : ADD_ALIGN_0
No
0x1 : ADD_ALIGN_1
ALIGNp is added.
End of enumeration elements list.
RX_INV : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : RX_INV_0
Normal Mode (Default Value)
0x1 : RX_INV_1
PCIE_RX_P/PCIE_RX_N Output Data
End of enumeration elements list.
TX_INV : TX Inversion Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : TX_INV_0
Normal Mode (Default Value)
0x1 : TX_INV_1
PCIE_TX_P/PCIE_TX_N Output Data
End of enumeration elements list.
no description available
address_offset : 0xD6 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TD_ORD : TX Bit Order Control
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : TD_ORD_0
No Order Reverse. TXD[0] to TXD[9] is transmitted and then TXD[10] to TXD[19] is transmitted for TXD[0:19].
0x1 : TD_ORD_1
Bit Order Reverse. TXD[9] to TXD[0] is transmitted and then TXD[19] to TXD[10] is transmitted.
0x2 : TD_ORD_2
Byte Order Reverse. TXD[10] to TXD[19] is transmitted and then TXD[0] to TXD[9] is transmitted.
0x3 : TD_ORD_3
Bit and Byte Order Reverse. RXD[19] to RXD[10] is received and then RXD[9] to RXD[0] is received.
End of enumeration elements list.
RD_ORD : RX Bit Order Control
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : RD_ORD_0
No Order Reverse. RXD[0] to RXD[9] is received and then RXD[10] to RXD[19] is received for RXD[0:19].
0x1 : RD_ORD_1
Bit Order Reverse. RXD[9] to RXD[0] is received and then RXD[19] to RXD[10] is received.
0x2 : RD_ORD_2
Byte Order Reverse. RXD[10] to RXD[19] is received and then RXD[0] to RXD[9] is received.
0x3 : RD_ORD_3
Bit and Byte Order Reverse. RXD[19] to RXD[10] is received and then RXD[9] to RXD[0] is received.
End of enumeration elements list.
no description available
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD_TRAS : TRSV Sub-block Powerdown
bits : 2 - 6 (5 bit)
access : read-write
Enumeration:
0 : PD_TRAS_0
Enable
End of enumeration elements list.
PHY_TRSV_EN : TRSV Sub-block PD Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PHY_TRSV_EN_0
Disabled for TRSV block PD control
0x1 : PHY_TRSV_EN_1
Enabled for TRSV block PD control
End of enumeration elements list.
no description available
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRSVRST : TRSV Reset Control
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x80 : TRSVRST_128
Fine control option for RESET
0xFF : TRSVRST_255
Fine control option for RESET
End of enumeration elements list.
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