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DDRC_MP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xB28 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PSTAT

PCFGIDMASKCH_50

PCFGIDVALUECH_50

PCFGIDMASKCH_60

SARBASE0

SARSIZE0

PCFGIDVALUECH_60

PCFGIDMASKCH_70

PCFGIDVALUECH_70

PCFGIDMASKCH_80

PCFGIDVALUECH_80

SARBASE1

SARSIZE1

PCFGIDMASKCH_90

PCFGIDVALUECH_90

PCFGIDMASKCH_00

PCFGIDMASKCH_100

SARBASE2

SARSIZE2

PCFGIDVALUECH_100

PCFGIDVALUECH_00

PCFGIDMASKCH_110

PCFGIDVALUECH_110

SARBASE3

SARSIZE3

PCFGIDMASKCH_120

PCFGIDVALUECH_120

PCCFG

PCFGIDMASKCH_130

PCFGIDMASKCH_10

PCFGIDVALUECH_130

PCFGIDMASKCH_140

PCFGIDVALUECH_140

PCFGIDVALUECH_10

PCFGIDMASKCH_150

PCFGIDVALUECH_150

PCFGIDMASKCH_20

PCFGIDVALUECH_20

PCFGR_0

PCFGIDMASKCH_30

PCTRL_0

PCFGQOS0_0

PCFGQOS1_0

PCFGWQOS0_0

PCFGWQOS1_0

PCFGIDVALUECH_30

PCFGW_0

PCFGIDMASKCH_40

PCFGIDVALUECH_40


PSTAT

Port Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PSTAT PSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_PORT_BUSY_0

RD_PORT_BUSY_0 : Indicates if there are outstanding reads for port 0
bits : 0 - 0 (1 bit)
access : read-only


PCFGIDMASKCH_50

Port n Channel m Configuration ID Mask Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDMASKCH_50 PCFGIDMASKCH_50 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_MASK

ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDVALUECH_50

Port n Channel m Configuration ID Value Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDVALUECH_50 PCFGIDVALUECH_50 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_VALUE

ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDMASKCH_60

Port n Channel m Configuration ID Mask Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDMASKCH_60 PCFGIDMASKCH_60 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_MASK

ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


SARBASE0

SAR Base Address Register n
address_offset : 0x1610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARBASE0 SARBASE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE_ADDR

BASE_ADDR : Base address for address region n specified as awaddr[DDRC_A_ADDRW-1:x]and araddr[DDRC_A_ADDRW-1:x] where x is determined by the minimum block size parameter DDRC_SARMINSIZE: (x = log2 (block size))
bits : 0 - 31 (32 bit)
access : read-write


SARSIZE0

SAR Size Register n
address_offset : 0x1618 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARSIZE0 SARSIZE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NBLOCKS

NBLOCKS : Number of blocks for address region n
bits : 0 - 7 (8 bit)
access : read-write


PCFGIDVALUECH_60

Port n Channel m Configuration ID Value Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDVALUECH_60 PCFGIDVALUECH_60 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_VALUE

ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDMASKCH_70

Port n Channel m Configuration ID Mask Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDMASKCH_70 PCFGIDMASKCH_70 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_MASK

ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDVALUECH_70

Port n Channel m Configuration ID Value Register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDVALUECH_70 PCFGIDVALUECH_70 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_VALUE

ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDMASKCH_80

Port n Channel m Configuration ID Mask Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDMASKCH_80 PCFGIDMASKCH_80 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_MASK

ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDVALUECH_80

Port n Channel m Configuration ID Value Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDVALUECH_80 PCFGIDVALUECH_80 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_VALUE

ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


SARBASE1

SAR Base Address Register n
address_offset : 0x2120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARBASE1 SARBASE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE_ADDR

BASE_ADDR : Base address for address region n specified as awaddr[DDRC_A_ADDRW-1:x]and araddr[DDRC_A_ADDRW-1:x] where x is determined by the minimum block size parameter DDRC_SARMINSIZE: (x = log2 (block size))
bits : 0 - 31 (32 bit)
access : read-write


SARSIZE1

SAR Size Register n
address_offset : 0x212C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARSIZE1 SARSIZE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NBLOCKS

NBLOCKS : Number of blocks for address region n
bits : 0 - 7 (8 bit)
access : read-write


PCFGIDMASKCH_90

Port n Channel m Configuration ID Mask Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDMASKCH_90 PCFGIDMASKCH_90 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_MASK

ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDVALUECH_90

Port n Channel m Configuration ID Value Register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDVALUECH_90 PCFGIDVALUECH_90 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_VALUE

ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDMASKCH_00

Port n Channel m Configuration ID Mask Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDMASKCH_00 PCFGIDMASKCH_00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_MASK

ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDMASKCH_100

Port n Channel m Configuration ID Mask Register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDMASKCH_100 PCFGIDMASKCH_100 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_MASK

ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


SARBASE2

SAR Base Address Register n
address_offset : 0x2C38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARBASE2 SARBASE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE_ADDR

BASE_ADDR : Base address for address region n specified as awaddr[DDRC_A_ADDRW-1:x]and araddr[DDRC_A_ADDRW-1:x] where x is determined by the minimum block size parameter DDRC_SARMINSIZE: (x = log2 (block size))
bits : 0 - 31 (32 bit)
access : read-write


SARSIZE2

SAR Size Register n
address_offset : 0x2C48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARSIZE2 SARSIZE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NBLOCKS

NBLOCKS : Number of blocks for address region n
bits : 0 - 7 (8 bit)
access : read-write


PCFGIDVALUECH_100

Port n Channel m Configuration ID Value Register
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDVALUECH_100 PCFGIDVALUECH_100 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_VALUE

ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDVALUECH_00

Port n Channel m Configuration ID Value Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDVALUECH_00 PCFGIDVALUECH_00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_VALUE

ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDMASKCH_110

Port n Channel m Configuration ID Mask Register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDMASKCH_110 PCFGIDMASKCH_110 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_MASK

ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDVALUECH_110

Port n Channel m Configuration ID Value Register
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDVALUECH_110 PCFGIDVALUECH_110 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_VALUE

ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


SARBASE3

SAR Base Address Register n
address_offset : 0x3758 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARBASE3 SARBASE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE_ADDR

BASE_ADDR : Base address for address region n specified as awaddr[DDRC_A_ADDRW-1:x]and araddr[DDRC_A_ADDRW-1:x] where x is determined by the minimum block size parameter DDRC_SARMINSIZE: (x = log2 (block size))
bits : 0 - 31 (32 bit)
access : read-write


SARSIZE3

SAR Size Register n
address_offset : 0x376C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SARSIZE3 SARSIZE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NBLOCKS

NBLOCKS : Number of blocks for address region n
bits : 0 - 7 (8 bit)
access : read-write


PCFGIDMASKCH_120

Port n Channel m Configuration ID Mask Register
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDMASKCH_120 PCFGIDMASKCH_120 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_MASK

ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDVALUECH_120

Port n Channel m Configuration ID Value Register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDVALUECH_120 PCFGIDVALUECH_120 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_VALUE

ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCCFG

Port Common Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCCFG PCCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GO2CRITICAL_EN PAGEMATCH_LIMIT

GO2CRITICAL_EN : If set to 1 (enabled), sets hif_go2critical_wr and hif_go2critical_lpr / hif_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master
bits : 0 - 0 (1 bit)
access : read-write

PAGEMATCH_LIMIT : Page Match Four Limit
bits : 4 - 4 (1 bit)
access : read-write


PCFGIDMASKCH_130

Port n Channel m Configuration ID Mask Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDMASKCH_130 PCFGIDMASKCH_130 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_MASK

ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDMASKCH_10

Port n Channel m Configuration ID Mask Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDMASKCH_10 PCFGIDMASKCH_10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_MASK

ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDVALUECH_130

Port n Channel m Configuration ID Value Register
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDVALUECH_130 PCFGIDVALUECH_130 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_VALUE

ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDMASKCH_140

Port n Channel m Configuration ID Mask Register
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDMASKCH_140 PCFGIDMASKCH_140 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_MASK

ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDVALUECH_140

Port n Channel m Configuration ID Value Register
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDVALUECH_140 PCFGIDVALUECH_140 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_VALUE

ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDVALUECH_10

Port n Channel m Configuration ID Value Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDVALUECH_10 PCFGIDVALUECH_10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_VALUE

ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDMASKCH_150

Port n Channel m Configuration ID Mask Register
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDMASKCH_150 PCFGIDMASKCH_150 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_MASK

ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDVALUECH_150

Port n Channel m Configuration ID Value Register
address_offset : 0x558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDVALUECH_150 PCFGIDVALUECH_150 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_VALUE

ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDMASKCH_20

Port n Channel m Configuration ID Mask Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDMASKCH_20 PCFGIDMASKCH_20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_MASK

ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDVALUECH_20

Port n Channel m Configuration ID Value Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDVALUECH_20 PCFGIDVALUECH_20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_VALUE

ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGR_0

Port n Configuration Read Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGR_0 PCFGR_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_PORT_PRIORITY READ_REORDER_BYPASS_EN RD_PORT_AGING_EN RD_PORT_URGENT_EN RD_PORT_PAGEMATCH_EN RDWR_ORDERED_EN

RD_PORT_PRIORITY : Determines the initial load value of read aging counters
bits : 0 - 9 (10 bit)
access : read-write

READ_REORDER_BYPASS_EN : If set to 1, read transactions with ID not covered by any of the virtual channel ID mapping registers are not reordered
bits : 11 - 11 (1 bit)
access : read-write

RD_PORT_AGING_EN : If set to 1, enables aging function for the read channel of the port
bits : 12 - 12 (1 bit)
access : read-write

RD_PORT_URGENT_EN : If set to 1, enables the AXI urgent sideband signal (arurgent)
bits : 13 - 13 (1 bit)
access : read-write

RD_PORT_PAGEMATCH_EN : If set to 1, enables the Page Match feature
bits : 14 - 14 (1 bit)
access : read-write

RDWR_ORDERED_EN : Enable ordered read / writes
bits : 16 - 16 (1 bit)
access : read-write


PCFGIDMASKCH_30

Port n Channel m Configuration ID Mask Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDMASKCH_30 PCFGIDMASKCH_30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_MASK

ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCTRL_0

Port n Control Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCTRL_0 PCTRL_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_EN

PORT_EN : Enables port n Value After Reset: DDRC_PORT_EN_RESET_VALUE Exists: Always
bits : 0 - 0 (1 bit)
access : read-write


PCFGQOS0_0

Port n Read QoS Configuration Register 0
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGQOS0_0 PCFGQOS0_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RQOS_MAP_LEVEL1 RQOS_MAP_LEVEL2 RQOS_MAP_REGION0 RQOS_MAP_REGION1 RQOS_MAP_REGION2

RQOS_MAP_LEVEL1 : Separation level1 indicating the end of region0 mapping; start of region0 is 0
bits : 0 - 3 (4 bit)
access : read-write

RQOS_MAP_LEVEL2 : Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1)
bits : 8 - 11 (4 bit)
access : read-write

RQOS_MAP_REGION0 : This bitfield indicates the traffic class of region 0
bits : 16 - 17 (2 bit)
access : read-write

RQOS_MAP_REGION1 : This bitfield indicates the traffic class of region 1
bits : 20 - 21 (2 bit)
access : read-write

RQOS_MAP_REGION2 : This bitfield indicates the traffic class of region2
bits : 24 - 25 (2 bit)
access : read-write


PCFGQOS1_0

Port n Read QoS Configuration Register 1
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGQOS1_0 PCFGQOS1_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RQOS_MAP_TIMEOUTB RQOS_MAP_TIMEOUTR

RQOS_MAP_TIMEOUTB : Specifies the timeout value for transactions mapped to the blue address queue
bits : 0 - 10 (11 bit)
access : read-write

RQOS_MAP_TIMEOUTR : Specifies the timeout value for transactions mapped to the red address queue
bits : 16 - 26 (11 bit)
access : read-write


PCFGWQOS0_0

Port n Write QoS Configuration Register 0
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGWQOS0_0 PCFGWQOS0_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WQOS_MAP_LEVEL WQOS_MAP_REGION0 WQOS_MAP_REGION1

WQOS_MAP_LEVEL : Separation level indicating the end of region0 mapping; start of region0 is 0
bits : 0 - 3 (4 bit)
access : read-write

WQOS_MAP_REGION0 : This bitfield indicates the traffic class of region 0
bits : 16 - 17 (2 bit)
access : read-write

WQOS_MAP_REGION1 : This bitfield indicates the traffic class of region 1
bits : 20 - 21 (2 bit)
access : read-write


PCFGWQOS1_0

Port n Write QoS Configuration Register 1
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGWQOS1_0 PCFGWQOS1_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WQOS_MAP_TIMEOUT

WQOS_MAP_TIMEOUT : Specifies the timeout value for write transactions. Value After Reset: 0x0 Exists: Always
bits : 0 - 10 (11 bit)
access : read-write


PCFGIDVALUECH_30

Port n Channel m Configuration ID Value Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDVALUECH_30 PCFGIDVALUECH_30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_VALUE

ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGW_0

Port n Configuration Write Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGW_0 PCFGW_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WR_PORT_PRIORITY WR_PORT_AGING_EN WR_PORT_URGENT_EN WR_PORT_PAGEMATCH_EN

WR_PORT_PRIORITY : Determines the initial load value of write aging counters
bits : 0 - 9 (10 bit)
access : read-write

WR_PORT_AGING_EN : If set to 1, enables aging function for the write channel of the port
bits : 12 - 12 (1 bit)
access : read-write

WR_PORT_URGENT_EN : If set to 1, enables the AXI urgent sideband signal (awurgent)
bits : 13 - 13 (1 bit)
access : read-write

WR_PORT_PAGEMATCH_EN : If set to 1, enables the Page Match feature
bits : 14 - 14 (1 bit)
access : read-write


PCFGIDMASKCH_40

Port n Channel m Configuration ID Mask Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDMASKCH_40 PCFGIDMASKCH_40 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_MASK

ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write


PCFGIDVALUECH_40

Port n Channel m Configuration ID Value Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGIDVALUECH_40 PCFGIDVALUECH_40 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID_VALUE

ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write



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