\n
address_offset : 0x0 Bytes (0x0)
size : 0xB28 byte (0x0)
mem_usage : registers
protection : not protected
Port Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD_PORT_BUSY_0 : Indicates if there are outstanding reads for port 0
bits : 0 - 0 (1 bit)
access : read-only
Port n Channel m Configuration ID Mask Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Value Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Mask Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
SAR Base Address Register n
address_offset : 0x1610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE_ADDR : Base address for address region n specified as awaddr[DDRC_A_ADDRW-1:x]and araddr[DDRC_A_ADDRW-1:x] where x is determined by the minimum block size parameter DDRC_SARMINSIZE: (x = log2 (block size))
bits : 0 - 31 (32 bit)
access : read-write
SAR Size Register n
address_offset : 0x1618 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NBLOCKS : Number of blocks for address region n
bits : 0 - 7 (8 bit)
access : read-write
Port n Channel m Configuration ID Value Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Mask Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Value Register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Mask Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Value Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
SAR Base Address Register n
address_offset : 0x2120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE_ADDR : Base address for address region n specified as awaddr[DDRC_A_ADDRW-1:x]and araddr[DDRC_A_ADDRW-1:x] where x is determined by the minimum block size parameter DDRC_SARMINSIZE: (x = log2 (block size))
bits : 0 - 31 (32 bit)
access : read-write
SAR Size Register n
address_offset : 0x212C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NBLOCKS : Number of blocks for address region n
bits : 0 - 7 (8 bit)
access : read-write
Port n Channel m Configuration ID Mask Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Value Register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Mask Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Mask Register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
SAR Base Address Register n
address_offset : 0x2C38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE_ADDR : Base address for address region n specified as awaddr[DDRC_A_ADDRW-1:x]and araddr[DDRC_A_ADDRW-1:x] where x is determined by the minimum block size parameter DDRC_SARMINSIZE: (x = log2 (block size))
bits : 0 - 31 (32 bit)
access : read-write
SAR Size Register n
address_offset : 0x2C48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NBLOCKS : Number of blocks for address region n
bits : 0 - 7 (8 bit)
access : read-write
Port n Channel m Configuration ID Value Register
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Value Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Mask Register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Value Register
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
SAR Base Address Register n
address_offset : 0x3758 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE_ADDR : Base address for address region n specified as awaddr[DDRC_A_ADDRW-1:x]and araddr[DDRC_A_ADDRW-1:x] where x is determined by the minimum block size parameter DDRC_SARMINSIZE: (x = log2 (block size))
bits : 0 - 31 (32 bit)
access : read-write
SAR Size Register n
address_offset : 0x376C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NBLOCKS : Number of blocks for address region n
bits : 0 - 7 (8 bit)
access : read-write
Port n Channel m Configuration ID Mask Register
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Value Register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port Common Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GO2CRITICAL_EN : If set to 1 (enabled), sets hif_go2critical_wr and hif_go2critical_lpr / hif_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master
bits : 0 - 0 (1 bit)
access : read-write
PAGEMATCH_LIMIT : Page Match Four Limit
bits : 4 - 4 (1 bit)
access : read-write
Port n Channel m Configuration ID Mask Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Mask Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Value Register
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Mask Register
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Value Register
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Value Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Mask Register
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Value Register
address_offset : 0x558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Mask Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Value Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Configuration Read Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_PORT_PRIORITY : Determines the initial load value of read aging counters
bits : 0 - 9 (10 bit)
access : read-write
READ_REORDER_BYPASS_EN : If set to 1, read transactions with ID not covered by any of the virtual channel ID mapping registers are not reordered
bits : 11 - 11 (1 bit)
access : read-write
RD_PORT_AGING_EN : If set to 1, enables aging function for the read channel of the port
bits : 12 - 12 (1 bit)
access : read-write
RD_PORT_URGENT_EN : If set to 1, enables the AXI urgent sideband signal (arurgent)
bits : 13 - 13 (1 bit)
access : read-write
RD_PORT_PAGEMATCH_EN : If set to 1, enables the Page Match feature
bits : 14 - 14 (1 bit)
access : read-write
RDWR_ORDERED_EN : Enable ordered read / writes
bits : 16 - 16 (1 bit)
access : read-write
Port n Channel m Configuration ID Mask Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Control Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORT_EN : Enables port n Value After Reset: DDRC_PORT_EN_RESET_VALUE Exists: Always
bits : 0 - 0 (1 bit)
access : read-write
Port n Read QoS Configuration Register 0
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RQOS_MAP_LEVEL1 : Separation level1 indicating the end of region0 mapping; start of region0 is 0
bits : 0 - 3 (4 bit)
access : read-write
RQOS_MAP_LEVEL2 : Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1)
bits : 8 - 11 (4 bit)
access : read-write
RQOS_MAP_REGION0 : This bitfield indicates the traffic class of region 0
bits : 16 - 17 (2 bit)
access : read-write
RQOS_MAP_REGION1 : This bitfield indicates the traffic class of region 1
bits : 20 - 21 (2 bit)
access : read-write
RQOS_MAP_REGION2 : This bitfield indicates the traffic class of region2
bits : 24 - 25 (2 bit)
access : read-write
Port n Read QoS Configuration Register 1
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RQOS_MAP_TIMEOUTB : Specifies the timeout value for transactions mapped to the blue address queue
bits : 0 - 10 (11 bit)
access : read-write
RQOS_MAP_TIMEOUTR : Specifies the timeout value for transactions mapped to the red address queue
bits : 16 - 26 (11 bit)
access : read-write
Port n Write QoS Configuration Register 0
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WQOS_MAP_LEVEL : Separation level indicating the end of region0 mapping; start of region0 is 0
bits : 0 - 3 (4 bit)
access : read-write
WQOS_MAP_REGION0 : This bitfield indicates the traffic class of region 0
bits : 16 - 17 (2 bit)
access : read-write
WQOS_MAP_REGION1 : This bitfield indicates the traffic class of region 1
bits : 20 - 21 (2 bit)
access : read-write
Port n Write QoS Configuration Register 1
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WQOS_MAP_TIMEOUT : Specifies the timeout value for write transactions. Value After Reset: 0x0 Exists: Always
bits : 0 - 10 (11 bit)
access : read-write
Port n Channel m Configuration ID Value Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Configuration Write Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR_PORT_PRIORITY : Determines the initial load value of write aging counters
bits : 0 - 9 (10 bit)
access : read-write
WR_PORT_AGING_EN : If set to 1, enables aging function for the write channel of the port
bits : 12 - 12 (1 bit)
access : read-write
WR_PORT_URGENT_EN : If set to 1, enables the AXI urgent sideband signal (awurgent)
bits : 13 - 13 (1 bit)
access : read-write
WR_PORT_PAGEMATCH_EN : If set to 1, enables the Page Match feature
bits : 14 - 14 (1 bit)
access : read-write
Port n Channel m Configuration ID Mask Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MASK : Determines the mask used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
Port n Channel m Configuration ID Value Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_VALUE : Determines the value used in the ID mapping function for virtual channel m
bits : 0 - 31 (32 bit)
access : read-write
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