Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
Processor B Transmit Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTR0 : Processor B Transmit Register 0
bits : 0 - 31 (32 bit)
access : read-write
Processor B Receive Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BRR0 : Processor B Receive Register 0
bits : 0 - 31 (32 bit)
access : read-only
Processor B Receive Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BRR1 : Processor B Receive Register 1
bits : 0 - 31 (32 bit)
access : read-only
Processor B Receive Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BRR2 : Processor B Receive Register 2
bits : 0 - 31 (32 bit)
access : read-only
Processor B Receive Register 3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BRR3 : Processor B Receive Register 3
bits : 0 - 31 (32 bit)
access : read-only
Processor B Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Fn : For n = {0, 1, 2} Processor B-Side Flag n
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : Fn_0
BAFn bit in BCR register is written 0 (default).
0x1 : Fn_1
BAFn bit in BCR register is written 1.
End of enumeration elements list.
EP : Processor B-Side Event Pending
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : EP_0
The Processor B-side event is not pending (default).
0x1 : EP_1
The Processor B-side event is pending.
End of enumeration elements list.
APM : Processor A Power Mode. (Read-only)
bits : 5 - 6 (2 bit)
access : read-only
Enumeration:
0 : APM_0
The System is in Run Mode.
0x1 : APM_1
The System is in Run Mode.
0x3 : APM_3
The System is in STOP Mode.
End of enumeration elements list.
ARS : Processor A-side Reset State
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ARS_0
The Processor B-side of the MU is not in reset.
0x1 : ARS_1
The Processor B-side of the MU is in reset.
End of enumeration elements list.
FUP : Processor B Flags Update Pending
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : FUP_0
No flags updated, initiated by the Processor B, in progress (default)
0x1 : FUP_1
Processor B initiated flags update, processing
End of enumeration elements list.
TEn : For n = {0, 1, 2, 3} Processor B Transmit Register n Empty
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0 : TEn_0
ATRn register is not empty.
0x1 : TEn_1
ATRn register is empty (default).
End of enumeration elements list.
RFn : For n = {0, 1, 2, 3} Processor B Receive Register n Full
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : RFn_0
ARRn register is not full (default).
0x1 : RFn_1
ARRn register has received data from BTRn register and is ready to be read by the Processor B.
End of enumeration elements list.
GIPn : For n = {0, 1, 2, 3} Processor B General Interrupt Request n Pending
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : GIPn_0
Processor B general purpose interrupt n is not pending. (default)
0x1 : GIPn_1
Processor B general purpose interrupt n is pending.
End of enumeration elements list.
Processor B Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BAFn : For n = {0, 1, 2} Processor B to Processor B Flag n
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : BAFn_0
Clears the Fn bit in the ASR register.
0x1 : BAFn_1
Sets the Fn bit in the ASR register.
End of enumeration elements list.
HRM : Processor B Hardware Reset
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : HRM_0
BHR bit in ACR is not masked, enables the hardware reset to the Processor B (default after hardware reset).
0x1 : HRM_1
BHR bit in ACR is masked, disables the hardware reset request to the Processor B.
End of enumeration elements list.
GIRn : For n = {0, 1, 2, 3} Processor B General Purpose Interrupt Request n
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : GIRn_0
Processor B General Interrupt n is not requested to the Processor B (default).
0x1 : GIRn_1
Processor B General Interrupt n is requested to the Processor B.
End of enumeration elements list.
TIEn : For n = {0, 1, 2, 3} Processor B Transmit Interrupt Enable n
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0 : TIEn_0
Disables Processor B Transmit Interrupt n. (default)
0x1 : TIEn_1
Enables Processor B Transmit Interrupt n.
End of enumeration elements list.
RIEn : For n = {0, 1, 2, 3} Processor B Receive Interrupt Enable n
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : RIEn_0
Disables Processor B Receive Interrupt n. (default)
0x1 : RIEn_1
Enables Processor B Receive Interrupt n.
End of enumeration elements list.
GIEn : For n = {0, 1, 2, 3} Processor B General Purpose Interrupt Enable n
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : GIEn_0
Disables Processor B General Interrupt n. (default)
0x1 : GIEn_1
Enables Processor B General Interrupt n.
End of enumeration elements list.
Processor B Transmit Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTR1 : Processor B Transmit Register 1
bits : 0 - 31 (32 bit)
access : read-write
Processor B Transmit Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTR2 : Processor B Transmit Register 2
bits : 0 - 31 (32 bit)
access : read-write
Processor B Transmit Register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTR3 : Processor B Transmit Register 3
bits : 0 - 31 (32 bit)
access : read-write
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