Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x804 byte (0x0)
mem_usage : registers
protection : not protected
AHB to APBH Bridge Control and Status Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKGATE_CHANNEL : These bits must be set to zero for normal operation of each channel
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0x1 : NAND0
NAND0
0x2 : NAND1
NAND1
0x4 : NAND2
NAND2
0x8 : NAND3
NAND3
0x10 : NAND4
NAND4
0x20 : NAND5
NAND5
0x40 : NAND6
NAND6
0x80 : NAND7
NAND7
0x100 : SSP
SSP
End of enumeration elements list.
APB_BURST_EN : Set this bit to one to enable apb master do a continous transfers when a device request a burst dma
bits : 28 - 28 (1 bit)
access : read-write
AHB_BURST8_EN : Set this bit to one (default) to enable AHB 8-beat burst
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : This bit must be set to zero for normal operation
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : Set this bit to zero to enable normal APBH DMA operation
bits : 31 - 31 (1 bit)
access : read-write
AHB to APBH Bridge Control and Status Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 0
bits : 0 - 0 (1 bit)
access : read-write
CH1_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 1
bits : 1 - 1 (1 bit)
access : read-write
CH2_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 2
bits : 2 - 2 (1 bit)
access : read-write
CH3_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 3
bits : 3 - 3 (1 bit)
access : read-write
CH4_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 4
bits : 4 - 4 (1 bit)
access : read-write
CH5_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 5
bits : 5 - 5 (1 bit)
access : read-write
CH6_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 6
bits : 6 - 6 (1 bit)
access : read-write
CH7_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 7
bits : 7 - 7 (1 bit)
access : read-write
CH8_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 8
bits : 8 - 8 (1 bit)
access : read-write
CH9_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 9
bits : 9 - 9 (1 bit)
access : read-write
CH10_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 10
bits : 10 - 10 (1 bit)
access : read-write
CH11_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 11
bits : 11 - 11 (1 bit)
access : read-write
CH12_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 12
bits : 12 - 12 (1 bit)
access : read-write
CH13_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 13
bits : 13 - 13 (1 bit)
access : read-write
CH14_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 14
bits : 14 - 14 (1 bit)
access : read-write
CH15_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 15
bits : 15 - 15 (1 bit)
access : read-write
CH0_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 0.
bits : 16 - 16 (1 bit)
access : read-write
CH1_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 1.
bits : 17 - 17 (1 bit)
access : read-write
CH2_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 2.
bits : 18 - 18 (1 bit)
access : read-write
CH3_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 3.
bits : 19 - 19 (1 bit)
access : read-write
CH4_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 4.
bits : 20 - 20 (1 bit)
access : read-write
CH5_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 5.
bits : 21 - 21 (1 bit)
access : read-write
CH6_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 6.
bits : 22 - 22 (1 bit)
access : read-write
CH7_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 7.
bits : 23 - 23 (1 bit)
access : read-write
CH8_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 8.
bits : 24 - 24 (1 bit)
access : read-write
CH9_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 9.
bits : 25 - 25 (1 bit)
access : read-write
CH10_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 10.
bits : 26 - 26 (1 bit)
access : read-write
CH11_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 11.
bits : 27 - 27 (1 bit)
access : read-write
CH12_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 12.
bits : 28 - 28 (1 bit)
access : read-write
CH13_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 13.
bits : 29 - 29 (1 bit)
access : read-write
CH14_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 14.
bits : 30 - 30 (1 bit)
access : read-write
CH15_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 15.
bits : 31 - 31 (1 bit)
access : read-write
AHB to APBH DMA Channel n Debug Information
address_offset : 0x1030 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHB_BYTES : This value reflects the current number of AHB bytes remaining to be transfered in the current transfer
bits : 0 - 15 (16 bit)
access : read-only
APB_BYTES : This value reflects the current number of APB bytes remaining to be transfered in the current transfer
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Current Command Address Register
address_offset : 0x1130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to command structure currently being processed for channel n.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Next Command Address Register
address_offset : 0x11B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to next command structure for channel n.
bits : 0 - 31 (32 bit)
access : read-write
APBH DMA Channel n Command Register
address_offset : 0x1230 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMMAND : This bitfield indicates the type of current command:
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : NO_DMA_XFER
Perform any requested PIO word transfers but terminate command before any DMA transfer.
0x1 : DMA_WRITE
Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
0x2 : DMA_READ
Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
0x3 : DMA_SENSE
Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
End of enumeration elements list.
CHAIN : A value of one indicates that another command is chained onto the end of the current command structure
bits : 2 - 2 (1 bit)
access : read-only
IRQONCMPLT : A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i
bits : 3 - 3 (1 bit)
access : read-only
NANDLOCK : A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels
bits : 4 - 4 (1 bit)
access : read-only
NANDWAIT4READY : A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command
bits : 5 - 5 (1 bit)
access : read-only
SEMAPHORE : A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure
bits : 6 - 6 (1 bit)
access : read-only
WAIT4ENDCMD : A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command
bits : 7 - 7 (1 bit)
access : read-only
HALTONTERMINATE : A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set
bits : 8 - 8 (1 bit)
access : read-only
CMDWORDS : This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there
bits : 12 - 15 (4 bit)
access : read-only
XFER_COUNT : This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Buffer Address Register
address_offset : 0x12B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of system memory buffer to be read or written over the AHB bus.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Semaphore Register
address_offset : 0x1330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_SEMA : The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
PHORE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x13B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATEMACHINE : PIO Display of the DMA Channel n state machine state.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : IDLE
This is the idle state of the DMA state machine.
0x1 : REQ_CMD1
State in which the DMA is waiting to receive the first word of a command.
0x2 : REQ_CMD3
State in which the DMA is waiting to receive the third word of a command.
0x3 : REQ_CMD2
State in which the DMA is waiting to receive the second word of a command.
0x4 : XFER_DECODE
The state machine processes the descriptor command field in this state and branches accordingly.
0x5 : REQ_WAIT
The state machine waits in this state for the PIO APB cycles to complete.
0x6 : REQ_CMD4
State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
0x7 : PIO_REQ
This state determines whether another PIO cycle needs to occur before starting DMA transfers.
0x8 : READ_FLUSH
During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
0x9 : READ_WAIT
When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
0xC : WRITE
During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xD : READ_REQ
During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xE : CHECK_CHAIN
Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
0xF : XFER_COMPLETE
The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
0x14 : TERMINATE
When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
0x15 : WAIT_END
When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
0x1C : WRITE_WAIT
During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
0x1D : HALT_AFTER_TERM
If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
0x1E : CHECK_WAIT
If the Chain bit is a 0, the state machine enters this state and effectively halts.
0x1F : WAIT_READY
When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
End of enumeration elements list.
WR_FIFO_FULL : This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
bits : 20 - 20 (1 bit)
access : read-only
WR_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
bits : 21 - 21 (1 bit)
access : read-only
RD_FIFO_FULL : This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
bits : 22 - 22 (1 bit)
access : read-only
RD_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
bits : 23 - 23 (1 bit)
access : read-only
NEXTCMDADDRVALID : This bit reflects the internal bit which indicates whether the channel's next command address is valid
bits : 24 - 24 (1 bit)
access : read-only
READY : This bit is reserved for this DMA Channel and always reads 0.
bits : 26 - 26 (1 bit)
access : read-only
END : This bit reflects the current state of the DMA End Command Signal sent from the APB Device
bits : 28 - 28 (1 bit)
access : read-only
KICK : This bit reflects the current state of the DMA Kick Signal sent to the APB Device
bits : 29 - 29 (1 bit)
access : read-only
BURST : This bit reflects the current state of the DMA Burst Signal from the APB device
bits : 30 - 30 (1 bit)
access : read-only
REQ : This bit reflects the current state of the DMA Request Signal from the APB device
bits : 31 - 31 (1 bit)
access : read-only
AHB to APBH Bridge Control and Status Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 0
bits : 0 - 0 (1 bit)
access : read-write
CH1_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 1
bits : 1 - 1 (1 bit)
access : read-write
CH2_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 2
bits : 2 - 2 (1 bit)
access : read-write
CH3_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 3
bits : 3 - 3 (1 bit)
access : read-write
CH4_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 4
bits : 4 - 4 (1 bit)
access : read-write
CH5_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 5
bits : 5 - 5 (1 bit)
access : read-write
CH6_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 6
bits : 6 - 6 (1 bit)
access : read-write
CH7_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 7
bits : 7 - 7 (1 bit)
access : read-write
CH8_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 8
bits : 8 - 8 (1 bit)
access : read-write
CH9_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 9
bits : 9 - 9 (1 bit)
access : read-write
CH10_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 10
bits : 10 - 10 (1 bit)
access : read-write
CH11_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 11
bits : 11 - 11 (1 bit)
access : read-write
CH12_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 12
bits : 12 - 12 (1 bit)
access : read-write
CH13_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 13
bits : 13 - 13 (1 bit)
access : read-write
CH14_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 14
bits : 14 - 14 (1 bit)
access : read-write
CH15_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 15
bits : 15 - 15 (1 bit)
access : read-write
CH0_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 0.
bits : 16 - 16 (1 bit)
access : read-write
CH1_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 1.
bits : 17 - 17 (1 bit)
access : read-write
CH2_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 2.
bits : 18 - 18 (1 bit)
access : read-write
CH3_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 3.
bits : 19 - 19 (1 bit)
access : read-write
CH4_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 4.
bits : 20 - 20 (1 bit)
access : read-write
CH5_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 5.
bits : 21 - 21 (1 bit)
access : read-write
CH6_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 6.
bits : 22 - 22 (1 bit)
access : read-write
CH7_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 7.
bits : 23 - 23 (1 bit)
access : read-write
CH8_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 8.
bits : 24 - 24 (1 bit)
access : read-write
CH9_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 9.
bits : 25 - 25 (1 bit)
access : read-write
CH10_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 10.
bits : 26 - 26 (1 bit)
access : read-write
CH11_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 11.
bits : 27 - 27 (1 bit)
access : read-write
CH12_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 12.
bits : 28 - 28 (1 bit)
access : read-write
CH13_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 13.
bits : 29 - 29 (1 bit)
access : read-write
CH14_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 14.
bits : 30 - 30 (1 bit)
access : read-write
CH15_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 15.
bits : 31 - 31 (1 bit)
access : read-write
AHB to APBH DMA Channel n Debug Information
address_offset : 0x1430 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHB_BYTES : This value reflects the current number of AHB bytes remaining to be transfered in the current transfer
bits : 0 - 15 (16 bit)
access : read-only
APB_BYTES : This value reflects the current number of APB bytes remaining to be transfered in the current transfer
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Current Command Address Register
address_offset : 0x1540 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to command structure currently being processed for channel n.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Next Command Address Register
address_offset : 0x15D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to next command structure for channel n.
bits : 0 - 31 (32 bit)
access : read-write
APBH DMA Channel n Command Register
address_offset : 0x1660 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMMAND : This bitfield indicates the type of current command:
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : NO_DMA_XFER
Perform any requested PIO word transfers but terminate command before any DMA transfer.
0x1 : DMA_WRITE
Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
0x2 : DMA_READ
Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
0x3 : DMA_SENSE
Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
End of enumeration elements list.
CHAIN : A value of one indicates that another command is chained onto the end of the current command structure
bits : 2 - 2 (1 bit)
access : read-only
IRQONCMPLT : A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i
bits : 3 - 3 (1 bit)
access : read-only
NANDLOCK : A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels
bits : 4 - 4 (1 bit)
access : read-only
NANDWAIT4READY : A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command
bits : 5 - 5 (1 bit)
access : read-only
SEMAPHORE : A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure
bits : 6 - 6 (1 bit)
access : read-only
WAIT4ENDCMD : A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command
bits : 7 - 7 (1 bit)
access : read-only
HALTONTERMINATE : A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set
bits : 8 - 8 (1 bit)
access : read-only
CMDWORDS : This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there
bits : 12 - 15 (4 bit)
access : read-only
XFER_COUNT : This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Buffer Address Register
address_offset : 0x16F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of system memory buffer to be read or written over the AHB bus.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Semaphore Register
address_offset : 0x1780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_SEMA : The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
PHORE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
AHB to APBH Bridge Control and Status Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 0
bits : 0 - 0 (1 bit)
access : read-write
CH1_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 1
bits : 1 - 1 (1 bit)
access : read-write
CH2_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 2
bits : 2 - 2 (1 bit)
access : read-write
CH3_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 3
bits : 3 - 3 (1 bit)
access : read-write
CH4_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 4
bits : 4 - 4 (1 bit)
access : read-write
CH5_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 5
bits : 5 - 5 (1 bit)
access : read-write
CH6_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 6
bits : 6 - 6 (1 bit)
access : read-write
CH7_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 7
bits : 7 - 7 (1 bit)
access : read-write
CH8_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 8
bits : 8 - 8 (1 bit)
access : read-write
CH9_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 9
bits : 9 - 9 (1 bit)
access : read-write
CH10_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 10
bits : 10 - 10 (1 bit)
access : read-write
CH11_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 11
bits : 11 - 11 (1 bit)
access : read-write
CH12_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 12
bits : 12 - 12 (1 bit)
access : read-write
CH13_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 13
bits : 13 - 13 (1 bit)
access : read-write
CH14_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 14
bits : 14 - 14 (1 bit)
access : read-write
CH15_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 15
bits : 15 - 15 (1 bit)
access : read-write
CH0_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 0.
bits : 16 - 16 (1 bit)
access : read-write
CH1_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 1.
bits : 17 - 17 (1 bit)
access : read-write
CH2_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 2.
bits : 18 - 18 (1 bit)
access : read-write
CH3_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 3.
bits : 19 - 19 (1 bit)
access : read-write
CH4_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 4.
bits : 20 - 20 (1 bit)
access : read-write
CH5_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 5.
bits : 21 - 21 (1 bit)
access : read-write
CH6_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 6.
bits : 22 - 22 (1 bit)
access : read-write
CH7_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 7.
bits : 23 - 23 (1 bit)
access : read-write
CH8_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 8.
bits : 24 - 24 (1 bit)
access : read-write
CH9_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 9.
bits : 25 - 25 (1 bit)
access : read-write
CH10_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 10.
bits : 26 - 26 (1 bit)
access : read-write
CH11_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 11.
bits : 27 - 27 (1 bit)
access : read-write
CH12_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 12.
bits : 28 - 28 (1 bit)
access : read-write
CH13_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 13.
bits : 29 - 29 (1 bit)
access : read-write
CH14_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 14.
bits : 30 - 30 (1 bit)
access : read-write
CH15_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 15.
bits : 31 - 31 (1 bit)
access : read-write
AHB to APBH DMA Channel n Debug Information
address_offset : 0x1810 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATEMACHINE : PIO Display of the DMA Channel n state machine state.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : IDLE
This is the idle state of the DMA state machine.
0x1 : REQ_CMD1
State in which the DMA is waiting to receive the first word of a command.
0x2 : REQ_CMD3
State in which the DMA is waiting to receive the third word of a command.
0x3 : REQ_CMD2
State in which the DMA is waiting to receive the second word of a command.
0x4 : XFER_DECODE
The state machine processes the descriptor command field in this state and branches accordingly.
0x5 : REQ_WAIT
The state machine waits in this state for the PIO APB cycles to complete.
0x6 : REQ_CMD4
State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
0x7 : PIO_REQ
This state determines whether another PIO cycle needs to occur before starting DMA transfers.
0x8 : READ_FLUSH
During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
0x9 : READ_WAIT
When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
0xC : WRITE
During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xD : READ_REQ
During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xE : CHECK_CHAIN
Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
0xF : XFER_COMPLETE
The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
0x14 : TERMINATE
When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
0x15 : WAIT_END
When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
0x1C : WRITE_WAIT
During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
0x1D : HALT_AFTER_TERM
If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
0x1E : CHECK_WAIT
If the Chain bit is a 0, the state machine enters this state and effectively halts.
0x1F : WAIT_READY
When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
End of enumeration elements list.
WR_FIFO_FULL : This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
bits : 20 - 20 (1 bit)
access : read-only
WR_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
bits : 21 - 21 (1 bit)
access : read-only
RD_FIFO_FULL : This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
bits : 22 - 22 (1 bit)
access : read-only
RD_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
bits : 23 - 23 (1 bit)
access : read-only
NEXTCMDADDRVALID : This bit reflects the internal bit which indicates whether the channel's next command address is valid
bits : 24 - 24 (1 bit)
access : read-only
READY : This bit is reserved for this DMA Channel and always reads 0.
bits : 26 - 26 (1 bit)
access : read-only
END : This bit reflects the current state of the DMA End Command Signal sent from the APB Device
bits : 28 - 28 (1 bit)
access : read-only
KICK : This bit reflects the current state of the DMA Kick Signal sent to the APB Device
bits : 29 - 29 (1 bit)
access : read-only
BURST : This bit reflects the current state of the DMA Burst Signal from the APB device
bits : 30 - 30 (1 bit)
access : read-only
REQ : This bit reflects the current state of the DMA Request Signal from the APB device
bits : 31 - 31 (1 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x18A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHB_BYTES : This value reflects the current number of AHB bytes remaining to be transfered in the current transfer
bits : 0 - 15 (16 bit)
access : read-only
APB_BYTES : This value reflects the current number of APB bytes remaining to be transfered in the current transfer
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Current Command Address Register
address_offset : 0x19C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to command structure currently being processed for channel n.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Next Command Address Register
address_offset : 0x1A60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to next command structure for channel n.
bits : 0 - 31 (32 bit)
access : read-write
APBH DMA Channel n Command Register
address_offset : 0x1B00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMMAND : This bitfield indicates the type of current command:
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : NO_DMA_XFER
Perform any requested PIO word transfers but terminate command before any DMA transfer.
0x1 : DMA_WRITE
Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
0x2 : DMA_READ
Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
0x3 : DMA_SENSE
Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
End of enumeration elements list.
CHAIN : A value of one indicates that another command is chained onto the end of the current command structure
bits : 2 - 2 (1 bit)
access : read-only
IRQONCMPLT : A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i
bits : 3 - 3 (1 bit)
access : read-only
NANDLOCK : A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels
bits : 4 - 4 (1 bit)
access : read-only
NANDWAIT4READY : A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command
bits : 5 - 5 (1 bit)
access : read-only
SEMAPHORE : A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure
bits : 6 - 6 (1 bit)
access : read-only
WAIT4ENDCMD : A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command
bits : 7 - 7 (1 bit)
access : read-only
HALTONTERMINATE : A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set
bits : 8 - 8 (1 bit)
access : read-only
CMDWORDS : This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there
bits : 12 - 15 (4 bit)
access : read-only
XFER_COUNT : This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Buffer Address Register
address_offset : 0x1BA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of system memory buffer to be read or written over the AHB bus.
bits : 0 - 31 (32 bit)
access : read-only
AHB to APBH Bridge Control and Status Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 0
bits : 0 - 0 (1 bit)
access : read-write
CH1_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 1
bits : 1 - 1 (1 bit)
access : read-write
CH2_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 2
bits : 2 - 2 (1 bit)
access : read-write
CH3_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 3
bits : 3 - 3 (1 bit)
access : read-write
CH4_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 4
bits : 4 - 4 (1 bit)
access : read-write
CH5_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 5
bits : 5 - 5 (1 bit)
access : read-write
CH6_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 6
bits : 6 - 6 (1 bit)
access : read-write
CH7_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA channel 7
bits : 7 - 7 (1 bit)
access : read-write
CH8_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 8
bits : 8 - 8 (1 bit)
access : read-write
CH9_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 9
bits : 9 - 9 (1 bit)
access : read-write
CH10_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 10
bits : 10 - 10 (1 bit)
access : read-write
CH11_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 11
bits : 11 - 11 (1 bit)
access : read-write
CH12_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 12
bits : 12 - 12 (1 bit)
access : read-write
CH13_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 13
bits : 13 - 13 (1 bit)
access : read-write
CH14_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 14
bits : 14 - 14 (1 bit)
access : read-write
CH15_CMDCMPLT_IRQ : Interrupt request status bit for APBH DMA Channel 15
bits : 15 - 15 (1 bit)
access : read-write
CH0_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 0.
bits : 16 - 16 (1 bit)
access : read-write
CH1_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 1.
bits : 17 - 17 (1 bit)
access : read-write
CH2_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 2.
bits : 18 - 18 (1 bit)
access : read-write
CH3_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 3.
bits : 19 - 19 (1 bit)
access : read-write
CH4_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 4.
bits : 20 - 20 (1 bit)
access : read-write
CH5_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 5.
bits : 21 - 21 (1 bit)
access : read-write
CH6_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 6.
bits : 22 - 22 (1 bit)
access : read-write
CH7_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 7.
bits : 23 - 23 (1 bit)
access : read-write
CH8_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 8.
bits : 24 - 24 (1 bit)
access : read-write
CH9_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 9.
bits : 25 - 25 (1 bit)
access : read-write
CH10_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 10.
bits : 26 - 26 (1 bit)
access : read-write
CH11_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 11.
bits : 27 - 27 (1 bit)
access : read-write
CH12_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 12.
bits : 28 - 28 (1 bit)
access : read-write
CH13_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 13.
bits : 29 - 29 (1 bit)
access : read-write
CH14_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 14.
bits : 30 - 30 (1 bit)
access : read-write
CH15_CMDCMPLT_IRQ_EN : Setting this bit enables the generation of an interrupt request for APBH DMA channel 15.
bits : 31 - 31 (1 bit)
access : read-write
APBH DMA Channel n Semaphore Register
address_offset : 0x1C40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_SEMA : The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
PHORE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x1CE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATEMACHINE : PIO Display of the DMA Channel n state machine state.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : IDLE
This is the idle state of the DMA state machine.
0x1 : REQ_CMD1
State in which the DMA is waiting to receive the first word of a command.
0x2 : REQ_CMD3
State in which the DMA is waiting to receive the third word of a command.
0x3 : REQ_CMD2
State in which the DMA is waiting to receive the second word of a command.
0x4 : XFER_DECODE
The state machine processes the descriptor command field in this state and branches accordingly.
0x5 : REQ_WAIT
The state machine waits in this state for the PIO APB cycles to complete.
0x6 : REQ_CMD4
State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
0x7 : PIO_REQ
This state determines whether another PIO cycle needs to occur before starting DMA transfers.
0x8 : READ_FLUSH
During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
0x9 : READ_WAIT
When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
0xC : WRITE
During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xD : READ_REQ
During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xE : CHECK_CHAIN
Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
0xF : XFER_COMPLETE
The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
0x14 : TERMINATE
When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
0x15 : WAIT_END
When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
0x1C : WRITE_WAIT
During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
0x1D : HALT_AFTER_TERM
If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
0x1E : CHECK_WAIT
If the Chain bit is a 0, the state machine enters this state and effectively halts.
0x1F : WAIT_READY
When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
End of enumeration elements list.
WR_FIFO_FULL : This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
bits : 20 - 20 (1 bit)
access : read-only
WR_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
bits : 21 - 21 (1 bit)
access : read-only
RD_FIFO_FULL : This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
bits : 22 - 22 (1 bit)
access : read-only
RD_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
bits : 23 - 23 (1 bit)
access : read-only
NEXTCMDADDRVALID : This bit reflects the internal bit which indicates whether the channel's next command address is valid
bits : 24 - 24 (1 bit)
access : read-only
READY : This bit is reserved for this DMA Channel and always reads 0.
bits : 26 - 26 (1 bit)
access : read-only
END : This bit reflects the current state of the DMA End Command Signal sent from the APB Device
bits : 28 - 28 (1 bit)
access : read-only
KICK : This bit reflects the current state of the DMA Kick Signal sent to the APB Device
bits : 29 - 29 (1 bit)
access : read-only
BURST : This bit reflects the current state of the DMA Burst Signal from the APB device
bits : 30 - 30 (1 bit)
access : read-only
REQ : This bit reflects the current state of the DMA Request Signal from the APB device
bits : 31 - 31 (1 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x1D80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHB_BYTES : This value reflects the current number of AHB bytes remaining to be transfered in the current transfer
bits : 0 - 15 (16 bit)
access : read-only
APB_BYTES : This value reflects the current number of APB bytes remaining to be transfered in the current transfer
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Current Command Address Register
address_offset : 0x1EB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to command structure currently being processed for channel n.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Next Command Address Register
address_offset : 0x1F60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to next command structure for channel n.
bits : 0 - 31 (32 bit)
access : read-write
AHB to APBH Bridge Control and Status Register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 0
bits : 0 - 0 (1 bit)
access : read-write
CH1_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 1
bits : 1 - 1 (1 bit)
access : read-write
CH2_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 2
bits : 2 - 2 (1 bit)
access : read-write
CH3_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 3
bits : 3 - 3 (1 bit)
access : read-write
CH4_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 4
bits : 4 - 4 (1 bit)
access : read-write
CH5_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 5
bits : 5 - 5 (1 bit)
access : read-write
CH6_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 6
bits : 6 - 6 (1 bit)
access : read-write
CH7_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 7
bits : 7 - 7 (1 bit)
access : read-write
CH8_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 8
bits : 8 - 8 (1 bit)
access : read-write
CH9_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 9
bits : 9 - 9 (1 bit)
access : read-write
CH10_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 10
bits : 10 - 10 (1 bit)
access : read-write
CH11_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 11
bits : 11 - 11 (1 bit)
access : read-write
CH12_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 12
bits : 12 - 12 (1 bit)
access : read-write
CH13_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 13
bits : 13 - 13 (1 bit)
access : read-write
CH14_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 14
bits : 14 - 14 (1 bit)
access : read-write
CH15_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 15
bits : 15 - 15 (1 bit)
access : read-write
CH0_ERROR_STATUS : Error status bit for APBX DMA Channel 0
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH1_ERROR_STATUS : Error status bit for APBX DMA Channel 1
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH2_ERROR_STATUS : Error status bit for APBX DMA Channel 2
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH3_ERROR_STATUS : Error status bit for APBX DMA Channel 3
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH4_ERROR_STATUS : Error status bit for APBX DMA Channel 4
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH5_ERROR_STATUS : Error status bit for APBX DMA Channel 5
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH6_ERROR_STATUS : Error status bit for APBX DMA Channel 6
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH7_ERROR_STATUS : Error status bit for APBX DMA Channel 7
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH8_ERROR_STATUS : Error status bit for APBH DMA Channel 8
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH9_ERROR_STATUS : Error status bit for APBH DMA Channel 9
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH10_ERROR_STATUS : Error status bit for APBH DMA Channel 10
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH11_ERROR_STATUS : Error status bit for APBH DMA Channel 11
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH12_ERROR_STATUS : Error status bit for APBH DMA Channel 12
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH13_ERROR_STATUS : Error status bit for APBH DMA Channel 13
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH14_ERROR_STATUS : Error status bit for APBH DMA Channel 14
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH15_ERROR_STATUS : Error status bit for APBH DMA Channel 15
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
APBH DMA Channel n Current Command Address Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to command structure currently being processed for channel n.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Command Register
address_offset : 0x2010 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMMAND : This bitfield indicates the type of current command:
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : NO_DMA_XFER
Perform any requested PIO word transfers but terminate command before any DMA transfer.
0x1 : DMA_WRITE
Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
0x2 : DMA_READ
Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
0x3 : DMA_SENSE
Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
End of enumeration elements list.
CHAIN : A value of one indicates that another command is chained onto the end of the current command structure
bits : 2 - 2 (1 bit)
access : read-only
IRQONCMPLT : A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i
bits : 3 - 3 (1 bit)
access : read-only
NANDLOCK : A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels
bits : 4 - 4 (1 bit)
access : read-only
NANDWAIT4READY : A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command
bits : 5 - 5 (1 bit)
access : read-only
SEMAPHORE : A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure
bits : 6 - 6 (1 bit)
access : read-only
WAIT4ENDCMD : A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command
bits : 7 - 7 (1 bit)
access : read-only
HALTONTERMINATE : A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set
bits : 8 - 8 (1 bit)
access : read-only
CMDWORDS : This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there
bits : 12 - 15 (4 bit)
access : read-only
XFER_COUNT : This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Buffer Address Register
address_offset : 0x20C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of system memory buffer to be read or written over the AHB bus.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Semaphore Register
address_offset : 0x2170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_SEMA : The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
PHORE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
APBH DMA Channel n Next Command Address Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to next command structure for channel n.
bits : 0 - 31 (32 bit)
access : read-write
AHB to APBH DMA Channel n Debug Information
address_offset : 0x2220 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATEMACHINE : PIO Display of the DMA Channel n state machine state.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : IDLE
This is the idle state of the DMA state machine.
0x1 : REQ_CMD1
State in which the DMA is waiting to receive the first word of a command.
0x2 : REQ_CMD3
State in which the DMA is waiting to receive the third word of a command.
0x3 : REQ_CMD2
State in which the DMA is waiting to receive the second word of a command.
0x4 : XFER_DECODE
The state machine processes the descriptor command field in this state and branches accordingly.
0x5 : REQ_WAIT
The state machine waits in this state for the PIO APB cycles to complete.
0x6 : REQ_CMD4
State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
0x7 : PIO_REQ
This state determines whether another PIO cycle needs to occur before starting DMA transfers.
0x8 : READ_FLUSH
During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
0x9 : READ_WAIT
When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
0xC : WRITE
During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xD : READ_REQ
During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xE : CHECK_CHAIN
Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
0xF : XFER_COMPLETE
The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
0x14 : TERMINATE
When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
0x15 : WAIT_END
When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
0x1C : WRITE_WAIT
During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
0x1D : HALT_AFTER_TERM
If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
0x1E : CHECK_WAIT
If the Chain bit is a 0, the state machine enters this state and effectively halts.
0x1F : WAIT_READY
When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
End of enumeration elements list.
WR_FIFO_FULL : This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
bits : 20 - 20 (1 bit)
access : read-only
WR_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
bits : 21 - 21 (1 bit)
access : read-only
RD_FIFO_FULL : This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
bits : 22 - 22 (1 bit)
access : read-only
RD_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
bits : 23 - 23 (1 bit)
access : read-only
NEXTCMDADDRVALID : This bit reflects the internal bit which indicates whether the channel's next command address is valid
bits : 24 - 24 (1 bit)
access : read-only
READY : This bit is reserved for this DMA Channel and always reads 0.
bits : 26 - 26 (1 bit)
access : read-only
END : This bit reflects the current state of the DMA End Command Signal sent from the APB Device
bits : 28 - 28 (1 bit)
access : read-only
KICK : This bit reflects the current state of the DMA Kick Signal sent to the APB Device
bits : 29 - 29 (1 bit)
access : read-only
BURST : This bit reflects the current state of the DMA Burst Signal from the APB device
bits : 30 - 30 (1 bit)
access : read-only
REQ : This bit reflects the current state of the DMA Request Signal from the APB device
bits : 31 - 31 (1 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x22D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHB_BYTES : This value reflects the current number of AHB bytes remaining to be transfered in the current transfer
bits : 0 - 15 (16 bit)
access : read-only
APB_BYTES : This value reflects the current number of APB bytes remaining to be transfered in the current transfer
bits : 16 - 31 (16 bit)
access : read-only
AHB to APBH Bridge Control and Status Register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 0
bits : 0 - 0 (1 bit)
access : read-write
CH1_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 1
bits : 1 - 1 (1 bit)
access : read-write
CH2_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 2
bits : 2 - 2 (1 bit)
access : read-write
CH3_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 3
bits : 3 - 3 (1 bit)
access : read-write
CH4_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 4
bits : 4 - 4 (1 bit)
access : read-write
CH5_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 5
bits : 5 - 5 (1 bit)
access : read-write
CH6_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 6
bits : 6 - 6 (1 bit)
access : read-write
CH7_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 7
bits : 7 - 7 (1 bit)
access : read-write
CH8_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 8
bits : 8 - 8 (1 bit)
access : read-write
CH9_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 9
bits : 9 - 9 (1 bit)
access : read-write
CH10_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 10
bits : 10 - 10 (1 bit)
access : read-write
CH11_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 11
bits : 11 - 11 (1 bit)
access : read-write
CH12_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 12
bits : 12 - 12 (1 bit)
access : read-write
CH13_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 13
bits : 13 - 13 (1 bit)
access : read-write
CH14_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 14
bits : 14 - 14 (1 bit)
access : read-write
CH15_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 15
bits : 15 - 15 (1 bit)
access : read-write
CH0_ERROR_STATUS : Error status bit for APBX DMA Channel 0
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH1_ERROR_STATUS : Error status bit for APBX DMA Channel 1
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH2_ERROR_STATUS : Error status bit for APBX DMA Channel 2
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH3_ERROR_STATUS : Error status bit for APBX DMA Channel 3
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH4_ERROR_STATUS : Error status bit for APBX DMA Channel 4
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH5_ERROR_STATUS : Error status bit for APBX DMA Channel 5
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH6_ERROR_STATUS : Error status bit for APBX DMA Channel 6
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH7_ERROR_STATUS : Error status bit for APBX DMA Channel 7
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH8_ERROR_STATUS : Error status bit for APBH DMA Channel 8
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH9_ERROR_STATUS : Error status bit for APBH DMA Channel 9
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH10_ERROR_STATUS : Error status bit for APBH DMA Channel 10
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH11_ERROR_STATUS : Error status bit for APBH DMA Channel 11
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH12_ERROR_STATUS : Error status bit for APBH DMA Channel 12
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH13_ERROR_STATUS : Error status bit for APBH DMA Channel 13
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH14_ERROR_STATUS : Error status bit for APBH DMA Channel 14
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH15_ERROR_STATUS : Error status bit for APBH DMA Channel 15
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
APBH DMA Channel n Command Register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMMAND : This bitfield indicates the type of current command:
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : NO_DMA_XFER
Perform any requested PIO word transfers but terminate command before any DMA transfer.
0x1 : DMA_WRITE
Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
0x2 : DMA_READ
Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
0x3 : DMA_SENSE
Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
End of enumeration elements list.
CHAIN : A value of one indicates that another command is chained onto the end of the current command structure
bits : 2 - 2 (1 bit)
access : read-only
IRQONCMPLT : A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i
bits : 3 - 3 (1 bit)
access : read-only
NANDLOCK : A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels
bits : 4 - 4 (1 bit)
access : read-only
NANDWAIT4READY : A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command
bits : 5 - 5 (1 bit)
access : read-only
SEMAPHORE : A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure
bits : 6 - 6 (1 bit)
access : read-only
WAIT4ENDCMD : A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command
bits : 7 - 7 (1 bit)
access : read-only
HALTONTERMINATE : A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set
bits : 8 - 8 (1 bit)
access : read-only
CMDWORDS : This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there
bits : 12 - 15 (4 bit)
access : read-only
XFER_COUNT : This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Current Command Address Register
address_offset : 0x2410 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to command structure currently being processed for channel n.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Next Command Address Register
address_offset : 0x24D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to next command structure for channel n.
bits : 0 - 31 (32 bit)
access : read-write
APBH DMA Channel n Command Register
address_offset : 0x2590 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMMAND : This bitfield indicates the type of current command:
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : NO_DMA_XFER
Perform any requested PIO word transfers but terminate command before any DMA transfer.
0x1 : DMA_WRITE
Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
0x2 : DMA_READ
Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
0x3 : DMA_SENSE
Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
End of enumeration elements list.
CHAIN : A value of one indicates that another command is chained onto the end of the current command structure
bits : 2 - 2 (1 bit)
access : read-only
IRQONCMPLT : A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i
bits : 3 - 3 (1 bit)
access : read-only
NANDLOCK : A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels
bits : 4 - 4 (1 bit)
access : read-only
NANDWAIT4READY : A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command
bits : 5 - 5 (1 bit)
access : read-only
SEMAPHORE : A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure
bits : 6 - 6 (1 bit)
access : read-only
WAIT4ENDCMD : A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command
bits : 7 - 7 (1 bit)
access : read-only
HALTONTERMINATE : A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set
bits : 8 - 8 (1 bit)
access : read-only
CMDWORDS : This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there
bits : 12 - 15 (4 bit)
access : read-only
XFER_COUNT : This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Buffer Address Register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of system memory buffer to be read or written over the AHB bus.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Buffer Address Register
address_offset : 0x2650 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of system memory buffer to be read or written over the AHB bus.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Semaphore Register
address_offset : 0x2710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_SEMA : The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
PHORE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x27D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATEMACHINE : PIO Display of the DMA Channel n state machine state.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : IDLE
This is the idle state of the DMA state machine.
0x1 : REQ_CMD1
State in which the DMA is waiting to receive the first word of a command.
0x2 : REQ_CMD3
State in which the DMA is waiting to receive the third word of a command.
0x3 : REQ_CMD2
State in which the DMA is waiting to receive the second word of a command.
0x4 : XFER_DECODE
The state machine processes the descriptor command field in this state and branches accordingly.
0x5 : REQ_WAIT
The state machine waits in this state for the PIO APB cycles to complete.
0x6 : REQ_CMD4
State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
0x7 : PIO_REQ
This state determines whether another PIO cycle needs to occur before starting DMA transfers.
0x8 : READ_FLUSH
During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
0x9 : READ_WAIT
When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
0xC : WRITE
During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xD : READ_REQ
During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xE : CHECK_CHAIN
Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
0xF : XFER_COMPLETE
The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
0x14 : TERMINATE
When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
0x15 : WAIT_END
When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
0x1C : WRITE_WAIT
During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
0x1D : HALT_AFTER_TERM
If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
0x1E : CHECK_WAIT
If the Chain bit is a 0, the state machine enters this state and effectively halts.
0x1F : WAIT_READY
When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
End of enumeration elements list.
WR_FIFO_FULL : This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
bits : 20 - 20 (1 bit)
access : read-only
WR_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
bits : 21 - 21 (1 bit)
access : read-only
RD_FIFO_FULL : This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
bits : 22 - 22 (1 bit)
access : read-only
RD_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
bits : 23 - 23 (1 bit)
access : read-only
NEXTCMDADDRVALID : This bit reflects the internal bit which indicates whether the channel's next command address is valid
bits : 24 - 24 (1 bit)
access : read-only
READY : This bit is reserved for this DMA Channel and always reads 0.
bits : 26 - 26 (1 bit)
access : read-only
END : This bit reflects the current state of the DMA End Command Signal sent from the APB Device
bits : 28 - 28 (1 bit)
access : read-only
KICK : This bit reflects the current state of the DMA Kick Signal sent to the APB Device
bits : 29 - 29 (1 bit)
access : read-only
BURST : This bit reflects the current state of the DMA Burst Signal from the APB device
bits : 30 - 30 (1 bit)
access : read-only
REQ : This bit reflects the current state of the DMA Request Signal from the APB device
bits : 31 - 31 (1 bit)
access : read-only
AHB to APBH Bridge Control and Status Register 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 0
bits : 0 - 0 (1 bit)
access : read-write
CH1_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 1
bits : 1 - 1 (1 bit)
access : read-write
CH2_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 2
bits : 2 - 2 (1 bit)
access : read-write
CH3_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 3
bits : 3 - 3 (1 bit)
access : read-write
CH4_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 4
bits : 4 - 4 (1 bit)
access : read-write
CH5_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 5
bits : 5 - 5 (1 bit)
access : read-write
CH6_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 6
bits : 6 - 6 (1 bit)
access : read-write
CH7_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 7
bits : 7 - 7 (1 bit)
access : read-write
CH8_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 8
bits : 8 - 8 (1 bit)
access : read-write
CH9_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 9
bits : 9 - 9 (1 bit)
access : read-write
CH10_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 10
bits : 10 - 10 (1 bit)
access : read-write
CH11_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 11
bits : 11 - 11 (1 bit)
access : read-write
CH12_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 12
bits : 12 - 12 (1 bit)
access : read-write
CH13_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 13
bits : 13 - 13 (1 bit)
access : read-write
CH14_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 14
bits : 14 - 14 (1 bit)
access : read-write
CH15_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 15
bits : 15 - 15 (1 bit)
access : read-write
CH0_ERROR_STATUS : Error status bit for APBX DMA Channel 0
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH1_ERROR_STATUS : Error status bit for APBX DMA Channel 1
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH2_ERROR_STATUS : Error status bit for APBX DMA Channel 2
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH3_ERROR_STATUS : Error status bit for APBX DMA Channel 3
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH4_ERROR_STATUS : Error status bit for APBX DMA Channel 4
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH5_ERROR_STATUS : Error status bit for APBX DMA Channel 5
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH6_ERROR_STATUS : Error status bit for APBX DMA Channel 6
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH7_ERROR_STATUS : Error status bit for APBX DMA Channel 7
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH8_ERROR_STATUS : Error status bit for APBH DMA Channel 8
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH9_ERROR_STATUS : Error status bit for APBH DMA Channel 9
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH10_ERROR_STATUS : Error status bit for APBH DMA Channel 10
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH11_ERROR_STATUS : Error status bit for APBH DMA Channel 11
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH12_ERROR_STATUS : Error status bit for APBH DMA Channel 12
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH13_ERROR_STATUS : Error status bit for APBH DMA Channel 13
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH14_ERROR_STATUS : Error status bit for APBH DMA Channel 14
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH15_ERROR_STATUS : Error status bit for APBH DMA Channel 15
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
APBH DMA Channel n Semaphore Register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_SEMA : The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
PHORE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x2890 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHB_BYTES : This value reflects the current number of AHB bytes remaining to be transfered in the current transfer
bits : 0 - 15 (16 bit)
access : read-only
APB_BYTES : This value reflects the current number of APB bytes remaining to be transfered in the current transfer
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Current Command Address Register
address_offset : 0x29E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to command structure currently being processed for channel n.
bits : 0 - 31 (32 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATEMACHINE : PIO Display of the DMA Channel n state machine state.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : IDLE
This is the idle state of the DMA state machine.
0x1 : REQ_CMD1
State in which the DMA is waiting to receive the first word of a command.
0x2 : REQ_CMD3
State in which the DMA is waiting to receive the third word of a command.
0x3 : REQ_CMD2
State in which the DMA is waiting to receive the second word of a command.
0x4 : XFER_DECODE
The state machine processes the descriptor command field in this state and branches accordingly.
0x5 : REQ_WAIT
The state machine waits in this state for the PIO APB cycles to complete.
0x6 : REQ_CMD4
State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
0x7 : PIO_REQ
This state determines whether another PIO cycle needs to occur before starting DMA transfers.
0x8 : READ_FLUSH
During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
0x9 : READ_WAIT
When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
0xC : WRITE
During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xD : READ_REQ
During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xE : CHECK_CHAIN
Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
0xF : XFER_COMPLETE
The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
0x14 : TERMINATE
When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
0x15 : WAIT_END
When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
0x1C : WRITE_WAIT
During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
0x1D : HALT_AFTER_TERM
If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
0x1E : CHECK_WAIT
If the Chain bit is a 0, the state machine enters this state and effectively halts.
0x1F : WAIT_READY
When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
End of enumeration elements list.
WR_FIFO_FULL : This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
bits : 20 - 20 (1 bit)
access : read-only
WR_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
bits : 21 - 21 (1 bit)
access : read-only
RD_FIFO_FULL : This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
bits : 22 - 22 (1 bit)
access : read-only
RD_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
bits : 23 - 23 (1 bit)
access : read-only
NEXTCMDADDRVALID : This bit reflects the internal bit which indicates whether the channel's next command address is valid
bits : 24 - 24 (1 bit)
access : read-only
READY : This bit is reserved for this DMA Channel and always reads 0.
bits : 26 - 26 (1 bit)
access : read-only
END : This bit reflects the current state of the DMA End Command Signal sent from the APB Device
bits : 28 - 28 (1 bit)
access : read-only
KICK : This bit reflects the current state of the DMA Kick Signal sent to the APB Device
bits : 29 - 29 (1 bit)
access : read-only
BURST : This bit reflects the current state of the DMA Burst Signal from the APB device
bits : 30 - 30 (1 bit)
access : read-only
REQ : This bit reflects the current state of the DMA Request Signal from the APB device
bits : 31 - 31 (1 bit)
access : read-only
APBH DMA Channel n Next Command Address Register
address_offset : 0x2AB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to next command structure for channel n.
bits : 0 - 31 (32 bit)
access : read-write
APBH DMA Channel n Command Register
address_offset : 0x2B80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMMAND : This bitfield indicates the type of current command:
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : NO_DMA_XFER
Perform any requested PIO word transfers but terminate command before any DMA transfer.
0x1 : DMA_WRITE
Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
0x2 : DMA_READ
Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
0x3 : DMA_SENSE
Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
End of enumeration elements list.
CHAIN : A value of one indicates that another command is chained onto the end of the current command structure
bits : 2 - 2 (1 bit)
access : read-only
IRQONCMPLT : A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i
bits : 3 - 3 (1 bit)
access : read-only
NANDLOCK : A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels
bits : 4 - 4 (1 bit)
access : read-only
NANDWAIT4READY : A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command
bits : 5 - 5 (1 bit)
access : read-only
SEMAPHORE : A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure
bits : 6 - 6 (1 bit)
access : read-only
WAIT4ENDCMD : A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command
bits : 7 - 7 (1 bit)
access : read-only
HALTONTERMINATE : A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set
bits : 8 - 8 (1 bit)
access : read-only
CMDWORDS : This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there
bits : 12 - 15 (4 bit)
access : read-only
XFER_COUNT : This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device
bits : 16 - 31 (16 bit)
access : read-only
AHB to APBH Bridge Control and Status Register 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 0
bits : 0 - 0 (1 bit)
access : read-write
CH1_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 1
bits : 1 - 1 (1 bit)
access : read-write
CH2_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 2
bits : 2 - 2 (1 bit)
access : read-write
CH3_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 3
bits : 3 - 3 (1 bit)
access : read-write
CH4_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 4
bits : 4 - 4 (1 bit)
access : read-write
CH5_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 5
bits : 5 - 5 (1 bit)
access : read-write
CH6_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 6
bits : 6 - 6 (1 bit)
access : read-write
CH7_ERROR_IRQ : Error interrupt status bit for APBX DMA Channel 7
bits : 7 - 7 (1 bit)
access : read-write
CH8_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 8
bits : 8 - 8 (1 bit)
access : read-write
CH9_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 9
bits : 9 - 9 (1 bit)
access : read-write
CH10_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 10
bits : 10 - 10 (1 bit)
access : read-write
CH11_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 11
bits : 11 - 11 (1 bit)
access : read-write
CH12_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 12
bits : 12 - 12 (1 bit)
access : read-write
CH13_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 13
bits : 13 - 13 (1 bit)
access : read-write
CH14_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 14
bits : 14 - 14 (1 bit)
access : read-write
CH15_ERROR_IRQ : Error interrupt status bit for APBH DMA Channel 15
bits : 15 - 15 (1 bit)
access : read-write
CH0_ERROR_STATUS : Error status bit for APBX DMA Channel 0
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH1_ERROR_STATUS : Error status bit for APBX DMA Channel 1
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH2_ERROR_STATUS : Error status bit for APBX DMA Channel 2
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH3_ERROR_STATUS : Error status bit for APBX DMA Channel 3
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH4_ERROR_STATUS : Error status bit for APBX DMA Channel 4
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH5_ERROR_STATUS : Error status bit for APBX DMA Channel 5
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH6_ERROR_STATUS : Error status bit for APBX DMA Channel 6
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH7_ERROR_STATUS : Error status bit for APBX DMA Channel 7
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH8_ERROR_STATUS : Error status bit for APBH DMA Channel 8
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH9_ERROR_STATUS : Error status bit for APBH DMA Channel 9
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH10_ERROR_STATUS : Error status bit for APBH DMA Channel 10
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH11_ERROR_STATUS : Error status bit for APBH DMA Channel 11
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH12_ERROR_STATUS : Error status bit for APBH DMA Channel 12
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH13_ERROR_STATUS : Error status bit for APBH DMA Channel 13
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH14_ERROR_STATUS : Error status bit for APBH DMA Channel 14
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
CH15_ERROR_STATUS : Error status bit for APBH DMA Channel 15
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : TERMINATION
An early termination from the device causes error IRQ.
0x1 : BUS_ERROR
An AHB bus error causes error IRQ.
End of enumeration elements list.
AHB to APBH DMA Channel n Debug Information
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHB_BYTES : This value reflects the current number of AHB bytes remaining to be transfered in the current transfer
bits : 0 - 15 (16 bit)
access : read-only
APB_BYTES : This value reflects the current number of APB bytes remaining to be transfered in the current transfer
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Buffer Address Register
address_offset : 0x2C50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of system memory buffer to be read or written over the AHB bus.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Semaphore Register
address_offset : 0x2D20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_SEMA : The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
PHORE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x2DF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATEMACHINE : PIO Display of the DMA Channel n state machine state.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : IDLE
This is the idle state of the DMA state machine.
0x1 : REQ_CMD1
State in which the DMA is waiting to receive the first word of a command.
0x2 : REQ_CMD3
State in which the DMA is waiting to receive the third word of a command.
0x3 : REQ_CMD2
State in which the DMA is waiting to receive the second word of a command.
0x4 : XFER_DECODE
The state machine processes the descriptor command field in this state and branches accordingly.
0x5 : REQ_WAIT
The state machine waits in this state for the PIO APB cycles to complete.
0x6 : REQ_CMD4
State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
0x7 : PIO_REQ
This state determines whether another PIO cycle needs to occur before starting DMA transfers.
0x8 : READ_FLUSH
During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
0x9 : READ_WAIT
When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
0xC : WRITE
During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xD : READ_REQ
During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xE : CHECK_CHAIN
Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
0xF : XFER_COMPLETE
The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
0x14 : TERMINATE
When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
0x15 : WAIT_END
When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
0x1C : WRITE_WAIT
During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
0x1D : HALT_AFTER_TERM
If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
0x1E : CHECK_WAIT
If the Chain bit is a 0, the state machine enters this state and effectively halts.
0x1F : WAIT_READY
When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
End of enumeration elements list.
WR_FIFO_FULL : This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
bits : 20 - 20 (1 bit)
access : read-only
WR_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
bits : 21 - 21 (1 bit)
access : read-only
RD_FIFO_FULL : This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
bits : 22 - 22 (1 bit)
access : read-only
RD_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
bits : 23 - 23 (1 bit)
access : read-only
NEXTCMDADDRVALID : This bit reflects the internal bit which indicates whether the channel's next command address is valid
bits : 24 - 24 (1 bit)
access : read-only
READY : This bit is reserved for this DMA Channel and always reads 0.
bits : 26 - 26 (1 bit)
access : read-only
END : This bit reflects the current state of the DMA End Command Signal sent from the APB Device
bits : 28 - 28 (1 bit)
access : read-only
KICK : This bit reflects the current state of the DMA Kick Signal sent to the APB Device
bits : 29 - 29 (1 bit)
access : read-only
BURST : This bit reflects the current state of the DMA Burst Signal from the APB device
bits : 30 - 30 (1 bit)
access : read-only
REQ : This bit reflects the current state of the DMA Request Signal from the APB device
bits : 31 - 31 (1 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x2EC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHB_BYTES : This value reflects the current number of AHB bytes remaining to be transfered in the current transfer
bits : 0 - 15 (16 bit)
access : read-only
APB_BYTES : This value reflects the current number of APB bytes remaining to be transfered in the current transfer
bits : 16 - 31 (16 bit)
access : read-only
AHB to APBH Bridge Channel Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREEZE_CHANNEL : Setting a bit in this field will freeze the DMA channel associated with it
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0x1 : NAND0
NAND0
0x2 : NAND1
NAND1
0x4 : NAND2
NAND2
0x8 : NAND3
NAND3
0x10 : NAND4
NAND4
0x20 : NAND5
NAND5
0x40 : NAND6
NAND6
0x80 : NAND7
NAND7
0x100 : SSP
SSP
End of enumeration elements list.
RESET_CHANNEL : Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0x1 : NAND0
NAND0
0x2 : NAND1
NAND1
0x4 : NAND2
NAND2
0x8 : NAND3
NAND3
0x10 : NAND4
NAND4
0x20 : NAND5
NAND5
0x40 : NAND6
NAND6
0x80 : NAND7
NAND7
0x100 : SSP
SSP
End of enumeration elements list.
APBH DMA Channel n Current Command Address Register
address_offset : 0x3020 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to command structure currently being processed for channel n.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Next Command Address Register
address_offset : 0x3100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to next command structure for channel n.
bits : 0 - 31 (32 bit)
access : read-write
APBH DMA Channel n Command Register
address_offset : 0x31E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMMAND : This bitfield indicates the type of current command:
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : NO_DMA_XFER
Perform any requested PIO word transfers but terminate command before any DMA transfer.
0x1 : DMA_WRITE
Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
0x2 : DMA_READ
Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
0x3 : DMA_SENSE
Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
End of enumeration elements list.
CHAIN : A value of one indicates that another command is chained onto the end of the current command structure
bits : 2 - 2 (1 bit)
access : read-only
IRQONCMPLT : A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i
bits : 3 - 3 (1 bit)
access : read-only
NANDLOCK : A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels
bits : 4 - 4 (1 bit)
access : read-only
NANDWAIT4READY : A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command
bits : 5 - 5 (1 bit)
access : read-only
SEMAPHORE : A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure
bits : 6 - 6 (1 bit)
access : read-only
WAIT4ENDCMD : A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command
bits : 7 - 7 (1 bit)
access : read-only
HALTONTERMINATE : A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set
bits : 8 - 8 (1 bit)
access : read-only
CMDWORDS : This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there
bits : 12 - 15 (4 bit)
access : read-only
XFER_COUNT : This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Buffer Address Register
address_offset : 0x32C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of system memory buffer to be read or written over the AHB bus.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Semaphore Register
address_offset : 0x33A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_SEMA : The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
PHORE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
AHB to APBH Bridge Channel Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREEZE_CHANNEL : Setting a bit in this field will freeze the DMA channel associated with it
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0x1 : NAND0
NAND0
0x2 : NAND1
NAND1
0x4 : NAND2
NAND2
0x8 : NAND3
NAND3
0x10 : NAND4
NAND4
0x20 : NAND5
NAND5
0x40 : NAND6
NAND6
0x80 : NAND7
NAND7
0x100 : SSP
SSP
End of enumeration elements list.
RESET_CHANNEL : Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0x1 : NAND0
NAND0
0x2 : NAND1
NAND1
0x4 : NAND2
NAND2
0x8 : NAND3
NAND3
0x10 : NAND4
NAND4
0x20 : NAND5
NAND5
0x40 : NAND6
NAND6
0x80 : NAND7
NAND7
0x100 : SSP
SSP
End of enumeration elements list.
AHB to APBH DMA Channel n Debug Information
address_offset : 0x3480 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATEMACHINE : PIO Display of the DMA Channel n state machine state.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : IDLE
This is the idle state of the DMA state machine.
0x1 : REQ_CMD1
State in which the DMA is waiting to receive the first word of a command.
0x2 : REQ_CMD3
State in which the DMA is waiting to receive the third word of a command.
0x3 : REQ_CMD2
State in which the DMA is waiting to receive the second word of a command.
0x4 : XFER_DECODE
The state machine processes the descriptor command field in this state and branches accordingly.
0x5 : REQ_WAIT
The state machine waits in this state for the PIO APB cycles to complete.
0x6 : REQ_CMD4
State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
0x7 : PIO_REQ
This state determines whether another PIO cycle needs to occur before starting DMA transfers.
0x8 : READ_FLUSH
During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
0x9 : READ_WAIT
When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
0xC : WRITE
During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xD : READ_REQ
During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xE : CHECK_CHAIN
Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
0xF : XFER_COMPLETE
The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
0x14 : TERMINATE
When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
0x15 : WAIT_END
When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
0x1C : WRITE_WAIT
During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
0x1D : HALT_AFTER_TERM
If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
0x1E : CHECK_WAIT
If the Chain bit is a 0, the state machine enters this state and effectively halts.
0x1F : WAIT_READY
When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
End of enumeration elements list.
WR_FIFO_FULL : This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
bits : 20 - 20 (1 bit)
access : read-only
WR_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
bits : 21 - 21 (1 bit)
access : read-only
RD_FIFO_FULL : This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
bits : 22 - 22 (1 bit)
access : read-only
RD_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
bits : 23 - 23 (1 bit)
access : read-only
NEXTCMDADDRVALID : This bit reflects the internal bit which indicates whether the channel's next command address is valid
bits : 24 - 24 (1 bit)
access : read-only
READY : This bit is reserved for this DMA Channel and always reads 0.
bits : 26 - 26 (1 bit)
access : read-only
END : This bit reflects the current state of the DMA End Command Signal sent from the APB Device
bits : 28 - 28 (1 bit)
access : read-only
KICK : This bit reflects the current state of the DMA Kick Signal sent to the APB Device
bits : 29 - 29 (1 bit)
access : read-only
BURST : This bit reflects the current state of the DMA Burst Signal from the APB device
bits : 30 - 30 (1 bit)
access : read-only
REQ : This bit reflects the current state of the DMA Request Signal from the APB device
bits : 31 - 31 (1 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x3560 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHB_BYTES : This value reflects the current number of AHB bytes remaining to be transfered in the current transfer
bits : 0 - 15 (16 bit)
access : read-only
APB_BYTES : This value reflects the current number of APB bytes remaining to be transfered in the current transfer
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Current Command Address Register
address_offset : 0x36D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to command structure currently being processed for channel n.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Current Command Address Register
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to command structure currently being processed for channel n.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Next Command Address Register
address_offset : 0x37C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to next command structure for channel n.
bits : 0 - 31 (32 bit)
access : read-write
AHB to APBH Bridge Channel Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREEZE_CHANNEL : Setting a bit in this field will freeze the DMA channel associated with it
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0x1 : NAND0
NAND0
0x2 : NAND1
NAND1
0x4 : NAND2
NAND2
0x8 : NAND3
NAND3
0x10 : NAND4
NAND4
0x20 : NAND5
NAND5
0x40 : NAND6
NAND6
0x80 : NAND7
NAND7
0x100 : SSP
SSP
End of enumeration elements list.
RESET_CHANNEL : Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0x1 : NAND0
NAND0
0x2 : NAND1
NAND1
0x4 : NAND2
NAND2
0x8 : NAND3
NAND3
0x10 : NAND4
NAND4
0x20 : NAND5
NAND5
0x40 : NAND6
NAND6
0x80 : NAND7
NAND7
0x100 : SSP
SSP
End of enumeration elements list.
APBH DMA Channel n Command Register
address_offset : 0x38B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMMAND : This bitfield indicates the type of current command:
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : NO_DMA_XFER
Perform any requested PIO word transfers but terminate command before any DMA transfer.
0x1 : DMA_WRITE
Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
0x2 : DMA_READ
Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
0x3 : DMA_SENSE
Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
End of enumeration elements list.
CHAIN : A value of one indicates that another command is chained onto the end of the current command structure
bits : 2 - 2 (1 bit)
access : read-only
IRQONCMPLT : A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i
bits : 3 - 3 (1 bit)
access : read-only
NANDLOCK : A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels
bits : 4 - 4 (1 bit)
access : read-only
NANDWAIT4READY : A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command
bits : 5 - 5 (1 bit)
access : read-only
SEMAPHORE : A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure
bits : 6 - 6 (1 bit)
access : read-only
WAIT4ENDCMD : A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command
bits : 7 - 7 (1 bit)
access : read-only
HALTONTERMINATE : A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set
bits : 8 - 8 (1 bit)
access : read-only
CMDWORDS : This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there
bits : 12 - 15 (4 bit)
access : read-only
XFER_COUNT : This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Buffer Address Register
address_offset : 0x39A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of system memory buffer to be read or written over the AHB bus.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Next Command Address Register
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to next command structure for channel n.
bits : 0 - 31 (32 bit)
access : read-write
APBH DMA Channel n Semaphore Register
address_offset : 0x3A90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_SEMA : The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
PHORE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x3B80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATEMACHINE : PIO Display of the DMA Channel n state machine state.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : IDLE
This is the idle state of the DMA state machine.
0x1 : REQ_CMD1
State in which the DMA is waiting to receive the first word of a command.
0x2 : REQ_CMD3
State in which the DMA is waiting to receive the third word of a command.
0x3 : REQ_CMD2
State in which the DMA is waiting to receive the second word of a command.
0x4 : XFER_DECODE
The state machine processes the descriptor command field in this state and branches accordingly.
0x5 : REQ_WAIT
The state machine waits in this state for the PIO APB cycles to complete.
0x6 : REQ_CMD4
State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
0x7 : PIO_REQ
This state determines whether another PIO cycle needs to occur before starting DMA transfers.
0x8 : READ_FLUSH
During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
0x9 : READ_WAIT
When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
0xC : WRITE
During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xD : READ_REQ
During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xE : CHECK_CHAIN
Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
0xF : XFER_COMPLETE
The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
0x14 : TERMINATE
When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
0x15 : WAIT_END
When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
0x1C : WRITE_WAIT
During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
0x1D : HALT_AFTER_TERM
If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
0x1E : CHECK_WAIT
If the Chain bit is a 0, the state machine enters this state and effectively halts.
0x1F : WAIT_READY
When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
End of enumeration elements list.
WR_FIFO_FULL : This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
bits : 20 - 20 (1 bit)
access : read-only
WR_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
bits : 21 - 21 (1 bit)
access : read-only
RD_FIFO_FULL : This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
bits : 22 - 22 (1 bit)
access : read-only
RD_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
bits : 23 - 23 (1 bit)
access : read-only
NEXTCMDADDRVALID : This bit reflects the internal bit which indicates whether the channel's next command address is valid
bits : 24 - 24 (1 bit)
access : read-only
READY : This bit is reserved for this DMA Channel and always reads 0.
bits : 26 - 26 (1 bit)
access : read-only
END : This bit reflects the current state of the DMA End Command Signal sent from the APB Device
bits : 28 - 28 (1 bit)
access : read-only
KICK : This bit reflects the current state of the DMA Kick Signal sent to the APB Device
bits : 29 - 29 (1 bit)
access : read-only
BURST : This bit reflects the current state of the DMA Burst Signal from the APB device
bits : 30 - 30 (1 bit)
access : read-only
REQ : This bit reflects the current state of the DMA Request Signal from the APB device
bits : 31 - 31 (1 bit)
access : read-only
AHB to APBH Bridge Channel Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREEZE_CHANNEL : Setting a bit in this field will freeze the DMA channel associated with it
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0x1 : NAND0
NAND0
0x2 : NAND1
NAND1
0x4 : NAND2
NAND2
0x8 : NAND3
NAND3
0x10 : NAND4
NAND4
0x20 : NAND5
NAND5
0x40 : NAND6
NAND6
0x80 : NAND7
NAND7
0x100 : SSP
SSP
End of enumeration elements list.
RESET_CHANNEL : Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0x1 : NAND0
NAND0
0x2 : NAND1
NAND1
0x4 : NAND2
NAND2
0x8 : NAND3
NAND3
0x10 : NAND4
NAND4
0x20 : NAND5
NAND5
0x40 : NAND6
NAND6
0x80 : NAND7
NAND7
0x100 : SSP
SSP
End of enumeration elements list.
AHB to APBH DMA Channel n Debug Information
address_offset : 0x3C70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHB_BYTES : This value reflects the current number of AHB bytes remaining to be transfered in the current transfer
bits : 0 - 15 (16 bit)
access : read-only
APB_BYTES : This value reflects the current number of APB bytes remaining to be transfered in the current transfer
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Command Register
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMMAND : This bitfield indicates the type of current command:
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : NO_DMA_XFER
Perform any requested PIO word transfers but terminate command before any DMA transfer.
0x1 : DMA_WRITE
Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
0x2 : DMA_READ
Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
0x3 : DMA_SENSE
Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
End of enumeration elements list.
CHAIN : A value of one indicates that another command is chained onto the end of the current command structure
bits : 2 - 2 (1 bit)
access : read-only
IRQONCMPLT : A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i
bits : 3 - 3 (1 bit)
access : read-only
NANDLOCK : A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels
bits : 4 - 4 (1 bit)
access : read-only
NANDWAIT4READY : A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command
bits : 5 - 5 (1 bit)
access : read-only
SEMAPHORE : A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure
bits : 6 - 6 (1 bit)
access : read-only
WAIT4ENDCMD : A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command
bits : 7 - 7 (1 bit)
access : read-only
HALTONTERMINATE : A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set
bits : 8 - 8 (1 bit)
access : read-only
CMDWORDS : This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there
bits : 12 - 15 (4 bit)
access : read-only
XFER_COUNT : This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Current Command Address Register
address_offset : 0x3DF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to command structure currently being processed for channel n.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Next Command Address Register
address_offset : 0x3EF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to next command structure for channel n.
bits : 0 - 31 (32 bit)
access : read-write
APBH DMA Channel n Command Register
address_offset : 0x3FF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMMAND : This bitfield indicates the type of current command:
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : NO_DMA_XFER
Perform any requested PIO word transfers but terminate command before any DMA transfer.
0x1 : DMA_WRITE
Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
0x2 : DMA_READ
Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
0x3 : DMA_SENSE
Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
End of enumeration elements list.
CHAIN : A value of one indicates that another command is chained onto the end of the current command structure
bits : 2 - 2 (1 bit)
access : read-only
IRQONCMPLT : A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i
bits : 3 - 3 (1 bit)
access : read-only
NANDLOCK : A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels
bits : 4 - 4 (1 bit)
access : read-only
NANDWAIT4READY : A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command
bits : 5 - 5 (1 bit)
access : read-only
SEMAPHORE : A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure
bits : 6 - 6 (1 bit)
access : read-only
WAIT4ENDCMD : A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command
bits : 7 - 7 (1 bit)
access : read-only
HALTONTERMINATE : A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set
bits : 8 - 8 (1 bit)
access : read-only
CMDWORDS : This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there
bits : 12 - 15 (4 bit)
access : read-only
XFER_COUNT : This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device
bits : 16 - 31 (16 bit)
access : read-only
AHB to APBH Bridge Control and Status Register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKGATE_CHANNEL : These bits must be set to zero for normal operation of each channel
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0x1 : NAND0
NAND0
0x2 : NAND1
NAND1
0x4 : NAND2
NAND2
0x8 : NAND3
NAND3
0x10 : NAND4
NAND4
0x20 : NAND5
NAND5
0x40 : NAND6
NAND6
0x80 : NAND7
NAND7
0x100 : SSP
SSP
End of enumeration elements list.
APB_BURST_EN : Set this bit to one to enable apb master do a continous transfers when a device request a burst dma
bits : 28 - 28 (1 bit)
access : read-write
AHB_BURST8_EN : Set this bit to one (default) to enable AHB 8-beat burst
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : This bit must be set to zero for normal operation
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : Set this bit to zero to enable normal APBH DMA operation
bits : 31 - 31 (1 bit)
access : read-write
AHB to APBH DMA Device Assignment Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
APBH DMA Channel n Buffer Address Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of system memory buffer to be read or written over the AHB bus.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Buffer Address Register
address_offset : 0x40F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of system memory buffer to be read or written over the AHB bus.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Semaphore Register
address_offset : 0x41F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_SEMA : The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
PHORE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x42F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATEMACHINE : PIO Display of the DMA Channel n state machine state.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : IDLE
This is the idle state of the DMA state machine.
0x1 : REQ_CMD1
State in which the DMA is waiting to receive the first word of a command.
0x2 : REQ_CMD3
State in which the DMA is waiting to receive the third word of a command.
0x3 : REQ_CMD2
State in which the DMA is waiting to receive the second word of a command.
0x4 : XFER_DECODE
The state machine processes the descriptor command field in this state and branches accordingly.
0x5 : REQ_WAIT
The state machine waits in this state for the PIO APB cycles to complete.
0x6 : REQ_CMD4
State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
0x7 : PIO_REQ
This state determines whether another PIO cycle needs to occur before starting DMA transfers.
0x8 : READ_FLUSH
During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
0x9 : READ_WAIT
When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
0xC : WRITE
During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xD : READ_REQ
During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xE : CHECK_CHAIN
Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
0xF : XFER_COMPLETE
The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
0x14 : TERMINATE
When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
0x15 : WAIT_END
When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
0x1C : WRITE_WAIT
During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
0x1D : HALT_AFTER_TERM
If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
0x1E : CHECK_WAIT
If the Chain bit is a 0, the state machine enters this state and effectively halts.
0x1F : WAIT_READY
When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
End of enumeration elements list.
WR_FIFO_FULL : This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
bits : 20 - 20 (1 bit)
access : read-only
WR_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
bits : 21 - 21 (1 bit)
access : read-only
RD_FIFO_FULL : This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
bits : 22 - 22 (1 bit)
access : read-only
RD_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
bits : 23 - 23 (1 bit)
access : read-only
NEXTCMDADDRVALID : This bit reflects the internal bit which indicates whether the channel's next command address is valid
bits : 24 - 24 (1 bit)
access : read-only
READY : This bit is reserved for this DMA Channel and always reads 0.
bits : 26 - 26 (1 bit)
access : read-only
END : This bit reflects the current state of the DMA End Command Signal sent from the APB Device
bits : 28 - 28 (1 bit)
access : read-only
KICK : This bit reflects the current state of the DMA Kick Signal sent to the APB Device
bits : 29 - 29 (1 bit)
access : read-only
BURST : This bit reflects the current state of the DMA Burst Signal from the APB device
bits : 30 - 30 (1 bit)
access : read-only
REQ : This bit reflects the current state of the DMA Request Signal from the APB device
bits : 31 - 31 (1 bit)
access : read-only
APBH DMA Channel n Semaphore Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_SEMA : The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
PHORE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x43F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHB_BYTES : This value reflects the current number of AHB bytes remaining to be transfered in the current transfer
bits : 0 - 15 (16 bit)
access : read-only
APB_BYTES : This value reflects the current number of APB bytes remaining to be transfered in the current transfer
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Current Command Address Register
address_offset : 0x4580 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to command structure currently being processed for channel n.
bits : 0 - 31 (32 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATEMACHINE : PIO Display of the DMA Channel n state machine state.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : IDLE
This is the idle state of the DMA state machine.
0x1 : REQ_CMD1
State in which the DMA is waiting to receive the first word of a command.
0x2 : REQ_CMD3
State in which the DMA is waiting to receive the third word of a command.
0x3 : REQ_CMD2
State in which the DMA is waiting to receive the second word of a command.
0x4 : XFER_DECODE
The state machine processes the descriptor command field in this state and branches accordingly.
0x5 : REQ_WAIT
The state machine waits in this state for the PIO APB cycles to complete.
0x6 : REQ_CMD4
State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
0x7 : PIO_REQ
This state determines whether another PIO cycle needs to occur before starting DMA transfers.
0x8 : READ_FLUSH
During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
0x9 : READ_WAIT
When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
0xC : WRITE
During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xD : READ_REQ
During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xE : CHECK_CHAIN
Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
0xF : XFER_COMPLETE
The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
0x14 : TERMINATE
When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
0x15 : WAIT_END
When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
0x1C : WRITE_WAIT
During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
0x1D : HALT_AFTER_TERM
If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
0x1E : CHECK_WAIT
If the Chain bit is a 0, the state machine enters this state and effectively halts.
0x1F : WAIT_READY
When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
End of enumeration elements list.
WR_FIFO_FULL : This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
bits : 20 - 20 (1 bit)
access : read-only
WR_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
bits : 21 - 21 (1 bit)
access : read-only
RD_FIFO_FULL : This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
bits : 22 - 22 (1 bit)
access : read-only
RD_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
bits : 23 - 23 (1 bit)
access : read-only
NEXTCMDADDRVALID : This bit reflects the internal bit which indicates whether the channel's next command address is valid
bits : 24 - 24 (1 bit)
access : read-only
READY : This bit is reserved for this DMA Channel and always reads 0.
bits : 26 - 26 (1 bit)
access : read-only
END : This bit reflects the current state of the DMA End Command Signal sent from the APB Device
bits : 28 - 28 (1 bit)
access : read-only
KICK : This bit reflects the current state of the DMA Kick Signal sent to the APB Device
bits : 29 - 29 (1 bit)
access : read-only
BURST : This bit reflects the current state of the DMA Burst Signal from the APB device
bits : 30 - 30 (1 bit)
access : read-only
REQ : This bit reflects the current state of the DMA Request Signal from the APB device
bits : 31 - 31 (1 bit)
access : read-only
APBH DMA Channel n Next Command Address Register
address_offset : 0x4690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to next command structure for channel n.
bits : 0 - 31 (32 bit)
access : read-write
APBH DMA Channel n Command Register
address_offset : 0x47A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMMAND : This bitfield indicates the type of current command:
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : NO_DMA_XFER
Perform any requested PIO word transfers but terminate command before any DMA transfer.
0x1 : DMA_WRITE
Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
0x2 : DMA_READ
Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
0x3 : DMA_SENSE
Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
End of enumeration elements list.
CHAIN : A value of one indicates that another command is chained onto the end of the current command structure
bits : 2 - 2 (1 bit)
access : read-only
IRQONCMPLT : A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i
bits : 3 - 3 (1 bit)
access : read-only
NANDLOCK : A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels
bits : 4 - 4 (1 bit)
access : read-only
NANDWAIT4READY : A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command
bits : 5 - 5 (1 bit)
access : read-only
SEMAPHORE : A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure
bits : 6 - 6 (1 bit)
access : read-only
WAIT4ENDCMD : A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command
bits : 7 - 7 (1 bit)
access : read-only
HALTONTERMINATE : A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set
bits : 8 - 8 (1 bit)
access : read-only
CMDWORDS : This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there
bits : 12 - 15 (4 bit)
access : read-only
XFER_COUNT : This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Buffer Address Register
address_offset : 0x48B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of system memory buffer to be read or written over the AHB bus.
bits : 0 - 31 (32 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHB_BYTES : This value reflects the current number of AHB bytes remaining to be transfered in the current transfer
bits : 0 - 15 (16 bit)
access : read-only
APB_BYTES : This value reflects the current number of APB bytes remaining to be transfered in the current transfer
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Semaphore Register
address_offset : 0x49C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_SEMA : The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
PHORE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x4AD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATEMACHINE : PIO Display of the DMA Channel n state machine state.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : IDLE
This is the idle state of the DMA state machine.
0x1 : REQ_CMD1
State in which the DMA is waiting to receive the first word of a command.
0x2 : REQ_CMD3
State in which the DMA is waiting to receive the third word of a command.
0x3 : REQ_CMD2
State in which the DMA is waiting to receive the second word of a command.
0x4 : XFER_DECODE
The state machine processes the descriptor command field in this state and branches accordingly.
0x5 : REQ_WAIT
The state machine waits in this state for the PIO APB cycles to complete.
0x6 : REQ_CMD4
State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
0x7 : PIO_REQ
This state determines whether another PIO cycle needs to occur before starting DMA transfers.
0x8 : READ_FLUSH
During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
0x9 : READ_WAIT
When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
0xC : WRITE
During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xD : READ_REQ
During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xE : CHECK_CHAIN
Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
0xF : XFER_COMPLETE
The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
0x14 : TERMINATE
When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
0x15 : WAIT_END
When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
0x1C : WRITE_WAIT
During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
0x1D : HALT_AFTER_TERM
If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
0x1E : CHECK_WAIT
If the Chain bit is a 0, the state machine enters this state and effectively halts.
0x1F : WAIT_READY
When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
End of enumeration elements list.
WR_FIFO_FULL : This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
bits : 20 - 20 (1 bit)
access : read-only
WR_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
bits : 21 - 21 (1 bit)
access : read-only
RD_FIFO_FULL : This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
bits : 22 - 22 (1 bit)
access : read-only
RD_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
bits : 23 - 23 (1 bit)
access : read-only
NEXTCMDADDRVALID : This bit reflects the internal bit which indicates whether the channel's next command address is valid
bits : 24 - 24 (1 bit)
access : read-only
READY : This bit is reserved for this DMA Channel and always reads 0.
bits : 26 - 26 (1 bit)
access : read-only
END : This bit reflects the current state of the DMA End Command Signal sent from the APB Device
bits : 28 - 28 (1 bit)
access : read-only
KICK : This bit reflects the current state of the DMA Kick Signal sent to the APB Device
bits : 29 - 29 (1 bit)
access : read-only
BURST : This bit reflects the current state of the DMA Burst Signal from the APB device
bits : 30 - 30 (1 bit)
access : read-only
REQ : This bit reflects the current state of the DMA Request Signal from the APB device
bits : 31 - 31 (1 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x4BE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHB_BYTES : This value reflects the current number of AHB bytes remaining to be transfered in the current transfer
bits : 0 - 15 (16 bit)
access : read-only
APB_BYTES : This value reflects the current number of APB bytes remaining to be transfered in the current transfer
bits : 16 - 31 (16 bit)
access : read-only
AHB to APBH DMA burst size
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : DMA burst size for GPMI channel 0. Do not change. GPMI only support burst size 4.
bits : 0 - 1 (2 bit)
access : read-write
CH1 : DMA burst size for GPMI channel 1. Do not change. GPMI only support burst size 4.
bits : 2 - 3 (2 bit)
access : read-write
CH2 : DMA burst size for GPMI channel 2. Do not change. GPMI only support burst size 4.
bits : 4 - 5 (2 bit)
access : read-write
CH3 : DMA burst size for GPMI channel 3. Do not change. GPMI only support burst size 4.
bits : 6 - 7 (2 bit)
access : read-write
CH4 : DMA burst size for GPMI channel 4. Do not change. GPMI only support burst size 4.
bits : 8 - 9 (2 bit)
access : read-write
CH5 : DMA burst size for GPMI channel 5. Do not change. GPMI only support burst size 4.
bits : 10 - 11 (2 bit)
access : read-write
CH6 : DMA burst size for GPMI channel 6. Do not change. GPMI only support burst size 4.
bits : 12 - 13 (2 bit)
access : read-write
CH7 : DMA burst size for GPMI channel 7. Do not change. GPMI only support burst size 4.
bits : 14 - 15 (2 bit)
access : read-write
CH8 : DMA burst size for SSP.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : BURST0
BURST0
0x1 : BURST4
BURST4
0x2 : BURST8
BURST8
End of enumeration elements list.
APBH DMA Channel n Current Command Address Register
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to command structure currently being processed for channel n.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Next Command Address Register
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to next command structure for channel n.
bits : 0 - 31 (32 bit)
access : read-write
APBH DMA Channel n Command Register
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMMAND : This bitfield indicates the type of current command:
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : NO_DMA_XFER
Perform any requested PIO word transfers but terminate command before any DMA transfer.
0x1 : DMA_WRITE
Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
0x2 : DMA_READ
Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
0x3 : DMA_SENSE
Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
End of enumeration elements list.
CHAIN : A value of one indicates that another command is chained onto the end of the current command structure
bits : 2 - 2 (1 bit)
access : read-only
IRQONCMPLT : A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i
bits : 3 - 3 (1 bit)
access : read-only
NANDLOCK : A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels
bits : 4 - 4 (1 bit)
access : read-only
NANDWAIT4READY : A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command
bits : 5 - 5 (1 bit)
access : read-only
SEMAPHORE : A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure
bits : 6 - 6 (1 bit)
access : read-only
WAIT4ENDCMD : A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command
bits : 7 - 7 (1 bit)
access : read-only
HALTONTERMINATE : A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set
bits : 8 - 8 (1 bit)
access : read-only
CMDWORDS : This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there
bits : 12 - 15 (4 bit)
access : read-only
XFER_COUNT : This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device
bits : 16 - 31 (16 bit)
access : read-only
AHB to APBH DMA Debug Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPMI_ONE_FIFO : Set to 0ne and the 8 GPMI channels will share the DMA FIFO, and when set to zero, the 8 GPMI channels will use its own DMA FIFO
bits : 0 - 0 (1 bit)
access : read-write
APBH DMA Channel n Buffer Address Register
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of system memory buffer to be read or written over the AHB bus.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Semaphore Register
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_SEMA : The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
PHORE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATEMACHINE : PIO Display of the DMA Channel n state machine state.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : IDLE
This is the idle state of the DMA state machine.
0x1 : REQ_CMD1
State in which the DMA is waiting to receive the first word of a command.
0x2 : REQ_CMD3
State in which the DMA is waiting to receive the third word of a command.
0x3 : REQ_CMD2
State in which the DMA is waiting to receive the second word of a command.
0x4 : XFER_DECODE
The state machine processes the descriptor command field in this state and branches accordingly.
0x5 : REQ_WAIT
The state machine waits in this state for the PIO APB cycles to complete.
0x6 : REQ_CMD4
State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
0x7 : PIO_REQ
This state determines whether another PIO cycle needs to occur before starting DMA transfers.
0x8 : READ_FLUSH
During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
0x9 : READ_WAIT
When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
0xC : WRITE
During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xD : READ_REQ
During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xE : CHECK_CHAIN
Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
0xF : XFER_COMPLETE
The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
0x14 : TERMINATE
When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
0x15 : WAIT_END
When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
0x1C : WRITE_WAIT
During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
0x1D : HALT_AFTER_TERM
If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
0x1E : CHECK_WAIT
If the Chain bit is a 0, the state machine enters this state and effectively halts.
0x1F : WAIT_READY
When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
End of enumeration elements list.
WR_FIFO_FULL : This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
bits : 20 - 20 (1 bit)
access : read-only
WR_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
bits : 21 - 21 (1 bit)
access : read-only
RD_FIFO_FULL : This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
bits : 22 - 22 (1 bit)
access : read-only
RD_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
bits : 23 - 23 (1 bit)
access : read-only
NEXTCMDADDRVALID : This bit reflects the internal bit which indicates whether the channel's next command address is valid
bits : 24 - 24 (1 bit)
access : read-only
READY : This bit is reserved for this DMA Channel and always reads 0.
bits : 26 - 26 (1 bit)
access : read-only
END : This bit reflects the current state of the DMA End Command Signal sent from the APB Device
bits : 28 - 28 (1 bit)
access : read-only
KICK : This bit reflects the current state of the DMA Kick Signal sent to the APB Device
bits : 29 - 29 (1 bit)
access : read-only
BURST : This bit reflects the current state of the DMA Burst Signal from the APB device
bits : 30 - 30 (1 bit)
access : read-only
REQ : This bit reflects the current state of the DMA Request Signal from the APB device
bits : 31 - 31 (1 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x6D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHB_BYTES : This value reflects the current number of AHB bytes remaining to be transfered in the current transfer
bits : 0 - 15 (16 bit)
access : read-only
APB_BYTES : This value reflects the current number of APB bytes remaining to be transfered in the current transfer
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Current Command Address Register
address_offset : 0x7A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to command structure currently being processed for channel n.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Next Command Address Register
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to next command structure for channel n.
bits : 0 - 31 (32 bit)
access : read-write
AHB to APBH Bridge Control and Status Register 0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKGATE_CHANNEL : These bits must be set to zero for normal operation of each channel
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0x1 : NAND0
NAND0
0x2 : NAND1
NAND1
0x4 : NAND2
NAND2
0x8 : NAND3
NAND3
0x10 : NAND4
NAND4
0x20 : NAND5
NAND5
0x40 : NAND6
NAND6
0x80 : NAND7
NAND7
0x100 : SSP
SSP
End of enumeration elements list.
APB_BURST_EN : Set this bit to one to enable apb master do a continous transfers when a device request a burst dma
bits : 28 - 28 (1 bit)
access : read-write
AHB_BURST8_EN : Set this bit to one (default) to enable AHB 8-beat burst
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : This bit must be set to zero for normal operation
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : Set this bit to zero to enable normal APBH DMA operation
bits : 31 - 31 (1 bit)
access : read-write
APBH Bridge Version Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STEP : Fixed read-only value reflecting the stepping of the RTL version.
bits : 0 - 15 (16 bit)
access : read-only
MINOR : Fixed read-only value reflecting the MINOR field of the RTL version.
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Fixed read-only value reflecting the MAJOR field of the RTL version.
bits : 24 - 31 (8 bit)
access : read-only
APBH DMA Channel n Command Register
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMMAND : This bitfield indicates the type of current command:
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : NO_DMA_XFER
Perform any requested PIO word transfers but terminate command before any DMA transfer.
0x1 : DMA_WRITE
Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
0x2 : DMA_READ
Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
0x3 : DMA_SENSE
Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
End of enumeration elements list.
CHAIN : A value of one indicates that another command is chained onto the end of the current command structure
bits : 2 - 2 (1 bit)
access : read-only
IRQONCMPLT : A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i
bits : 3 - 3 (1 bit)
access : read-only
NANDLOCK : A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels
bits : 4 - 4 (1 bit)
access : read-only
NANDWAIT4READY : A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command
bits : 5 - 5 (1 bit)
access : read-only
SEMAPHORE : A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure
bits : 6 - 6 (1 bit)
access : read-only
WAIT4ENDCMD : A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command
bits : 7 - 7 (1 bit)
access : read-only
HALTONTERMINATE : A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set
bits : 8 - 8 (1 bit)
access : read-only
CMDWORDS : This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there
bits : 12 - 15 (4 bit)
access : read-only
XFER_COUNT : This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Buffer Address Register
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of system memory buffer to be read or written over the AHB bus.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Semaphore Register
address_offset : 0x8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_SEMA : The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
PHORE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATEMACHINE : PIO Display of the DMA Channel n state machine state.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : IDLE
This is the idle state of the DMA state machine.
0x1 : REQ_CMD1
State in which the DMA is waiting to receive the first word of a command.
0x2 : REQ_CMD3
State in which the DMA is waiting to receive the third word of a command.
0x3 : REQ_CMD2
State in which the DMA is waiting to receive the second word of a command.
0x4 : XFER_DECODE
The state machine processes the descriptor command field in this state and branches accordingly.
0x5 : REQ_WAIT
The state machine waits in this state for the PIO APB cycles to complete.
0x6 : REQ_CMD4
State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
0x7 : PIO_REQ
This state determines whether another PIO cycle needs to occur before starting DMA transfers.
0x8 : READ_FLUSH
During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
0x9 : READ_WAIT
When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
0xC : WRITE
During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xD : READ_REQ
During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xE : CHECK_CHAIN
Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
0xF : XFER_COMPLETE
The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
0x14 : TERMINATE
When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
0x15 : WAIT_END
When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
0x1C : WRITE_WAIT
During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
0x1D : HALT_AFTER_TERM
If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
0x1E : CHECK_WAIT
If the Chain bit is a 0, the state machine enters this state and effectively halts.
0x1F : WAIT_READY
When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
End of enumeration elements list.
WR_FIFO_FULL : This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
bits : 20 - 20 (1 bit)
access : read-only
WR_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
bits : 21 - 21 (1 bit)
access : read-only
RD_FIFO_FULL : This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
bits : 22 - 22 (1 bit)
access : read-only
RD_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
bits : 23 - 23 (1 bit)
access : read-only
NEXTCMDADDRVALID : This bit reflects the internal bit which indicates whether the channel's next command address is valid
bits : 24 - 24 (1 bit)
access : read-only
READY : This bit is reserved for this DMA Channel and always reads 0.
bits : 26 - 26 (1 bit)
access : read-only
END : This bit reflects the current state of the DMA End Command Signal sent from the APB Device
bits : 28 - 28 (1 bit)
access : read-only
KICK : This bit reflects the current state of the DMA Kick Signal sent to the APB Device
bits : 29 - 29 (1 bit)
access : read-only
BURST : This bit reflects the current state of the DMA Burst Signal from the APB device
bits : 30 - 30 (1 bit)
access : read-only
REQ : This bit reflects the current state of the DMA Request Signal from the APB device
bits : 31 - 31 (1 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0x980 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHB_BYTES : This value reflects the current number of AHB bytes remaining to be transfered in the current transfer
bits : 0 - 15 (16 bit)
access : read-only
APB_BYTES : This value reflects the current number of APB bytes remaining to be transfered in the current transfer
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Current Command Address Register
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to command structure currently being processed for channel n.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Next Command Address Register
address_offset : 0xAC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to next command structure for channel n.
bits : 0 - 31 (32 bit)
access : read-write
APBH DMA Channel n Command Register
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMMAND : This bitfield indicates the type of current command:
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : NO_DMA_XFER
Perform any requested PIO word transfers but terminate command before any DMA transfer.
0x1 : DMA_WRITE
Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
0x2 : DMA_READ
Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
0x3 : DMA_SENSE
Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
End of enumeration elements list.
CHAIN : A value of one indicates that another command is chained onto the end of the current command structure
bits : 2 - 2 (1 bit)
access : read-only
IRQONCMPLT : A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i
bits : 3 - 3 (1 bit)
access : read-only
NANDLOCK : A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels
bits : 4 - 4 (1 bit)
access : read-only
NANDWAIT4READY : A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command
bits : 5 - 5 (1 bit)
access : read-only
SEMAPHORE : A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure
bits : 6 - 6 (1 bit)
access : read-only
WAIT4ENDCMD : A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command
bits : 7 - 7 (1 bit)
access : read-only
HALTONTERMINATE : A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set
bits : 8 - 8 (1 bit)
access : read-only
CMDWORDS : This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there
bits : 12 - 15 (4 bit)
access : read-only
XFER_COUNT : This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Buffer Address Register
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of system memory buffer to be read or written over the AHB bus.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Semaphore Register
address_offset : 0xBE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_SEMA : The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
PHORE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
AHB to APBH Bridge Control and Status Register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKGATE_CHANNEL : These bits must be set to zero for normal operation of each channel
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0x1 : NAND0
NAND0
0x2 : NAND1
NAND1
0x4 : NAND2
NAND2
0x8 : NAND3
NAND3
0x10 : NAND4
NAND4
0x20 : NAND5
NAND5
0x40 : NAND6
NAND6
0x80 : NAND7
NAND7
0x100 : SSP
SSP
End of enumeration elements list.
APB_BURST_EN : Set this bit to one to enable apb master do a continous transfers when a device request a burst dma
bits : 28 - 28 (1 bit)
access : read-write
AHB_BURST8_EN : Set this bit to one (default) to enable AHB 8-beat burst
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : This bit must be set to zero for normal operation
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : Set this bit to zero to enable normal APBH DMA operation
bits : 31 - 31 (1 bit)
access : read-write
AHB to APBH DMA Channel n Debug Information
address_offset : 0xC40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATEMACHINE : PIO Display of the DMA Channel n state machine state.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : IDLE
This is the idle state of the DMA state machine.
0x1 : REQ_CMD1
State in which the DMA is waiting to receive the first word of a command.
0x2 : REQ_CMD3
State in which the DMA is waiting to receive the third word of a command.
0x3 : REQ_CMD2
State in which the DMA is waiting to receive the second word of a command.
0x4 : XFER_DECODE
The state machine processes the descriptor command field in this state and branches accordingly.
0x5 : REQ_WAIT
The state machine waits in this state for the PIO APB cycles to complete.
0x6 : REQ_CMD4
State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
0x7 : PIO_REQ
This state determines whether another PIO cycle needs to occur before starting DMA transfers.
0x8 : READ_FLUSH
During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
0x9 : READ_WAIT
When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
0xC : WRITE
During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xD : READ_REQ
During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xE : CHECK_CHAIN
Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
0xF : XFER_COMPLETE
The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
0x14 : TERMINATE
When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
0x15 : WAIT_END
When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
0x1C : WRITE_WAIT
During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
0x1D : HALT_AFTER_TERM
If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
0x1E : CHECK_WAIT
If the Chain bit is a 0, the state machine enters this state and effectively halts.
0x1F : WAIT_READY
When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
End of enumeration elements list.
WR_FIFO_FULL : This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
bits : 20 - 20 (1 bit)
access : read-only
WR_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
bits : 21 - 21 (1 bit)
access : read-only
RD_FIFO_FULL : This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
bits : 22 - 22 (1 bit)
access : read-only
RD_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
bits : 23 - 23 (1 bit)
access : read-only
NEXTCMDADDRVALID : This bit reflects the internal bit which indicates whether the channel's next command address is valid
bits : 24 - 24 (1 bit)
access : read-only
READY : This bit is reserved for this DMA Channel and always reads 0.
bits : 26 - 26 (1 bit)
access : read-only
END : This bit reflects the current state of the DMA End Command Signal sent from the APB Device
bits : 28 - 28 (1 bit)
access : read-only
KICK : This bit reflects the current state of the DMA Kick Signal sent to the APB Device
bits : 29 - 29 (1 bit)
access : read-only
BURST : This bit reflects the current state of the DMA Burst Signal from the APB device
bits : 30 - 30 (1 bit)
access : read-only
REQ : This bit reflects the current state of the DMA Request Signal from the APB device
bits : 31 - 31 (1 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0xCA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHB_BYTES : This value reflects the current number of AHB bytes remaining to be transfered in the current transfer
bits : 0 - 15 (16 bit)
access : read-only
APB_BYTES : This value reflects the current number of APB bytes remaining to be transfered in the current transfer
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Current Command Address Register
address_offset : 0xD90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to command structure currently being processed for channel n.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Next Command Address Register
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ADDR : Pointer to next command structure for channel n.
bits : 0 - 31 (32 bit)
access : read-write
APBH DMA Channel n Command Register
address_offset : 0xE70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMMAND : This bitfield indicates the type of current command:
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : NO_DMA_XFER
Perform any requested PIO word transfers but terminate command before any DMA transfer.
0x1 : DMA_WRITE
Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
0x2 : DMA_READ
Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
0x3 : DMA_SENSE
Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
End of enumeration elements list.
CHAIN : A value of one indicates that another command is chained onto the end of the current command structure
bits : 2 - 2 (1 bit)
access : read-only
IRQONCMPLT : A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i
bits : 3 - 3 (1 bit)
access : read-only
NANDLOCK : A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels
bits : 4 - 4 (1 bit)
access : read-only
NANDWAIT4READY : A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command
bits : 5 - 5 (1 bit)
access : read-only
SEMAPHORE : A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure
bits : 6 - 6 (1 bit)
access : read-only
WAIT4ENDCMD : A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command
bits : 7 - 7 (1 bit)
access : read-only
HALTONTERMINATE : A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set
bits : 8 - 8 (1 bit)
access : read-only
CMDWORDS : This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there
bits : 12 - 15 (4 bit)
access : read-only
XFER_COUNT : This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device
bits : 16 - 31 (16 bit)
access : read-only
APBH DMA Channel n Buffer Address Register
address_offset : 0xEE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of system memory buffer to be read or written over the AHB bus.
bits : 0 - 31 (32 bit)
access : read-only
APBH DMA Channel n Semaphore Register
address_offset : 0xF50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCREMENT_SEMA : The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected
bits : 0 - 7 (8 bit)
access : read-write
PHORE : This read-only field shows the current (instantaneous) value of the semaphore counter.
bits : 16 - 23 (8 bit)
access : read-only
AHB to APBH DMA Channel n Debug Information
address_offset : 0xFC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATEMACHINE : PIO Display of the DMA Channel n state machine state.
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0 : IDLE
This is the idle state of the DMA state machine.
0x1 : REQ_CMD1
State in which the DMA is waiting to receive the first word of a command.
0x2 : REQ_CMD3
State in which the DMA is waiting to receive the third word of a command.
0x3 : REQ_CMD2
State in which the DMA is waiting to receive the second word of a command.
0x4 : XFER_DECODE
The state machine processes the descriptor command field in this state and branches accordingly.
0x5 : REQ_WAIT
The state machine waits in this state for the PIO APB cycles to complete.
0x6 : REQ_CMD4
State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
0x7 : PIO_REQ
This state determines whether another PIO cycle needs to occur before starting DMA transfers.
0x8 : READ_FLUSH
During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
0x9 : READ_WAIT
When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
0xC : WRITE
During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xD : READ_REQ
During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
0xE : CHECK_CHAIN
Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
0xF : XFER_COMPLETE
The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
0x14 : TERMINATE
When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
0x15 : WAIT_END
When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
0x1C : WRITE_WAIT
During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
0x1D : HALT_AFTER_TERM
If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
0x1E : CHECK_WAIT
If the Chain bit is a 0, the state machine enters this state and effectively halts.
0x1F : WAIT_READY
When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
End of enumeration elements list.
WR_FIFO_FULL : This bit reflects the current state of the DMA Channel's Write FIFO Full signal.
bits : 20 - 20 (1 bit)
access : read-only
WR_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Write FIFO Empty signal.
bits : 21 - 21 (1 bit)
access : read-only
RD_FIFO_FULL : This bit reflects the current state of the DMA Channel's Read FIFO Full signal.
bits : 22 - 22 (1 bit)
access : read-only
RD_FIFO_EMPTY : This bit reflects the current state of the DMA Channel's Read FIFO Empty signal.
bits : 23 - 23 (1 bit)
access : read-only
NEXTCMDADDRVALID : This bit reflects the internal bit which indicates whether the channel's next command address is valid
bits : 24 - 24 (1 bit)
access : read-only
READY : This bit is reserved for this DMA Channel and always reads 0.
bits : 26 - 26 (1 bit)
access : read-only
END : This bit reflects the current state of the DMA End Command Signal sent from the APB Device
bits : 28 - 28 (1 bit)
access : read-only
KICK : This bit reflects the current state of the DMA Kick Signal sent to the APB Device
bits : 29 - 29 (1 bit)
access : read-only
BURST : This bit reflects the current state of the DMA Burst Signal from the APB device
bits : 30 - 30 (1 bit)
access : read-only
REQ : This bit reflects the current state of the DMA Request Signal from the APB device
bits : 31 - 31 (1 bit)
access : read-only
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