\n
address_offset : 0x0 Bytes (0x0)
size : 0x3B0 byte (0x0)
mem_usage : registers
protection : not protected
no description available
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL_FNC_FB : Valid only when {mode_phy, mode_nand, mode_scan, mode_mux} is 4'b00000
bits : 0 - 2 (3 bit)
access : read-write
CTRL_TWPRE : Write preamble setting Initial Value = 1'b0
bits : 3 - 3 (1 bit)
access : read-write
CTRL_CMOSRCV : This field controls the input mode of I/O. Initial Value = 1'b0
bits : 4 - 4 (1 bit)
access : read-write
CTRL_ATGATE : This bit should be set to 1'b1. Initial Value = 1'b1
bits : 6 - 6 (1 bit)
access : read-write
CTRL_SHGATE : This field controls the gate control signal Initial Value = 1'b0
bits : 8 - 8 (1 bit)
access : read-write
CTRL_DFDQS : Initial Value = 1'b1
bits : 9 - 9 (1 bit)
access : read-write
CTRL_DDR_MODE : Initial Value = 2'b11
bits : 11 - 12 (2 bit)
access : read-write
WRLVL_MODE : Write Leveling Mode Enable Initial Value = 1'b0
bits : 16 - 16 (1 bit)
access : read-write
CTRL_UPD_RANGE : It decides how many differences between the new lock value and the current lock value which is used in Slave-DLL is needed for updating lock value
bits : 20 - 21 (2 bit)
access : read-write
CTRL_UPD_MODE : It controls when DLL is updated. Initial Value = 2'b01
bits : 22 - 23 (2 bit)
access : read-write
no description available
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL_RDLAT : Read Latency (RL) Initial Value = 5'h0
bits : 0 - 4 (5 bit)
access : read-write
CTRL_BSTLEN : Burst Length (BL) Initial Value = 5'h0
bits : 8 - 12 (5 bit)
access : read-write
CTRL_WRLAT : Clock cycles between write command and the first edge of DQS which can capture the first valid DQ
bits : 16 - 20 (5 bit)
access : read-write
no description available
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL_WRLAT_PLUS1_0 : This field can control Write Latency (WL) by half cycle, one or two cycles for Data_Slice0
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : CTRL_WRLAT_PLUS1_0_0
Write Latency Increases by half clock cycle when enabled.
0x1 : CTRL_WRLAT_PLUS1_0_1
Write Latency Increases by one clock cycle when enabled.
0x2 : CTRL_WRLAT_PLUS1_0_2
Write Latency Increases by wo clock cycle when enabled.
End of enumeration elements list.
CTRL_WRLAT_PLUS1_1 : This field can control Write Latency (WL) by half cycle, one or two cycles for Data_Slice1
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : CTRL_WRLAT_PLUS1_1_0
Write Latency Increases by half clock cycle when enabled.
0x1 : CTRL_WRLAT_PLUS1_1_1
Write Latency Increases by one clock cycle when enabled.
0x2 : CTRL_WRLAT_PLUS1_1_2
Write Latency Increases by wo clock cycle when enabled.
End of enumeration elements list.
CTRL_WRLAT_PLUS2 : This field can control Write Latency (WL) by half cycle, one or two cycles for Data_Slice2
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : CTRL_WRLAT_PLUS2_0
Write Latency Increases by half clock cycle when enabled.
0x1 : CTRL_WRLAT_PLUS2_1
Write Latency Increases by one clock cycle when enabled.
0x2 : CTRL_WRLAT_PLUS2_2
Write Latency Increases by wo clock cycle when enabled.
End of enumeration elements list.
CTRL_WRLAT_PLUS3 : This field can control Write Latency (WL) by half cycle, one or two cycles for Data_Slice3
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : CTRL_WRLAT_PLUS3_0
Write Latency Increases by half clock cycle when enabled.
0x1 : CTRL_WRLAT_PLUS3_1
Write Latency Increases by one clock cycle when enabled.
0x2 : CTRL_WRLAT_PLUS3_2
Write Latency Increases by wo clock cycle when enabled.
End of enumeration elements list.
no description available
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL_PULLD_DQS : Active HIGH signal to pull-up or down PDQS / NDQS signals
bits : 0 - 8 (9 bit)
access : read-write
CTRL_PULLD_DQ : Active HIGH signal to down DQ signals
bits : 16 - 24 (9 bit)
access : read-write
no description available
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD0DESKEW0 : Read DQ0 De-Skew Code
bits : 0 - 7 (8 bit)
access : read-only
RD0DESKEW1 : Read DQ8 De-Skew Code
bits : 8 - 15 (8 bit)
access : read-only
RD0DESKEW2 : Read DQ16 De-Skew Code
bits : 16 - 23 (8 bit)
access : read-only
RD0DESKEW3 : Read DQ24 De-Skew Code
bits : 24 - 31 (8 bit)
access : read-only
no description available
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD1DESKEW0 : Read DQ1 De-Skew Code
bits : 0 - 7 (8 bit)
access : read-only
RD1DESKEW1 : Read DQ9 De-Skew Code
bits : 8 - 15 (8 bit)
access : read-only
RD1DESKEW2 : Read DQ17 De-Skew Code
bits : 16 - 23 (8 bit)
access : read-only
RD1DESKEW3 : Read DQ25 De-Skew Code
bits : 24 - 31 (8 bit)
access : read-only
no description available
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD2DESKEW0 : Read DQ2 De-Skew Code
bits : 0 - 7 (8 bit)
access : read-only
RD2DESKEW1 : Read DQ10 De-Skew Code
bits : 8 - 15 (8 bit)
access : read-only
RD2DESKEW2 : Read DQ18 De-Skew Code
bits : 16 - 23 (8 bit)
access : read-only
RD2DESKEW3 : Read DQ26 De-Skew Code
bits : 24 - 31 (8 bit)
access : read-only
no description available
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD3DESKEW0 : Read DQ3 De-Skew Code
bits : 0 - 7 (8 bit)
access : read-only
RD3DESKEW1 : Read DQ11 De-Skew Code
bits : 8 - 15 (8 bit)
access : read-only
RD3DESKEW2 : Read DQ19 De-Skew Code
bits : 16 - 23 (8 bit)
access : read-only
RD3DESKEW3 : Read DQ27 De-Skew Code
bits : 24 - 31 (8 bit)
access : read-only
no description available
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL_READ_DIS : Read ODT (On-Die-Termination) Disable Signal
bits : 16 - 16 (1 bit)
access : read-write
no description available
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD4DESKEW0 : Read DQ4 De-Skew Code
bits : 0 - 7 (8 bit)
access : read-only
RD4DESKEW1 : Read DQ12 De-Skew Code
bits : 8 - 15 (8 bit)
access : read-only
RD4DESKEW2 : Read DQ20 De-Skew Code
bits : 16 - 23 (8 bit)
access : read-only
RD4DESKEW3 : Read DQ28 De-Skew Code
bits : 24 - 31 (8 bit)
access : read-only
no description available
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD5DESKEW0 : Read DQ5 De-Skew Code
bits : 0 - 7 (8 bit)
access : read-only
RD5DESKEW1 : Read DQ13 De-Skew Code
bits : 8 - 15 (8 bit)
access : read-only
RD5DESKEW2 : Read DQ21 De-Skew Code
bits : 16 - 23 (8 bit)
access : read-only
RD5DESKEW3 : Read DQ29 De-Skew Code
bits : 24 - 31 (8 bit)
access : read-only
no description available
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD6DESKEW0 : Read DQ6 De-Skew Code
bits : 0 - 7 (8 bit)
access : read-only
RD6DESKEW1 : Read DQ14 De-Skew Code
bits : 8 - 15 (8 bit)
access : read-only
RD6DESKEW2 : Read DQ22 De-Skew Code
bits : 16 - 23 (8 bit)
access : read-only
RD6DESKEW3 : Read DQ30 De-Skew Code
bits : 24 - 31 (8 bit)
access : read-only
no description available
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD7DESKEW0 : Read DQ7 De-Skew Code
bits : 0 - 7 (8 bit)
access : read-only
RD7DESKEW1 : Read DQ15 De-Skew Code
bits : 8 - 15 (8 bit)
access : read-only
RD7DESKEW2 : Read DQ23 De-Skew Code
bits : 16 - 23 (8 bit)
access : read-only
RD7DESKEW3 : Read DQ31 De-Skew Code
bits : 24 - 31 (8 bit)
access : read-only
no description available
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR0DESKEW0 : Write DQ0 De-Skew Code
bits : 0 - 7 (8 bit)
access : read-write
WR0DESKEW1 : Write DQ8 De-Skew Code
bits : 8 - 15 (8 bit)
access : read-write
WR0DESKEW2 : Write DQ16 De-Skew Code
bits : 16 - 23 (8 bit)
access : read-write
WR0DESKEW3 : Wirte DQ24 De-Skew Code
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR1DESKEW0 : Write DQ1 De-Skew Code
bits : 0 - 7 (8 bit)
access : read-write
WR1DESKEW1 : Write DQ9 De-Skew Code
bits : 8 - 15 (8 bit)
access : read-write
WR1DESKEW2 : Write DQ17 De-Skew Code
bits : 16 - 23 (8 bit)
access : read-write
WR1DESKEW3 : Write DQ25 De-Skew Code
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL_OFFSETR0 : This field can be used to give offset to read DQS
bits : 0 - 7 (8 bit)
access : read-write
CTRL_OFFSETR1 : This field can be used to give offset to read DQS
bits : 8 - 15 (8 bit)
access : read-write
CTRL_OFFSETR2 : This field can be used to give offset to read DQS
bits : 16 - 23 (8 bit)
access : read-write
CTRL_OFFSETR3 : This field can be used to give offset to read DQS
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR2DESKEW0 : Write DQ2 De-Skew Code for Data Slice0.
bits : 0 - 7 (8 bit)
access : read-write
WR2DESKEW1 : Write DQ2 De-Skew Code for Data Slice1.
bits : 8 - 15 (8 bit)
access : read-write
WR2DESKEW2 : Write DQ2 De-Skew Code for Data Slice2.
bits : 16 - 23 (8 bit)
access : read-write
WR2DESKEW3 : Write DQ2 De-Skew Code for Data Slice3.
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR3DESKEW0 : Write DQ3 De-Skew Code for Data Slice0.
bits : 0 - 7 (8 bit)
access : read-write
WR3DESKEW1 : Write DQ3 De-Skew Code for Data Slice1.
bits : 8 - 15 (8 bit)
access : read-write
WR3DESKEW2 : Write DQ3 De-Skew Code for Data Slice2.
bits : 16 - 23 (8 bit)
access : read-write
WR3DESKEW3 : Write DQ3 De-Skew Code for Data Slice3.
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR4DESKEW0 : Write DQ4 De-Skew Code for Data Slice0.
bits : 0 - 7 (8 bit)
access : read-write
WR4DESKEW1 : Write DQ4 De-Skew Code for Data Slice1.
bits : 8 - 15 (8 bit)
access : read-write
WR4DESKEW2 : Write DQ4 De-Skew Code for Data Slice2.
bits : 16 - 23 (8 bit)
access : read-write
WR4DESKEW3 : Write DQ4 De-Skew Code for Data Slice3.
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR5DESKEW0 : Write DQ5 De-Skew Code for Data Slice0.
bits : 0 - 7 (8 bit)
access : read-write
WR5DESKEW1 : Write DQ5 De-Skew Code for Data Slice1.
bits : 8 - 15 (8 bit)
access : read-write
WR5DESKEW2 : Write DQ5 De-Skew Code for Data Slice2.
bits : 16 - 23 (8 bit)
access : read-write
WR5DESKEW3 : Write DQ5 De-Skew Code for Data Slice3.
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD6DESKEW0 : Read DQ6 De-Skew Code for Data Slice0.
bits : 0 - 7 (8 bit)
access : read-only
WR6DESKEW1 : Write DQ6 De-Skew Code for Data Slice1.
bits : 8 - 15 (8 bit)
access : read-write
WR6DESKEW2 : Write DQ6 De-Skew Code for Data Slice2.
bits : 16 - 23 (8 bit)
access : read-write
WR6DESKEW3 : Write DQ6 De-Skew Code for Data Slice3.
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR7DESKEW0 : Write DQ7 De-Skew Code for Data Slice0.
bits : 0 - 7 (8 bit)
access : read-write
WR7DESKEW1 : Write DQ7 De-Skew Code for Data Slice1.
bits : 8 - 15 (8 bit)
access : read-write
WR7DESKEW2 : Write DQ7 De-Skew Code for Data Slice2.
bits : 16 - 23 (8 bit)
access : read-write
WR7DESKEW3 : Write DQ7 De-Skew Code for Data Slice3.
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMDESKEW0 : Write DM De-Skew Code for Data Slice0.
bits : 0 - 7 (8 bit)
access : read-write
DMDESKEW1 : Write DM De-Skew Code for Data Slice1.
bits : 8 - 15 (8 bit)
access : read-write
DMDESKEW2 : Write DM De-Skew Code for Data Slice2.
bits : 16 - 23 (8 bit)
access : read-write
DMDESKEW3 : Write DM De-Skew Code for Data Slice3.
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL_OFFSETW0 : This field can be used to give offset to write DQ
bits : 0 - 7 (8 bit)
access : read-write
CTRL_OFFSETW1 : This field can be used to give offset to write DQ
bits : 8 - 15 (8 bit)
access : read-write
CTRL_OFFSETW2 : This field can be used to give offset to write DQ
bits : 16 - 23 (8 bit)
access : read-write
CTRL_OFFSETW3 : This field can be used to give offset to write DQ
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DQ_IO_RD0 : DQ I/O Read Data for DS0
bits : 0 - 7 (8 bit)
access : read-only
DQ_IO_RD1 : DQ I/O Read Data for DS1
bits : 8 - 15 (8 bit)
access : read-only
DQ_IO_RD2 : DQ I/O Read Data for DS2
bits : 16 - 23 (8 bit)
access : read-only
DQ_IO_RD3 : DQ I/O Read Data for DS3
bits : 24 - 31 (8 bit)
access : read-only
no description available
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION_INFO : Version Information
bits : 0 - 31 (32 bit)
access : read-only
no description available
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ctrl_gateduradj : It adjusts the duration cycle of "ctrl_gate" on a clock cycle base
bits : 20 - 23 (4 bit)
access : read-write
CTRL_GATEADJ : It adjusts the enable time of "ctrl_gate" on a clock cycle base
bits : 28 - 31 (4 bit)
access : read-write
no description available
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL_OFFSETC0 : Gate offset amount for DDR3 Data Slice 0
bits : 0 - 7 (8 bit)
access : read-write
CTRL_OFFSETC1 : Gate offset amount for DDR3 Data Slice 1
bits : 8 - 15 (8 bit)
access : read-write
CTRL_OFFSETC2 : Gate offset amount for DDR3 Data Slice 2
bits : 16 - 23 (8 bit)
access : read-write
CTRL_OFFSETC3 : Gate offset amount for DDR3 Data Slice 3
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL_SHIFTC0 : GATEin signal delay amount for DDR
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : CTRL_SHIFTC0_0
0 (0degree shift)
0x1 : CTRL_SHIFTC0_1
T (365degree shift)
0x2 : CTRL_SHIFTC0_2
T / 2 (180degree shift)
0x3 : CTRL_SHIFTC0_3
T / 4 (90degree shift)
0x4 : CTRL_SHIFTC0_4
T / 8 (45degree shift)
0x5 : CTRL_SHIFTC0_5
T / 16 (22.5degree shift)
End of enumeration elements list.
CTRL_SHIFTC1 : GATEin signal delay amount for DDR
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
0 : CTRL_SHIFTC1_0
0 (0degree shift)
0x1 : CTRL_SHIFTC1_1
T (365degree shift)
0x2 : CTRL_SHIFTC1_2
T / 2 (180degree shift)
0x3 : CTRL_SHIFTC1_3
T / 4 (90degree shift)
0x4 : CTRL_SHIFTC1_4
T / 8 (45degree shift)
0x5 : CTRL_SHIFTC1_5
T / 16 (22.5degree shift)
End of enumeration elements list.
CTRL_SHIFTC2 : GATEin signal delay amount for DDR
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : CTRL_SHIFTC2_0
0 (0degree shift)
0x1 : CTRL_SHIFTC2_1
T (365degree shift)
0x2 : CTRL_SHIFTC2_2
T / 2 (180degree shift)
0x3 : CTRL_SHIFTC2_3
T / 4 (90degree shift)
0x4 : CTRL_SHIFTC2_4
T / 8 (45degree shift)
0x5 : CTRL_SHIFTC2_5
T / 16 (22.5degree shift)
End of enumeration elements list.
CTRL_SHIFTC3 : GATEin signal delay amount for DDR
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : CTRL_SHIFTC3_0
0 (0degree shift)
0x1 : CTRL_SHIFTC3_1
T (365degree shift)
0x2 : CTRL_SHIFTC3_2
T / 2 (180degree shift)
0x3 : CTRL_SHIFTC3_3
T / 4 (90degree shift)
0x4 : CTRL_SHIFTC3_4
T / 8 (45degree shift)
0x5 : CTRL_SHIFTC3_5
T / 16 (22.5degree shift)
End of enumeration elements list.
no description available
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL_OFFSETD : This field is for debug purpose
bits : 0 - 7 (8 bit)
access : read-write
CTRL_RESYNC : Active RISIG-EDGE signal
bits : 24 - 24 (1 bit)
access : read-write
UPD_MODE : This field controls "PHY Update" Mode. Initial Value = 0x1
bits : 28 - 28 (1 bit)
access : read-write
no description available
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ctrl_wrlvl0_code : Write Level Slave DLL Code Value for Data_Slice 0 Initial Value = 0x0
bits : 0 - 7 (8 bit)
access : read-write
ctrl_wrlvl1_code : Write Level Slave DLL Code Value for Data_Slice 1 Initial Value = 0x0
bits : 8 - 15 (8 bit)
access : read-write
ctrl_wrlvl2_code : Write Level Slave DLL Code Value for Data_Slice 2 Initial Value = 0x0
bits : 16 - 23 (8 bit)
access : read-write
ctrl_wrlvl3_code : Write Level Slave DLL Code Value for Data_Slice 3 Initial Value = 0x0
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL_WRLVL_RESYNC : Write Level DLL Code Update Enable Initial Value = 0x0
bits : 0 - 0 (1 bit)
access : read-write
no description available
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CA1DESKEWCODE_0 : DeSkew Code for CA[0] Initial Value = 0x0
bits : 0 - 7 (8 bit)
access : read-write
CA1DESKEWCODE_1 : DeSkew Code for CA[1] Initial Value = 0x0
bits : 8 - 15 (8 bit)
access : read-write
CA2DESKEWCODE : DeSkew Code for CA[2] Initial Value = 0x0
bits : 16 - 23 (8 bit)
access : read-write
CA3DESKEWCODE : DeSkew Code for CA[3] Initial Value = 0x0
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDDESKEW_CLEAR : Clear "ctrl_offsetr*" to RdDeSkewCode Initial Value = 1'b0
bits : 13 - 13 (1 bit)
access : read-write
WRDESKEW_CLEAR : Write "ctrl_offsetw*" toWrDeSkewCode Initial Value = 1'b0
bits : 14 - 14 (1 bit)
access : read-write
CA_CAL_MODE : Not used Initial Value = 1'b0
bits : 23 - 23 (1 bit)
access : read-write
GATE_CAL_MODE : When gate_cal_mode = 1, Gate leveling offset value will be used instead of ctrl_shiftc*
bits : 24 - 24 (1 bit)
access : read-write
no description available
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CA4DESKEWCODE : DeSkew Code for CA[4] Initial Value = 0x0
bits : 0 - 7 (8 bit)
access : read-write
CA5DESKEWCODE : DeSkew Code for CA[5] Initial Value = 0x0
bits : 8 - 15 (8 bit)
access : read-write
CA6DESKEWCODE : DeSkew Code for CA[6] Initial Value = 0x0
bits : 16 - 23 (8 bit)
access : read-write
CA7DESKEWCODE : DeSkew Code for CA[7] Initial Value = 0x0
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CA8DESKEWCODE : DeSkew Code for CA[8] Initial Value = 0x0
bits : 0 - 7 (8 bit)
access : read-write
CA9DESKEWCODE : DeSkew Code for CA[9] Initial Value = 0x0
bits : 8 - 15 (8 bit)
access : read-write
CKDESKEWCODE : DeSkew Code for CK Initial Value = 0x0
bits : 16 - 23 (8 bit)
access : read-write
CS0DESKEWCODE : DeSkew Code for CS0 Initial Value = 0x0
bits : 24 - 31 (8 bit)
access : read-write
no description available
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CS1DESKEWCODE : DeSkew Code for CS1 Initial Value = 0x0
bits : 0 - 7 (8 bit)
access : read-write
CKE0DESKEWCODE : DeSkew Code for CKE0 Initial Value = 0x0
bits : 8 - 15 (8 bit)
access : read-write
CKE1DESKEWCODE : DeSkew Code for CKE1 Initial Value = 0x0
bits : 16 - 23 (8 bit)
access : read-write
no description available
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTDESKEWCODE : DeSkew Code for RST Initial Value = 0x0
bits : 0 - 7 (8 bit)
access : read-write
no description available
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAADRDRVRDS : Driver strength for CA[9:0], RAS, CAS,WEN, ODT[1:0], RESET, BANK[2:0]. Initial value = 0x0
bits : 0 - 2 (3 bit)
access : read-write
CACSDRVRDS : Driver strength for CS[1:0] Initial value = 0x0
bits : 3 - 5 (3 bit)
access : read-write
CACKEDRVRDS : Driver strength for CKE[1:0] Initial value = 0x0
bits : 6 - 8 (3 bit)
access : read-write
CACKDRVRDS : Driver strenght for CK Initial value = 0x0. See table above for register setting values.
bits : 9 - 11 (3 bit)
access : read-write
no description available
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL_REF : This field determines the period of time when ctrl_locked is cleared. Initial Value = 4'h8
bits : 1 - 4 (4 bit)
access : read-write
CTRL_DLL_ON : HIGH active start signal to turn on the DLL
bits : 5 - 5 (1 bit)
access : read-write
CTRL_START : This field is used to start DLL locking. Initial Value = 1'b1
bits : 6 - 6 (1 bit)
access : read-write
CTRL_FORCE : This field is used instead of ctrl_lock_value[8:0] found by the DLL only when ctrl_dll_on is LOW, i
bits : 7 - 15 (9 bit)
access : read-write
CTRL_INC : Increase amount of start point Initial Value = 7'h10
bits : 16 - 22 (7 bit)
access : read-write
CTRL_START_POINT : Initial DLL lock start point
bits : 24 - 30 (7 bit)
access : read-write
no description available
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL_LOCKED : DLL stable lock information
bits : 0 - 0 (1 bit)
access : read-write
CTRL_FLOCK : Fine lock information. According to clock jitter, ctrl_flock can be de-asserted.
bits : 1 - 1 (1 bit)
access : read-write
CTRL_CLOCK : Coarse lock information. According to clock jitter, ctrl_clock can be de-asserted.
bits : 2 - 2 (1 bit)
access : read-write
CTRL_LOCK_VALUE : Locked delay line encoding value
bits : 8 - 16 (9 bit)
access : read-write
no description available
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG_MODE : Register mode control to write the information at each data Initial Value = 0x0
bits : 0 - 7 (8 bit)
access : read-write
WRLVL_START : Start Write Leveling signal
bits : 16 - 16 (1 bit)
access : read-write
WL_CAL_MODE : Write Leveling Calibration mode Enable Initial Value = 0x0
bits : 20 - 20 (1 bit)
access : read-write
WL_CAL_START : Start Write Leveling Calibration Initial Value = 0x0
bits : 21 - 21 (1 bit)
access : read-write
WRLVL_RESP : Response after Write Leveling Initial Value = 0x0
bits : 24 - 24 (1 bit)
access : read-write
WL_CAL_RESP : Response after Write Leveling Calibration Initial Value = 0x0
bits : 27 - 27 (1 bit)
access : read-write
no description available
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZQ_AUTO_EN : Auto calibration enable Initial Value = 1'b0
bits : 0 - 0 (1 bit)
access : read-write
ZQ_MANUAL_STR : Manual calibration start Initial Value = 1'b0
bits : 1 - 1 (1 bit)
access : read-write
ZQ_MANUAL_MODE : Manual calibration mode selection Initial Value = 2'b01
bits : 2 - 3 (2 bit)
access : read-write
ZQ_UDT_DLY : ZQ I/O clock enable duration for auto calibration mode. Initial Value = 8'h30
bits : 4 - 11 (8 bit)
access : read-write
ZQ_FORCE_IMPP : Immediate control code for pull-up. Initial Value = 3'h7
bits : 12 - 14 (3 bit)
access : read-write
ZQ_FORCE_IMPN : Immediate control code for pull-down. Initial Value = 3'h0
bits : 15 - 17 (3 bit)
access : read-write
ZQ_CLK_DIV_EN : Clock dividing enable Initial Value = 1'b0
bits : 18 - 18 (1 bit)
access : read-write
ZQ_MODE_NOTERM : Termination disable selection Initial Value = 1'b0
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : ZQ_MODE_NOTERM_0
Termination enable
0x1 : ZQ_MODE_NOTERM_1
Termination disable
End of enumeration elements list.
ZQ_RGDDR3 : Not used Initial Value = 1'b0
bits : 20 - 20 (1 bit)
access : read-write
ZQ_MODE_TERM : On-die-termination (ODT) resistor value selection. Initial Value = 3'h0
bits : 21 - 23 (3 bit)
access : read-write
ZQ_MODE_DDS : Driver strength selection. Initial Value = 3'h7
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : ZQ_MODE_DDS_0
240 ohm Impedance output driver
0x1 : ZQ_MODE_DDS_1
120 ohm Impedance output driver
0x2 : ZQ_MODE_DDS_2
80 ohm Impedance output driver
0x3 : ZQ_MODE_DDS_3
60 ohm Impedance output driver
0x4 : ZQ_MODE_DDS_4
48 ohm Impedance output driver
0x5 : ZQ_MODE_DDS_5
40 ohm Impedance output driver
0x6 : ZQ_MODE_DDS_6
34 ohm Impedance output driver
0x7 : ZQ_MODE_DDS_7
30 ohm Impedance output driver
End of enumeration elements list.
ZQ_CLK_EN : ZQ I/O Clock enable Initial Value = 1'b1
bits : 27 - 27 (1 bit)
access : read-write
no description available
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZQ_DONE : ZQ Calibration is finished. Initial Value = 1'b0
bits : 0 - 0 (1 bit)
access : read-write
ZQ_PENDING : Auto calibration enable status
bits : 1 - 1 (1 bit)
access : read-write
ZQ_ERROR : Calibration fail indication (High: calibration failed)
bits : 2 - 2 (1 bit)
access : read-write
ZQ_NMON : Control code found by auto calibration for pull-down.
bits : 3 - 5 (3 bit)
access : read-write
ZQ_PMON : Control code found by auto calibration for pull-up.
bits : 6 - 8 (3 bit)
access : read-write
no description available
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL_ZQ_CLK_DIV : ZQ Clock (= io_zq_clk) divider setting value
bits : 0 - 15 (16 bit)
access : read-write
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