Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x410 byte (0x0)
mem_usage : registers
protection : not protected
Module Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRSTSD : Software reset for Serial Flash domainPlease keep other fields value when write to SWRSTHD and SWRSTSD These software reset don't reset register setting but only reset internal flip-flops in quadspi controller To remove the reset, need to write 0 to SWRSTHD and SWRSTSD
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SWRSTSD_0
No action
0x1 : SWRSTSD_1
Serial Flash domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects.
End of enumeration elements list.
SWRSTHD : Software reset for AHB domainPlease keep other fields value when write to SWRSTHD and SWRSTSD These software reset don't reset register setting but only reset internal flip-flops in quadspi controller To remove the reset, need to write 0 to SWRSTHD and SWRSTSD
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SWRSTHD_0
No action
0x1 : SWRSTHD_1
AHB domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects.
End of enumeration elements list.
END_CFG : Defines the endianness of the QSPI module.For more details refer to Byte Ordering Endianess
bits : 2 - 3 (2 bit)
access : read-write
DQS_EN : DQS enable: This field is valid for both SDR and DDR mode
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DQS_EN_0
DQS disabled.
0x1 : DQS_EN_1
DQS enabled- When enabled, the incoming data is sampled on both the edges of DQS input when QSPI_MCR[DDR_EN] is set, else, on only one edge when QSPI_MCR[DDR_EN] is 0. The QSPI_SMPR[DDR_SMP] values are ignored.
End of enumeration elements list.
DDR_EN : DDR mode enable:
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DDR_EN_0
2x and 4x clocks are disabled for SDR instructions only
0x1 : DDR_EN_1
2x and 4x clocks are enabled supports both SDR and DDR instruction.
End of enumeration elements list.
CLR_RXF : Clear RX FIFO. Invalidate the RX Buffer.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : CLR_RXF_0
No action.
0x1 : CLR_RXF_1
Read and write pointers of the RX Buffer are reset to 0. QSPI_RBSR[RDBFL] is reset to 0.
End of enumeration elements list.
CLR_TXF : Clear TX FIFO/Buffer. Invalidate the TX Buffer content.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : CLR_TXF_0
No action.
0x1 : CLR_TXF_1
Read and write pointers of the TX Buffer are reset to 0. QSPI_TBSR[TRCTR] is reset to 0.
End of enumeration elements list.
MDIS : Module Disable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : MDIS_0
Enable QuadSPI clocks.
0x1 : MDIS_1
Allow external logic to disable QuadSPI clocks.
End of enumeration elements list.
DQS_LOOPBACK_FROM_PAD : This bit should always be set to '1' when DQS_LOOPBACK_EN is set to '1'
bits : 24 - 24 (1 bit)
access : read-write
DQS_LOOPBACK_EN : Quadspi will output serial data strobe signal which will be loopback from pad to sample input flash serial data
bits : 25 - 25 (1 bit)
access : read-write
DQS_PHASE_EN : This bit controls internal DQS output phase
bits : 26 - 26 (1 bit)
access : read-write
Buffer0 Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTRID : Master ID: The ID of the AHB master associated with BUFFER0
bits : 0 - 3 (4 bit)
access : read-write
ADATSZ : AHB data transfer size: Defines the data transfer size in 8 bytes of an AHB triggered access to serial flash
bits : 8 - 15 (8 bit)
access : read-write
HP_EN : High Priority Enable: When set, the master associated with this buffer is assigned a priority higher than the rest of the masters
bits : 31 - 31 (1 bit)
access : read-write
Serial Flash Address Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFADR : Serial Flash Address. The register content is used as byte address for all following IP Commands.
bits : 0 - 31 (32 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Sampling Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDRSMP : SDR sampling point.
bits : 5 - 6 (2 bit)
access : read-write
DDRSMP : DDR Sampling point
bits : 16 - 18 (3 bit)
access : read-write
RX Buffer Status Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDBFL : RX Buffer Fill Level, indicates how many entries of 4 bytes are still available in the RX Buffer
bits : 8 - 13 (6 bit)
access : read-only
RDCTR : Read Counter, indicates how many entries of 4 bytes have been removed from the RX Buffer
bits : 16 - 31 (16 bit)
access : read-only
RX Buffer Control Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WMRK : RX Buffer Watermark: This field determines when the readout action of the RX Buffer is triggered
bits : 0 - 4 (5 bit)
access : read-write
RXBRD : RX Buffer Readout: This bit specifies the access scheme for the RX Buffer readout.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : RXBRD_0
RX Buffer content is read using the AHB Bus registers QSPI_ARDB0 to QSPI_ARDB31. For details, refer to Exclusive Access to Serial Flash for AHB Commands.
0x1 : RXBRD_1
RX Buffer content is read using the IP Bus registers QSPI_RBDR0 to QSPI_RBDR31.
End of enumeration elements list.
RX Buffer Data Register
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x12B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Buffer1 Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTRID : Master ID: The ID of the AHB master associated with BUFFER1
bits : 0 - 3 (4 bit)
access : read-write
ADATSZ : AHB data transfer size: Defines the data transfer size in 8 bytes of an AHB triggered access to serial flash
bits : 8 - 15 (8 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x1490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
TX Buffer Status Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TRBFL : TX Buffer Fill Level
bits : 8 - 12 (5 bit)
access : read-only
TRCTR : Transmit Counter
bits : 16 - 31 (16 bit)
access : read-only
TX Buffer Data Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data On write access the data is written into the next available entry of the TX Buffer and the QPSI_TBSR[TRBFL] field is updated accordingly
bits : 0 - 31 (32 bit)
access : read-write
Status Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : Module Busy: Asserted when module is currently busy handling a transaction to an external flash device
bits : 0 - 0 (1 bit)
access : read-only
IP_ACC : IP Access: Asserted when transaction currently executed was initiated by IP bus.
bits : 1 - 1 (1 bit)
access : read-only
AHB_ACC : AHB Access: Asserted when the transaction currently executed was initiated by AHB bus.
bits : 2 - 2 (1 bit)
access : read-only
AHBGNT : AHB Command priority Granted: Asserted when another module has been granted priority of AHB Commands against IP Commands
bits : 5 - 5 (1 bit)
access : read-only
AHBTRN : AHB Access Transaction pending: Asserted when there is a pending request on the AHB interface
bits : 6 - 6 (1 bit)
access : read-only
AHB0NE : AHB 0 Buffer Not Empty: Asserted when AHB 0 buffer contains data.
bits : 7 - 7 (1 bit)
access : read-only
AHB1NE : AHB 1 Buffer Not Empty: Asserted when AHB 1 buffer contains data.
bits : 8 - 8 (1 bit)
access : read-only
AHB2NE : AHB 2 Buffer Not Empty: Asserted when AHB 2 buffer contains data.
bits : 9 - 9 (1 bit)
access : read-only
AHB3NE : AHB 3 Buffer Not Empty: Asserted when AHB 3 buffer contains data.
bits : 10 - 10 (1 bit)
access : read-only
AHB0FUL : AHB 0 Buffer Full: Asserted when AHB 0 buffer is full.
bits : 11 - 11 (1 bit)
access : read-only
AHB1FUL : AHB 1 Buffer Full: Asserted when AHB 1 buffer is full.
bits : 12 - 12 (1 bit)
access : read-only
AHB2FUL : AHB 2 Buffer Full: Asserted when AHB 2 buffer is full.
bits : 13 - 13 (1 bit)
access : read-only
AHB3FUL : AHB 3 Buffer Full: Asserted when AHB 3 buffer is full.
bits : 14 - 14 (1 bit)
access : read-only
RXWE : RX Buffer Watermark Exceeded: Asserted when the number of valid entries in the RX Buffer exceeds the number given in the QSPI_RBCT[WMRK] field
bits : 16 - 16 (1 bit)
access : read-only
RXFULL : RX Buffer Full: Asserted when the RX Buffer is full, i
bits : 19 - 19 (1 bit)
access : read-only
RXDMA : RX Buffer DMA: Asserted when RX Buffer read out via DMA is active i.e DMA is requested or running.
bits : 23 - 23 (1 bit)
access : read-only
TXEDA : Tx Buffer Enough Data Available
bits : 24 - 24 (1 bit)
access : read-only
TXFULL : TX Buffer Full: Asserted when no more data can be stored.
bits : 27 - 27 (1 bit)
access : read-only
DLPSMP : Data learning is not implemented on this chip
bits : 29 - 31 (3 bit)
access : read-only
Look-up Table register
address_offset : 0x15E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Flag Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFF : IP Command Transaction Finished Flag: Set when the QuadSPI module has finished a running IP Command
bits : 0 - 0 (1 bit)
access : read-write
IPGEF : IP Command Trigger during AHB Grant Error Flag: Set when the following condition occurs: A write access occurs to the QSPI_IPCR[SEQID] field and the QSPI_SR[AHBGNT] bit is set
bits : 4 - 4 (1 bit)
access : read-write
IPIEF : IP Command Trigger could not be executed Error Flag
bits : 6 - 6 (1 bit)
access : read-write
IPAEF : IP Command Trigger during AHB Access Error Flag
bits : 7 - 7 (1 bit)
access : read-write
IUEF : IP Command Usage Error Flag: Set when in parallel flash mode the execution of an IP Command is started and the sequence pointed to by the sequence ID contains a WRITE or a WRITE_DDR command
bits : 11 - 11 (1 bit)
access : read-write
ABOF : AHB Buffer Overflow Flag: Set when the size of the AHB access exceeds the size of the AHB buffer
bits : 12 - 12 (1 bit)
access : read-write
ABSEF : AHB Sequence Error Flag: Set when the execution of an AHB Command is started with an WRITE or WRITE_DDR Command in the sequence pointed to by the QSPI_BUFxCR QSPI_BUFxCR implies anyone of QSPI_BUF0CR/QSPI_BUF1CR/QSPI_BUF2CR/QSPI_BUF3CR register Communication with the serial flash device is terminated before the execution of WRITE/WRITE_DDR command by the QuadSPI module
bits : 15 - 15 (1 bit)
access : read-write
RBDF : RX Buffer Drain Flag: Will be set if the QuadSPI_SR[RXWE] status bit is asserted
bits : 16 - 16 (1 bit)
access : read-write
RBOF : RX Buffer Overflow Flag: Set when not all the data read from the serial flash device could be pushed into the RX Buffer
bits : 17 - 17 (1 bit)
access : read-write
ILLINE : Illegal Instruction Error Flag: Set when an illegal instruction is encountered by the controller in any of the sequences
bits : 23 - 23 (1 bit)
access : read-write
TBUF : TX Buffer Underrun Flag: Set when the module tried to pull data although TX Buffer was emptyor the buffer contains less than 128bits of data
bits : 26 - 26 (1 bit)
access : read-write
TBFF : TX Buffer Fill Flag: Before writing to the TX buffer, this bit should be cleared
bits : 27 - 27 (1 bit)
access : read-write
DLPFF : Data learning is not implemented on this chip
bits : 31 - 31 (1 bit)
access : read-write
Interrupt and DMA Request Select and Enable Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transaction Finished Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TFIE_0
No TFF interrupt will be generated
0x1 : TFIE_1
TFF interrupt will be generated
End of enumeration elements list.
IPGEIE : IP Command Trigger during AHB Grant Error Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : IPGEIE_0
No IPGEF interrupt will be generated
0x1 : IPGEIE_1
IPGEF interrupt will be generated
End of enumeration elements list.
IPIEIE : IP Command Trigger during IP Access Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : IPIEIE_0
No IPIEF interrupt will be generated
End of enumeration elements list.
IPAEIE : IP Command Trigger during AHB Access Error Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : IPAEIE_0
No IPAEF interrupt will be generated
0x1 : IPAEIE_1
IPAEF interrupt will be generated
End of enumeration elements list.
IUEIE : IP Command Usage Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : IUEIE_0
No IUEF interrupt will be generated
0x1 : IUEIE_1
IUEF interrupt will be generated
End of enumeration elements list.
ABOIE : AHB Buffer Overflow Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : ABOIE_0
No ABOF interrupt will be generated
0x1 : ABOIE_1
ABOF interrupt will be generated
End of enumeration elements list.
ABSEIE : AHB Sequence Error Interrupt Enable: Triggered by ABSEF flags of QSPI_FR
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ABSEIE_0
No ABSEF interrupt will be generated
0x1 : ABSEIE_1
ABSEF interrupt will be generated
End of enumeration elements list.
RBDIE : RX Buffer Drain Interrupt Enable: Enables generation of IRQ requests for RX Buffer Drain
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : RBDIE_0
No RBDF interrupt will be generated
0x1 : RBDIE_1
RBDF Interrupt will be generated
End of enumeration elements list.
RBOIE : RX Buffer Overflow Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : RBOIE_0
No RBOF interrupt will be generated
0x1 : RBOIE_1
RBOF interrupt will be generated
End of enumeration elements list.
RBDDE : RX Buffer Drain DMA Enable: Enables generation of DMA requests for RX Buffer Drain
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : RBDDE_0
No DMA request will be generated
0x1 : RBDDE_1
DMA request will be generated
End of enumeration elements list.
ILLINIE : Illegal Instruction Error Interrupt Enable. Triggered by ILLINE flag in QSPI_FR
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : ILLINIE_0
No ILLINE interrupt will be generated
0x1 : ILLINIE_1
ILLINE interrupt will be generated
End of enumeration elements list.
TBUIE : TX Buffer Underrun Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : TBUIE_0
No TBUF interrupt will be generated
0x1 : TBUIE_1
TBUF interrupt will be generated
End of enumeration elements list.
TBFIE : TX Buffer Fill Interrupt Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : TBFIE_0
No TBFF interrupt will be generated
0x1 : TBFIE_1
TBFF interrupt will be generated
End of enumeration elements list.
DLPFIE : Data learning is not implemented on this chip
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DLPFIE_0
No DLPFF interrupt will be generated
0x1 : DLPFIE_1
DLPFF interrupt will be generated
End of enumeration elements list.
Sequence Suspend Status Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUSPND : When set, it signifies that a sequence is in suspended state
bits : 0 - 0 (1 bit)
access : read-only
SPDBUF : Suspended Buffer: Provides the suspended buffer number. Valid only when SUSPND is set to 1'b1
bits : 6 - 7 (2 bit)
access : read-only
DATLFT : Data left: Provides information about the amount of data left to be read in the suspended sequence
bits : 9 - 15 (7 bit)
access : read-only
RX Buffer Data Register
address_offset : 0x16B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Sequence Pointer Clear Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BFPTRC : Buffer Pointer Clear: 1: Clears the sequence pointer for AHB accesses as defined in QuadSPI_BFGENCR
bits : 0 - 0 (1 bit)
access : read-write
IPPTRC : IP Pointer Clear: 1: Clears the sequence pointer for IP accesses as defined in QuadSPI_IPCR
bits : 8 - 8 (1 bit)
access : read-write
Buffer2 Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTRID : Master ID: The ID of the AHB master associated with BUFFER2
bits : 0 - 3 (4 bit)
access : read-write
ADATSZ : AHB data transfer size: Defines the data transfer size in 8 Bytes of an AHB triggered access to serial flash
bits : 8 - 15 (8 bit)
access : read-write
Serial Flash A1 Top Address
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPADA1 : Top address for Serial Flash A1. In effect, TPADxx is the first location of the next memory.
bits : 10 - 31 (22 bit)
access : read-write
Serial Flash A2 Top Address
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPADA2 : Top address for Serial Flash A2. In effect, TPxxAD is the first location of the next memory.
bits : 10 - 31 (22 bit)
access : read-write
Serial Flash B1Top Address
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPADB1 : Top address for Serial Flash B1.In effect, TPxxAD is the first location of the next memory.
bits : 10 - 31 (22 bit)
access : read-write
Serial Flash B2Top Address
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPADB2 : Top address for Serial Flash B2. In effect, TPxxAD is the first location of the next memory.
bits : 10 - 31 (22 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x18DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x1914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x1B08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Buffer3 Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTRID : Master ID: The ID of the AHB master associated with BUFFER3
bits : 0 - 3 (4 bit)
access : read-write
ADATSZ : AHB data transfer size: Defines the data transfer size in 8 Bytes of an AHB triggered access to serial flash
bits : 8 - 15 (8 bit)
access : read-write
ALLMST : All master enable: When set, buffer3 acts as an all-master buffer
bits : 31 - 31 (1 bit)
access : read-write
Look-up Table register
address_offset : 0x1C48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x1D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x1F6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x1F80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Buffer Generic Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQID : Points to a sequence in the Look-up-table
bits : 12 - 15 (4 bit)
access : read-write
PAR_EN : When set, a transaction to two serial flash devices is triggered in parallel mode
bits : 16 - 16 (1 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x21A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x22BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x23E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x25FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x2620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x2864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x2940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x2AAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x2C88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x2CF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x2F48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x2FD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Buffer0 Top Index Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPINDX0 : Top index of buffer 0.
bits : 3 - 31 (29 bit)
access : read-write
LUT Key Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : The key to lock or unlock the LUT. The KEY is 0x5AF05AF0. The read value is always 0x5AF05AF0
bits : 0 - 31 (32 bit)
access : read-write
LUT Lock Configuration Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : Locks the LUT when the following condition is met: This register is written just after the LUTKEYLUT Key Register The LUT key register was written with 0x5AF05AF0 key
bits : 0 - 0 (1 bit)
access : read-write
UNLOCK : Unlocks the LUT when the following two conditions are met: 1
bits : 1 - 1 (1 bit)
access : read-write
Look-up Table register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x319C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x3324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x33F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Buffer1 Top Index Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPINDX1 : Top index of buffer 1.
bits : 3 - 31 (29 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x3650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x3678 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Buffer2 Top Index Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPINDX2 : Top index of buffer 2.
bits : 3 - 31 (29 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x38B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x39D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x3B14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x3D2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x3D7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x3FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x408C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x4258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x43F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x44CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x4744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x4758 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x49C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x4AC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x4E34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x51A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x5520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x589C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x5C1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x5FA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x6328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x66B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x6A44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x6DD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x7170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x750C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x78AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x7C50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x7FF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
IP Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDATSZ : IP data transfer size: Defines the data transfer size in bytes of the IP command.
bits : 0 - 15 (16 bit)
access : read-write
PAR_EN : When set, a transaction to two serial flash devices is triggered in parallel mode
bits : 16 - 16 (1 bit)
access : read-write
SEQID : Points to a sequence in the Look-up-table
bits : 24 - 27 (4 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0x83A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x8754 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x8B08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x8EC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x927C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x94C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x963C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x9A00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x9DC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0xA194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xA564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xA938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xAD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xB0EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xB4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xB8B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xBC98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Flash Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCSS : Serial flash CS setup time in terms of serial flash clock cycles
bits : 0 - 3 (4 bit)
access : read-write
TCSH : Serial flash CS hold time in terms of serial flash clock cycles
bits : 8 - 11 (4 bit)
access : read-write
TDH : Serial flash Data In hold time: This helps in meeting the Data In Hold time requirement of a Flash
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : TDH_0
Data aligned with the posedge of Internal reference clock of QuadSPI
0x1 : TDH_1
Data aligned with 2x serial flash half clock
End of enumeration elements list.
Look-up Table register
address_offset : 0xC084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0xC474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xC6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xC868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xCC60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xD05C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xD45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xD860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xDC68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xE074 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-write
Look-up Table register
address_offset : 0xF90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : PAD0_0
1 Pad
0x1 : PAD0_1
2 Pads
0x2 : PAD0_2
4 Pads
0x3 : PAD0_3
NA
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : PAD1_0
1 Pad
0x1 : PAD1_1
2 Pads
0x2 : PAD1_2
4 Pads
0x3 : PAD1_3
NA
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
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