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USB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1E0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ID

HWTXBUF

CAPLENGTH

HCIVERSION

HCSPARAMS

HCCPARAMS

DCIVERSION

DCCPARAMS

HWRXBUF

USBCMD

USBSTS

USBINTR

FRINDEX

DEVICEADDR

PERIODICLISTBASE

ASYNCLISTADDR

ENDPTLISTADDR

BURSTSIZE

TXFILLTUNING

ENDPTNAK

ENDPTNAKEN

CONFIGFLAG

PORTSC1

OTGSC

USBMODE

ENDPTSETUPSTAT

ENDPTPRIME

ENDPTFLUSH

ENDPTSTAT

ENDPTCOMPLETE

ENDPTCTRL0

ENDPTCTRL1

ENDPTCTRL2

ENDPTCTRL3

ENDPTCTRL4

ENDPTCTRL5

ENDPTCTRL6

ENDPTCTRL7

HWGENERAL

HWHOST

GPTIMER0LD

GPTIMER0CTRL

GPTIMER1LD

GPTIMER1CTRL

SBUSCFG

HWDEVICE


ID

Identification register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ID ID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID NID REVISION

ID : Configuration number
bits : 0 - 5 (6 bit)
access : read-only

NID : Complement version of ID
bits : 8 - 13 (6 bit)
access : read-only

REVISION : Revision number of the controller core.
bits : 16 - 23 (8 bit)
access : read-only


HWTXBUF

TX Buffer Hardware Parameters
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWTXBUF HWTXBUF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXBURST TXCHANADD

TXBURST : Default burst size for memory to TX buffer transfer
bits : 0 - 7 (8 bit)
access : read-only

TXCHANADD : TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes
bits : 16 - 23 (8 bit)
access : read-only


CAPLENGTH

Capability Registers Length
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAPLENGTH CAPLENGTH read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CAPLENGTH

CAPLENGTH : These bits are used as an offset to add to register base to find the beginning of the Operational Register
bits : 0 - 7 (8 bit)
access : read-only


HCIVERSION

Host Controller Interface Version
address_offset : 0x102 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCIVERSION HCIVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCIVERSION

HCIVERSION : Host Controller Interface Version Number Default value is '10h', which means EHCI rev1.0.
bits : 0 - 15 (16 bit)
access : read-only


HCSPARAMS

Host Controller Structural Parameters
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCSPARAMS HCSPARAMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N_PORTS PPC N_PCC N_CC PI N_PTT N_TT

N_PORTS : Number of downstream ports
bits : 0 - 3 (4 bit)
access : read-only

PPC : Port Power Control This field indicates whether the host controller implementation includes port power control
bits : 4 - 4 (1 bit)
access : read-only

N_PCC : Number of Ports per Companion Controller This field indicates the number of ports supported per internal Companion Controller
bits : 8 - 11 (4 bit)
access : read-only

N_CC : Number of Companion Controller (N_CC)
bits : 12 - 15 (4 bit)
access : read-only

Enumeration:

0 : N_CC_0

There is no internal Companion Controller and port-ownership hand-off is not supported.

0x1 : N_CC_1

There are internal companion controller(s) and port-ownership hand-offs is supported.

End of enumeration elements list.

PI : Port Indicators (P INDICATOR) This bit indicates whether the ports support port indicator control
bits : 16 - 16 (1 bit)
access : read-only

N_PTT : Number of Ports per Transaction Translator (N_PTT)
bits : 20 - 23 (4 bit)
access : read-only

N_TT : Number of Transaction Translators (N_TT)
bits : 24 - 27 (4 bit)
access : read-only


HCCPARAMS

Host Controller Capability Parameters
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCCPARAMS HCCPARAMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC PFL ASP IST EECP

ADC : 64-bit Addressing Capability This bit is set '0b' in all controller core, no 64-bit addressing capability is supported
bits : 0 - 0 (1 bit)
access : read-only

PFL : Programmable Frame List Flag If this bit is set to zero, then the system software must use a frame list length of 1024 elements with this host controller
bits : 1 - 1 (1 bit)
access : read-only

ASP : Asynchronous Schedule Park Capability If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule
bits : 2 - 2 (1 bit)
access : read-only

IST : Isochronous Scheduling Threshold
bits : 4 - 7 (4 bit)
access : read-only

EECP : EHCI Extended Capabilities Pointer
bits : 8 - 15 (8 bit)
access : read-only


DCIVERSION

Device Controller Interface Version
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCIVERSION DCIVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCIVERSION

DCIVERSION : Device Controller Interface Version Number Default value is '01h', which means rev0.1.
bits : 0 - 15 (16 bit)
access : read-only


DCCPARAMS

Device Controller Capability Parameters
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCCPARAMS DCCPARAMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEN DC HC

DEN : Device Endpoint Number This field indicates the number of endpoints built into the device controller
bits : 0 - 4 (5 bit)
access : read-only

DC : Device Capable When this bit is 1, this controller is capable of operating as a USB 2.0 device.
bits : 7 - 7 (1 bit)
access : read-only

HC : Host Capable When this bit is 1, this controller is capable of operating as an EHCI compatible USB 2
bits : 8 - 8 (1 bit)
access : read-only


HWRXBUF

RX Buffer Hardware Parameters
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWRXBUF HWRXBUF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXBURST RXADD

RXBURST : Default burst size for memory to RX buffer transfer
bits : 0 - 7 (8 bit)
access : read-only

RXADD : Buffer total size for all receive endpoints is (2^RXADD)
bits : 8 - 15 (8 bit)
access : read-only


USBCMD

USB Command Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBCMD USBCMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RS RST FS_1 PSE ASE IAA ASP ASPE ATDTW SUTW FS_2 ITC

RS : Run/Stop (RS) - Read/Write
bits : 0 - 0 (1 bit)
access : read-write

RST : Controller Reset (RESET) - Read/Write
bits : 1 - 1 (1 bit)
access : read-write

FS_1 : See description at bit 15
bits : 2 - 3 (2 bit)
access : read-write

PSE : Periodic Schedule Enable- Read/Write
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PSE_0

Do not process the Periodic Schedule

0x1 : PSE_1

Use the PERIODICLISTBASE register to access the Periodic Schedule.

End of enumeration elements list.

ASE : Asynchronous Schedule Enable - Read/Write
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ASE_0

Do not process the Asynchronous Schedule.

0x1 : ASE_1

Use the ASYNCLISTADDR register to access the Asynchronous Schedule.

End of enumeration elements list.

IAA : Interrupt on Async Advance Doorbell - Read/Write
bits : 6 - 6 (1 bit)
access : read-write

ASP : Asynchronous Schedule Park Mode Count - Read/Write
bits : 8 - 9 (2 bit)
access : read-write

ASPE : Asynchronous Schedule Park Mode Enable - Read/Write
bits : 11 - 11 (1 bit)
access : read-write

ATDTW : Add dTD TripWire - Read/Write
bits : 12 - 12 (1 bit)
access : read-write

SUTW : Setup TripWire - Read/Write
bits : 13 - 13 (1 bit)
access : read-write

FS_2 : See also bits 3-2 Frame List Size - (Read/Write or Read Only)
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : FS_2_0

1024 elements (4096 bytes) Default value

0x1 : FS_2_1

512 elements (2048 bytes)

End of enumeration elements list.

ITC : Interrupt Threshold Control -Read/Write
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0 : ITC_0

Immediate (no threshold)

0x1 : ITC_1

1 micro-frame

0x2 : ITC_2

2 micro-frames

0x4 : ITC_4

4 micro-frames

0x8 : ITC_8

8 micro-frames

0x10 : ITC_16

16 micro-frames

0x20 : ITC_32

32 micro-frames

0x40 : ITC_64

64 micro-frames

End of enumeration elements list.


USBSTS

USB Status Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBSTS USBSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UI UEI PCI FRI SEI AAI URI SRI SLI ULPII HCH RCL PS AS NAKI TI0 TI1

UI : USB Interrupt (USBINT) - R/WC
bits : 0 - 0 (1 bit)
access : read-write

UEI : USB Error Interrupt (USBERRINT) - R/WC
bits : 1 - 1 (1 bit)
access : read-write

PCI : Port Change Detect - R/WC
bits : 2 - 2 (1 bit)
access : read-write

FRI : Frame List Rollover - R/WC
bits : 3 - 3 (1 bit)
access : read-write

SEI : System Error- R/WC
bits : 4 - 4 (1 bit)
access : read-write

AAI : Interrupt on Async Advance - R/WC
bits : 5 - 5 (1 bit)
access : read-write

URI : USB Reset Received - R/WC
bits : 6 - 6 (1 bit)
access : read-write

SRI : SOF Received - R/WC
bits : 7 - 7 (1 bit)
access : read-write

SLI : DCSuspend - R/WC
bits : 8 - 8 (1 bit)
access : read-write

ULPII : ULPI Interrupt - R/WC
bits : 10 - 10 (1 bit)
access : read-write

HCH : HCHaIted - Read Only
bits : 12 - 12 (1 bit)
access : read-write

RCL : Reclamation - Read Only
bits : 13 - 13 (1 bit)
access : read-write

PS : Periodic Schedule Status - Read Only
bits : 14 - 14 (1 bit)
access : read-write

AS : Asynchronous Schedule Status - Read Only
bits : 15 - 15 (1 bit)
access : read-write

NAKI : NAK Interrupt Bit--RO
bits : 16 - 16 (1 bit)
access : read-only

TI0 : General Purpose Timer Interrupt 0(GPTINT0)--R/WC
bits : 24 - 24 (1 bit)
access : read-write

TI1 : General Purpose Timer Interrupt 1(GPTINT1)--R/WC
bits : 25 - 25 (1 bit)
access : read-write


USBINTR

Interrupt Enable Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBINTR USBINTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UE UEE PCE FRE SEE AAE URE SRE SLE ULPIE NAKE UAIE UPIE TIE0 TIE1

UE : USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt
bits : 0 - 0 (1 bit)
access : read-write

UEE : USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt
bits : 1 - 1 (1 bit)
access : read-write

PCE : Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt
bits : 2 - 2 (1 bit)
access : read-write

FRE : Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt
bits : 3 - 3 (1 bit)
access : read-write

SEE : System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt
bits : 4 - 4 (1 bit)
access : read-write

AAE : Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt
bits : 5 - 5 (1 bit)
access : read-write

URE : USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt
bits : 6 - 6 (1 bit)
access : read-write

SRE : SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt
bits : 7 - 7 (1 bit)
access : read-write

SLE : Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt
bits : 8 - 8 (1 bit)
access : read-write

ULPIE : ULPI Interrupt Enable When this bit is one and the UPLII bit in n_USBSTS register is a one the controller will issue an interrupt
bits : 10 - 10 (1 bit)
access : read-write

NAKE : NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt
bits : 16 - 16 (1 bit)
access : read-write

UAIE : USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold
bits : 18 - 18 (1 bit)
access : read-write

UPIE : USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold
bits : 19 - 19 (1 bit)
access : read-write

TIE0 : General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt
bits : 24 - 24 (1 bit)
access : read-write

TIE1 : General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt
bits : 25 - 25 (1 bit)
access : read-write


FRINDEX

USB Frame Index
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRINDEX FRINDEX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRINDEX

FRINDEX : Frame Index
bits : 0 - 13 (14 bit)
access : read-write

Enumeration:

0 : FRINDEX_0

(1024) 12

0x1 : FRINDEX_1

(512) 11

0x2 : FRINDEX_2

(256) 10

0x3 : FRINDEX_3

(128) 9

0x4 : FRINDEX_4

(64) 8

0x5 : FRINDEX_5

(32) 7

0x6 : FRINDEX_6

(16) 6

0x7 : FRINDEX_7

(8) 5

End of enumeration elements list.


DEVICEADDR

Device Address
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DEVICEADDR_PERIODICLISTBASE
reset_Mask : 0x0

DEVICEADDR DEVICEADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBADRA USBADR

USBADRA : Device Address Advance
bits : 24 - 24 (1 bit)
access : read-write

USBADR : Device Address. These bits correspond to the USB device address
bits : 25 - 31 (7 bit)
access : read-write


PERIODICLISTBASE

Frame List Base Address
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DEVICEADDR_PERIODICLISTBASE
reset_Mask : 0x0

PERIODICLISTBASE PERIODICLISTBASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASEADR

BASEADR : Base Address (Low)
bits : 12 - 31 (20 bit)
access : read-write


ASYNCLISTADDR

Next Asynch. Address
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : ASYNCLISTADDR_ENDPTLISTADDR
reset_Mask : 0x0

ASYNCLISTADDR ASYNCLISTADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASYBASE

ASYBASE : Link Pointer Low (LPL)
bits : 5 - 31 (27 bit)
access : read-write


ENDPTLISTADDR

Endpoint List Address
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : ASYNCLISTADDR_ENDPTLISTADDR
reset_Mask : 0x0

ENDPTLISTADDR ENDPTLISTADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPBASE

EPBASE : Endpoint List Pointer(Low)
bits : 11 - 31 (21 bit)
access : read-write


BURSTSIZE

Programmable Burst Size
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BURSTSIZE BURSTSIZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPBURST TXPBURST

RXPBURST : Programmable RX Burst Size
bits : 0 - 7 (8 bit)
access : read-write

TXPBURST : Programmable TX Burst Size
bits : 8 - 16 (9 bit)
access : read-write


TXFILLTUNING

TX FIFO Fill Tuning
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFILLTUNING TXFILLTUNING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXSCHOH TXSCHHEALTH TXFIFOTHRES

TXSCHOH : Scheduler Overhead
bits : 0 - 7 (8 bit)
access : read-write

TXSCHHEALTH : Scheduler Health Counter
bits : 8 - 12 (5 bit)
access : read-write

TXFIFOTHRES : FIFO Burst Threshold
bits : 16 - 21 (6 bit)
access : read-write


ENDPTNAK

Endpoint NAK
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTNAK ENDPTNAK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPRN EPTN

EPRN : RX Endpoint NAK - R/WC
bits : 0 - 7 (8 bit)
access : read-write

EPTN : TX Endpoint NAK - R/WC
bits : 16 - 23 (8 bit)
access : read-write


ENDPTNAKEN

Endpoint NAK Enable
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTNAKEN ENDPTNAKEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPRNE EPTNE

EPRNE : RX Endpoint NAK Enable - R/W
bits : 0 - 7 (8 bit)
access : read-write

EPTNE : TX Endpoint NAK Enable - R/W
bits : 16 - 23 (8 bit)
access : read-write


CONFIGFLAG

Configure Flag Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CONFIGFLAG CONFIGFLAG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CF

CF : Configure Flag Host software sets this bit as the last action in its process of configuring the Host Controller
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : CF_0

Port routing control logic default-routes each port to an implementation dependent classic host controller.

0x1 : CF_1

Port routing control logic default-routes all ports to this host controller.

End of enumeration elements list.


PORTSC1

Port Status and Control
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PORTSC1 PORTSC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCS CSC PE PEC OCA OCC FPR SUSP PR HSP LS PP PO PIC PTC WKCN WKDC WKOC PHCD PFSC PTS_2 PSPD PTW STS PTS_1

CCS : Current Connect Status-Read Only
bits : 0 - 0 (1 bit)
access : read-only

CSC : Connect Status Change-R/WC
bits : 1 - 1 (1 bit)
access : read-write

PE : Port Enabled/Disabled-Read/Write
bits : 2 - 2 (1 bit)
access : read-write

PEC : Port Enable/Disable Change-R/WC
bits : 3 - 3 (1 bit)
access : read-write

OCA : Over-current Active-Read Only
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

0 : OCA_0

This port does not have an over-current condition.

0x1 : OCA_1

This port currently has an over-current condition

End of enumeration elements list.

OCC : Over-current Change-R/WC
bits : 5 - 5 (1 bit)
access : read-write

FPR : Force Port Resume -Read/Write
bits : 6 - 6 (1 bit)
access : read-write

SUSP : Suspend - Read/Write or Read Only
bits : 7 - 7 (1 bit)
access : read-write

PR : Port Reset - Read/Write or Read Only
bits : 8 - 8 (1 bit)
access : read-write

HSP : High-Speed Port - Read Only
bits : 9 - 9 (1 bit)
access : read-only

LS : Line Status-Read Only
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

0 : LS_0

SE0

0x1 : LS_1

K-state

0x2 : LS_2

J-state

0x3 : LS_3

Undefined

End of enumeration elements list.

PP : Port Power (PP)-Read/Write or Read Only
bits : 12 - 12 (1 bit)
access : read-write

PO : Port Owner-Read/Write
bits : 13 - 13 (1 bit)
access : read-write

PIC : Port Indicator Control - Read/Write
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : PIC_0

Port indicators are off

0x1 : PIC_1

Amber

0x2 : PIC_2

Green

0x3 : PIC_3

Undefined

End of enumeration elements list.

PTC : Port Test Control - Read/Write
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : PTC_0

TEST_MODE_DISABLE

0x1 : PTC_1

J_STATE

0x2 : PTC_2

K_STATE

0x3 : PTC_3

SE0 (host) / NAK (device)

0x4 : PTC_4

Packet

0x5 : PTC_5

FORCE_ENABLE_HS

0x6 : PTC_6

FORCE_ENABLE_FS

0x7 : PTC_7

FORCE_ENABLE_LS

End of enumeration elements list.

WKCN : Wake on Connect Enable (WKCNNT_E) - Read/Write
bits : 20 - 20 (1 bit)
access : read-write

WKDC : Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write
bits : 21 - 21 (1 bit)
access : read-write

WKOC : Wake on Over-current Enable (WKOC_E) - Read/Write
bits : 22 - 22 (1 bit)
access : read-write

PHCD : PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : PHCD_0

Enable PHY clock

0x1 : PHCD_1

Disable PHY clock

End of enumeration elements list.

PFSC : Port Force Full Speed Connect - Read/Write
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : PFSC_0

Normal operation

0x1 : PFSC_1

Forced to full speed

End of enumeration elements list.

PTS_2 : See description at bits 31-30
bits : 25 - 25 (1 bit)
access : read-write

PSPD : Port Speed - Read Only. This register field indicates the speed at which the port is operating.
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : PSPD_0

Full Speed

0x1 : PSPD_1

Low Speed

0x2 : PSPD_2

High Speed

0x3 : PSPD_3

Undefined

End of enumeration elements list.

PTW : Parallel Transceiver Width This bit has no effect if serial interface engine is used
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : PTW_0

Select the 8-bit UTMI interface [60MHz]

0x1 : PTW_1

Select the 16-bit UTMI interface [30MHz]

End of enumeration elements list.

STS : Serial Transceiver Select - Read Only Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals
bits : 29 - 29 (1 bit)
access : read-write

PTS_1 : Bit field {bit25, bit31, bit30}: "000b" UTMI/UTMI+ "001b" Reserved "010b" ULPI "011b" Serial/USB 1
bits : 30 - 31 (2 bit)
access : read-write


OTGSC

On-The-Go Status and control
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTGSC OTGSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VD VC OT DP IDPU ID AVV ASV BSV BSE TOG_1MS DPS IDIS AVVIS ASVIS BSVIS BSEIS STATUS_1MS DPIS IDIE AVVIE ASVIE BSVIE BSEIE EN_1MS DPIE

VD : VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor.
bits : 0 - 0 (1 bit)
access : read-write

VC : VBUS Charge - Read/Write
bits : 1 - 1 (1 bit)
access : read-write

OT : OTG Termination - Read/Write
bits : 3 - 3 (1 bit)
access : read-write

DP : Data Pulsing - Read/Write
bits : 4 - 4 (1 bit)
access : read-write

IDPU : ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]
bits : 5 - 5 (1 bit)
access : read-write

ID : USB ID - Read Only. 0 = A device, 1 = B device
bits : 8 - 8 (1 bit)
access : read-only

AVV : A VBus Valid - Read Only. Indicates VBus is above the A VBus valid threshold.
bits : 9 - 9 (1 bit)
access : read-only

ASV : A Session Valid - Read Only. Indicates VBus is above the A session valid threshold.
bits : 10 - 10 (1 bit)
access : read-only

BSV : B Session Valid - Read Only. Indicates VBus is above the B session valid threshold.
bits : 11 - 11 (1 bit)
access : read-only

BSE : B Session End - Read Only. Indicates VBus is below the B session end threshold.
bits : 12 - 12 (1 bit)
access : read-only

TOG_1MS : 1 millisecond timer toggle - Read Only. This bit toggles once per millisecond.
bits : 13 - 13 (1 bit)
access : read-only

DPS : Data Bus Pulsing Status - Read Only
bits : 14 - 14 (1 bit)
access : read-only

IDIS : USB ID Interrupt Status - Read/Write
bits : 16 - 16 (1 bit)
access : read-write

AVVIS : A VBus Valid Interrupt Status - Read/Write to Clear
bits : 17 - 17 (1 bit)
access : read-write

ASVIS : A Session Valid Interrupt Status - Read/Write to Clear
bits : 18 - 18 (1 bit)
access : read-write

BSVIS : B Session Valid Interrupt Status - Read/Write to Clear
bits : 19 - 19 (1 bit)
access : read-write

BSEIS : B Session End Interrupt Status - Read/Write to Clear
bits : 20 - 20 (1 bit)
access : read-write

STATUS_1MS : 1 millisecond timer Interrupt Status - Read/Write to Clear
bits : 21 - 21 (1 bit)
access : read-write

DPIS : Data Pulse Interrupt Status - Read/Write to Clear
bits : 22 - 22 (1 bit)
access : read-write

IDIE : USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt.
bits : 24 - 24 (1 bit)
access : read-write

AVVIE : A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt.
bits : 25 - 25 (1 bit)
access : read-write

ASVIE : A Session Valid Interrupt Enable - Read/Write
bits : 26 - 26 (1 bit)
access : read-write

BSVIE : B Session Valid Interrupt Enable - Read/Write
bits : 27 - 27 (1 bit)
access : read-write

BSEIE : B Session End Interrupt Enable - Read/Write. Setting this bit enables the B session end interrupt.
bits : 28 - 28 (1 bit)
access : read-write

EN_1MS : 1 millisecond timer Interrupt Enable - Read/Write
bits : 29 - 29 (1 bit)
access : read-write

DPIE : Data Pulse Interrupt Enable
bits : 30 - 30 (1 bit)
access : read-write


USBMODE

USB Device Mode
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBMODE USBMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM ES SLOM SDIS

CM : Controller Mode - R/WO
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : CM_0

Idle [Default for combination host/device]

0x2 : CM_2

Device Controller [Default for device only controller]

0x3 : CM_3

Host Controller [Default for host only controller]

End of enumeration elements list.

ES : Endian Select - Read/Write
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : ES_0

Little Endian [Default]

0x1 : ES_1

Big Endian

End of enumeration elements list.

SLOM : Setup Lockout Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SLOM_0

Setup Lockouts On (default);

0x1 : SLOM_1

Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register .

End of enumeration elements list.

SDIS : Stream Disable Mode
bits : 4 - 4 (1 bit)
access : read-write


ENDPTSETUPSTAT

Endpoint Setup Status
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTSETUPSTAT ENDPTSETUPSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENDPTSETUPSTAT

ENDPTSETUPSTAT : Setup Endpoint Status
bits : 0 - 15 (16 bit)
access : read-write


ENDPTPRIME

Endpoint Prime
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTPRIME ENDPTPRIME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERB PETB

PERB : Prime Endpoint Receive Buffer - R/WS
bits : 0 - 7 (8 bit)
access : read-write

PETB : Prime Endpoint Transmit Buffer - R/WS
bits : 16 - 23 (8 bit)
access : read-write


ENDPTFLUSH

Endpoint Flush
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTFLUSH ENDPTFLUSH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FERB FETB

FERB : Flush Endpoint Receive Buffer - R/WS
bits : 0 - 7 (8 bit)
access : read-write

FETB : Flush Endpoint Transmit Buffer - R/WS
bits : 16 - 23 (8 bit)
access : read-write


ENDPTSTAT

Endpoint Status
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENDPTSTAT ENDPTSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERBR ETBR

ERBR : Endpoint Receive Buffer Ready -- Read Only
bits : 0 - 7 (8 bit)
access : read-only

ETBR : Endpoint Transmit Buffer Ready -- Read Only
bits : 16 - 23 (8 bit)
access : read-only


ENDPTCOMPLETE

Endpoint Complete
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTCOMPLETE ENDPTCOMPLETE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERCE ETCE

ERCE : Endpoint Receive Complete Event - RW/C
bits : 0 - 7 (8 bit)
access : read-write

ETCE : Endpoint Transmit Complete Event - R/WC
bits : 16 - 23 (8 bit)
access : read-write


ENDPTCTRL0

Endpoint Control0
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTCTRL0 ENDPTCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RXT RXE TXS TXT TXE

RXS : RX Endpoint Stall - Read/Write 0 End Point OK
bits : 0 - 0 (1 bit)
access : read-write

RXT : RX Endpoint Type - Read/Write 00 Control Endpoint0 is fixed as a Control End Point.
bits : 2 - 3 (2 bit)
access : read-write

RXE : RX Endpoint Enable 1 Enabled Endpoint0 is always enabled.
bits : 7 - 7 (1 bit)
access : read-write

TXS : TX Endpoint Stall - Read/Write 0 End Point OK [Default] 1 End Point Stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host
bits : 16 - 16 (1 bit)
access : read-write

TXT : TX Endpoint Type - Read/Write 00 - Control Endpoint0 is fixed as a Control End Point.
bits : 18 - 19 (2 bit)
access : read-write

TXE : TX Endpoint Enable 1 Enabled Endpoint0 is always enabled.
bits : 23 - 23 (1 bit)
access : read-write


ENDPTCTRL1

Endpoint Control 1
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTCTRL1 ENDPTCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RXD RXT RXI RXR RXE TXS TXD TXT TXI TXR TXE

RXS : RX Endpoint Stall - Read/Write 0 End Point OK
bits : 0 - 0 (1 bit)
access : read-write

RXD : RX Endpoint Data Sink - Read/Write - TBD 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero
bits : 1 - 1 (1 bit)
access : read-write

RXT : RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Reserved
bits : 2 - 3 (2 bit)
access : read-write

RXI : RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero
bits : 5 - 5 (1 bit)
access : read-write

RXR : RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device
bits : 6 - 6 (1 bit)
access : read-write

RXE : RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured
bits : 7 - 7 (1 bit)
access : read-write

TXS : TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared
bits : 16 - 16 (1 bit)
access : read-write

TXD : TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0
bits : 17 - 17 (1 bit)
access : read-write

TXT : TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt
bits : 18 - 19 (2 bit)
access : read-write

TXI : TX Data Toggle Inhibit 0 PID Sequencing Enabled
bits : 21 - 21 (1 bit)
access : read-write

TXR : TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device
bits : 22 - 22 (1 bit)
access : read-write

TXE : TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured
bits : 23 - 23 (1 bit)
access : read-write


ENDPTCTRL2

Endpoint Control 2
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTCTRL2 ENDPTCTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RXD RXT RXI RXR RXE TXS TXD TXT TXI TXR TXE

RXS : RX Endpoint Stall - Read/Write 0 End Point OK
bits : 0 - 0 (1 bit)
access : read-write

RXD : RX Endpoint Data Sink - Read/Write - TBD 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero
bits : 1 - 1 (1 bit)
access : read-write

RXT : RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Reserved
bits : 2 - 3 (2 bit)
access : read-write

RXI : RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero
bits : 5 - 5 (1 bit)
access : read-write

RXR : RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device
bits : 6 - 6 (1 bit)
access : read-write

RXE : RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured
bits : 7 - 7 (1 bit)
access : read-write

TXS : TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared
bits : 16 - 16 (1 bit)
access : read-write

TXD : TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0
bits : 17 - 17 (1 bit)
access : read-write

TXT : TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt
bits : 18 - 19 (2 bit)
access : read-write

TXI : TX Data Toggle Inhibit 0 PID Sequencing Enabled
bits : 21 - 21 (1 bit)
access : read-write

TXR : TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device
bits : 22 - 22 (1 bit)
access : read-write

TXE : TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured
bits : 23 - 23 (1 bit)
access : read-write


ENDPTCTRL3

Endpoint Control 3
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTCTRL3 ENDPTCTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RXD RXT RXI RXR RXE TXS TXD TXT TXI TXR TXE

RXS : RX Endpoint Stall - Read/Write 0 End Point OK
bits : 0 - 0 (1 bit)
access : read-write

RXD : RX Endpoint Data Sink - Read/Write - TBD 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero
bits : 1 - 1 (1 bit)
access : read-write

RXT : RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Reserved
bits : 2 - 3 (2 bit)
access : read-write

RXI : RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero
bits : 5 - 5 (1 bit)
access : read-write

RXR : RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device
bits : 6 - 6 (1 bit)
access : read-write

RXE : RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured
bits : 7 - 7 (1 bit)
access : read-write

TXS : TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared
bits : 16 - 16 (1 bit)
access : read-write

TXD : TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0
bits : 17 - 17 (1 bit)
access : read-write

TXT : TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt
bits : 18 - 19 (2 bit)
access : read-write

TXI : TX Data Toggle Inhibit 0 PID Sequencing Enabled
bits : 21 - 21 (1 bit)
access : read-write

TXR : TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device
bits : 22 - 22 (1 bit)
access : read-write

TXE : TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured
bits : 23 - 23 (1 bit)
access : read-write


ENDPTCTRL4

Endpoint Control 4
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTCTRL4 ENDPTCTRL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RXD RXT RXI RXR RXE TXS TXD TXT TXI TXR TXE

RXS : RX Endpoint Stall - Read/Write 0 End Point OK
bits : 0 - 0 (1 bit)
access : read-write

RXD : RX Endpoint Data Sink - Read/Write - TBD 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero
bits : 1 - 1 (1 bit)
access : read-write

RXT : RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Reserved
bits : 2 - 3 (2 bit)
access : read-write

RXI : RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero
bits : 5 - 5 (1 bit)
access : read-write

RXR : RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device
bits : 6 - 6 (1 bit)
access : read-write

RXE : RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured
bits : 7 - 7 (1 bit)
access : read-write

TXS : TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared
bits : 16 - 16 (1 bit)
access : read-write

TXD : TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0
bits : 17 - 17 (1 bit)
access : read-write

TXT : TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt
bits : 18 - 19 (2 bit)
access : read-write

TXI : TX Data Toggle Inhibit 0 PID Sequencing Enabled
bits : 21 - 21 (1 bit)
access : read-write

TXR : TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device
bits : 22 - 22 (1 bit)
access : read-write

TXE : TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured
bits : 23 - 23 (1 bit)
access : read-write


ENDPTCTRL5

Endpoint Control 5
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTCTRL5 ENDPTCTRL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RXD RXT RXI RXR RXE TXS TXD TXT TXI TXR TXE

RXS : RX Endpoint Stall - Read/Write 0 End Point OK
bits : 0 - 0 (1 bit)
access : read-write

RXD : RX Endpoint Data Sink - Read/Write - TBD 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero
bits : 1 - 1 (1 bit)
access : read-write

RXT : RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Reserved
bits : 2 - 3 (2 bit)
access : read-write

RXI : RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero
bits : 5 - 5 (1 bit)
access : read-write

RXR : RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device
bits : 6 - 6 (1 bit)
access : read-write

RXE : RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured
bits : 7 - 7 (1 bit)
access : read-write

TXS : TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared
bits : 16 - 16 (1 bit)
access : read-write

TXD : TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0
bits : 17 - 17 (1 bit)
access : read-write

TXT : TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt
bits : 18 - 19 (2 bit)
access : read-write

TXI : TX Data Toggle Inhibit 0 PID Sequencing Enabled
bits : 21 - 21 (1 bit)
access : read-write

TXR : TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device
bits : 22 - 22 (1 bit)
access : read-write

TXE : TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured
bits : 23 - 23 (1 bit)
access : read-write


ENDPTCTRL6

Endpoint Control 6
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTCTRL6 ENDPTCTRL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RXD RXT RXI RXR RXE TXS TXD TXT TXI TXR TXE

RXS : RX Endpoint Stall - Read/Write 0 End Point OK
bits : 0 - 0 (1 bit)
access : read-write

RXD : RX Endpoint Data Sink - Read/Write - TBD 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero
bits : 1 - 1 (1 bit)
access : read-write

RXT : RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Reserved
bits : 2 - 3 (2 bit)
access : read-write

RXI : RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero
bits : 5 - 5 (1 bit)
access : read-write

RXR : RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device
bits : 6 - 6 (1 bit)
access : read-write

RXE : RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured
bits : 7 - 7 (1 bit)
access : read-write

TXS : TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared
bits : 16 - 16 (1 bit)
access : read-write

TXD : TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0
bits : 17 - 17 (1 bit)
access : read-write

TXT : TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt
bits : 18 - 19 (2 bit)
access : read-write

TXI : TX Data Toggle Inhibit 0 PID Sequencing Enabled
bits : 21 - 21 (1 bit)
access : read-write

TXR : TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device
bits : 22 - 22 (1 bit)
access : read-write

TXE : TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured
bits : 23 - 23 (1 bit)
access : read-write


ENDPTCTRL7

Endpoint Control 7
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTCTRL7 ENDPTCTRL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RXD RXT RXI RXR RXE TXS TXD TXT TXI TXR TXE

RXS : RX Endpoint Stall - Read/Write 0 End Point OK
bits : 0 - 0 (1 bit)
access : read-write

RXD : RX Endpoint Data Sink - Read/Write - TBD 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero
bits : 1 - 1 (1 bit)
access : read-write

RXT : RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Reserved
bits : 2 - 3 (2 bit)
access : read-write

RXI : RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero
bits : 5 - 5 (1 bit)
access : read-write

RXR : RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device
bits : 6 - 6 (1 bit)
access : read-write

RXE : RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured
bits : 7 - 7 (1 bit)
access : read-write

TXS : TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared
bits : 16 - 16 (1 bit)
access : read-write

TXD : TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0
bits : 17 - 17 (1 bit)
access : read-write

TXT : TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt
bits : 18 - 19 (2 bit)
access : read-write

TXI : TX Data Toggle Inhibit 0 PID Sequencing Enabled
bits : 21 - 21 (1 bit)
access : read-write

TXR : TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device
bits : 22 - 22 (1 bit)
access : read-write

TXE : TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured
bits : 23 - 23 (1 bit)
access : read-write


HWGENERAL

Hardware General
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWGENERAL HWGENERAL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHYW PHYM SM

PHYW : Data width of the transciever connected to the controller core
bits : 4 - 5 (2 bit)
access : read-only

Enumeration:

0x3 : PHYW_3

Reset to 16 bit wide data bus Software programmable

End of enumeration elements list.

PHYM : Transceiver type PHYM bit reset value: '0000b' for OTG1/OTG2 controller core, and '1011b' for Host-only HSIC controller core
bits : 6 - 9 (4 bit)
access : read-only

Enumeration:

0 : PHYM_0

UTMI/UMTI+

0xB : PHYM_11

Software programmable - reset to HSIC

End of enumeration elements list.

SM : Serial interface mode capability SM bit reset value is '00b'
bits : 10 - 11 (2 bit)
access : read-only

Enumeration:

0 : SM_0

No Serial Engine, always use parallel signalling.

End of enumeration elements list.


HWHOST

Host Hardware Parameters
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWHOST HWHOST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HC NPORT

HC : Host Capable. Indicating whether host operation mode is supported or not.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : HC_0

Not supported

0x1 : HC_1

Supported

End of enumeration elements list.

NPORT : The Nmber of downstream ports supported by the host controller is (NPORT+1)
bits : 1 - 3 (3 bit)
access : read-only


GPTIMER0LD

General Purpose Timer #0 Load
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPTIMER0LD GPTIMER0LD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPTLD

GPTLD : General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'
bits : 0 - 23 (24 bit)
access : read-write


GPTIMER0CTRL

General Purpose Timer #0 Controller
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPTIMER0CTRL GPTIMER0CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPTCNT GPTMODE GPTRST GPTRUN

GPTCNT : General Purpose Timer Counter. This field is the count value of the countdown timer.
bits : 0 - 23 (24 bit)
access : read-write

GPTMODE : General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : GPTMODE_0

One Shot Mode

0x1 : GPTMODE_1

Repeat Mode

End of enumeration elements list.

GPTRST : General Purpose Timer Reset
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : GPTRST_0

No action

0x1 : GPTRST_1

Load counter value from GPTLD bits in n_GPTIMER0LD

End of enumeration elements list.

GPTRUN : General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : GPTRUN_0

Stop counting

0x1 : GPTRUN_1

Run

End of enumeration elements list.


GPTIMER1LD

General Purpose Timer #1 Load
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPTIMER1LD GPTIMER1LD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPTLD

GPTLD : General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'
bits : 0 - 23 (24 bit)
access : read-write


GPTIMER1CTRL

General Purpose Timer #1 Controller
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPTIMER1CTRL GPTIMER1CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPTCNT GPTMODE GPTRST GPTRUN

GPTCNT : General Purpose Timer Counter. This field is the count value of the countdown timer.
bits : 0 - 23 (24 bit)
access : read-write

GPTMODE : General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : GPTMODE_0

One Shot Mode

0x1 : GPTMODE_1

Repeat Mode

End of enumeration elements list.

GPTRST : General Purpose Timer Reset
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : GPTRST_0

No action

0x1 : GPTRST_1

Load counter value from GPTLD bits in USB_n_GPTIMER0LD

End of enumeration elements list.

GPTRUN : General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : GPTRUN_0

Stop counting

0x1 : GPTRUN_1

Run

End of enumeration elements list.


SBUSCFG

System Bus Config
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SBUSCFG SBUSCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHBBRST

AHBBRST : AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority)
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : AHBBRST_0

Incremental burst of unspecified length only

0x1 : AHBBRST_1

INCR4 burst, then single transfer

0x2 : AHBBRST_2

INCR8 burst, INCR4 burst, then single transfer

0x3 : AHBBRST_3

INCR16 burst, INCR8 burst, INCR4 burst, then single transfer

0x5 : AHBBRST_5

INCR4 burst, then incremental burst of unspecified length

0x6 : AHBBRST_6

INCR8 burst, INCR4 burst, then incremental burst of unspecified length

0x7 : AHBBRST_7

INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length

End of enumeration elements list.


HWDEVICE

Device Hardware Parameters
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWDEVICE HWDEVICE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DC DEVEP

DC : Device Capable. Indicating whether device operation mode is supported or not.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : DC_0

Not supported

0x1 : DC_1

Supported

End of enumeration elements list.

DEVEP : Device Endpoint Number
bits : 1 - 5 (5 bit)
access : read-only



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