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OCOTP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x7F4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

TIMING

DATA0

DATA1

CTRL_SET

DATA2

LOCK

TESTER0

TESTER1

TESTER2

TESTER3

TESTER4

TESTER5

BOOT_CFG0

BOOT_CFG1

BOOT_CFG2

BOOT_CFG3

BOOT_CFG4

MEM_TRIM0

MEM_TRIM1

ANA0

ANA1

DATA3

OTPMK0

OTPMK1

OTPMK2

OTPMK3

OTPMK4

OTPMK5

OTPMK6

OTPMK7

SRK0

SRK1

SRK2

SRK3

SRK4

SRK5

SRK6

SRK7

READ_CTRL

SJC_RESP0

SJC_RESP1

USB_ID

FIELD_RETURN

MAC_ADDR0

MAC_ADDR1

MAC_ADDR2

SRK_REVOKE

MAU_KEY0

MAU_KEY1

MAU_KEY2

MAU_KEY3

MAU_KEY4

MAU_KEY5

MAU_KEY6

MAU_KEY7

READ_FUSE_DATA0

GP10

GP11

GP20

GP21

CRC_GP10

CRC_GP11

CRC_GP20

CRC_GP21

CTRL_CLR

READ_FUSE_DATA1

READ_FUSE_DATA2

READ_FUSE_DATA3

SW_STICKY

CTRL_TOG

SCS

SCS_SET

SCS_CLR

SCS_TOG

CRC_ADDR

CRC_VALUE

VERSION


CTRL

OTP Controller Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RSVD0 BUSY ERROR RELOAD_SHADOWS CRC_TEST CRC_FAIL RSVD1 WR_UNLOCK

ADDR : OTP write and read access address register
bits : 0 - 3 (4 bit)
access : read-write

RSVD0 : This field is reserved.
bits : 4 - 7 (4 bit)
access : read-only

BUSY : OTP controller status bit
bits : 8 - 8 (1 bit)
access : read-only

ERROR : Set by the controller when an access to a locked region (OTP or shadow register) is requested
bits : 9 - 9 (1 bit)
access : read-write

RELOAD_SHADOWS : Set to force re-loading all the shadow registers (HW / SW capability and LOCK)
bits : 10 - 10 (1 bit)
access : read-write

CRC_TEST : Set to calculate CRC32 according to start address and end address in CRC_ADDR register
bits : 11 - 11 (1 bit)
access : read-write

CRC_FAIL : Set by controller when calculated CRC value is not equal to appointed CRC fuse word.
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : This field is reserved.
bits : 13 - 15 (3 bit)
access : read-only

WR_UNLOCK : Write 0x3E77 to enable OTP write accesses
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0x3E77 : KEY

Key needed to unlock HW_OCOTP_DATA register.

End of enumeration elements list.


TIMING

OTP Controller Timing Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMING TIMING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROG FSOURCE RSRVD0

PROG : This count value specifies the strobe period in one time write OTP
bits : 0 - 11 (12 bit)
access : read-write

FSOURCE : This count value specifies FSOURCE to PROG setup / hold time
bits : 12 - 19 (8 bit)
access : read-write

RSRVD0 : This field is reserved.
bits : 20 - 31 (12 bit)
access : read-only


DATA0

OTP Controller Write Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA0 DATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA0

DATA0 : The program data for first fuse word in one 128 bits OTP
bits : 0 - 31 (32 bit)
access : read-write


DATA1

OTP Controller Write Data Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA1 DATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA1

DATA1 : The program data for second fuse word in one 128 bits OTP.
bits : 0 - 31 (32 bit)
access : read-write


CTRL_SET

OTP Controller Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_SET CTRL_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RSVD0 BUSY ERROR RELOAD_SHADOWS CRC_TEST CRC_FAIL RSVD1 WR_UNLOCK

ADDR : OTP write and read access address register
bits : 0 - 3 (4 bit)
access : read-write

RSVD0 : This field is reserved.
bits : 4 - 7 (4 bit)
access : read-only

BUSY : OTP controller status bit
bits : 8 - 8 (1 bit)
access : read-only

ERROR : Set by the controller when an access to a locked region (OTP or shadow register) is requested
bits : 9 - 9 (1 bit)
access : read-write

RELOAD_SHADOWS : Set to force re-loading all the shadow registers (HW / SW capability and LOCK)
bits : 10 - 10 (1 bit)
access : read-write

CRC_TEST : Set to calculate CRC32 according to start address and end address in CRC_ADDR register
bits : 11 - 11 (1 bit)
access : read-write

CRC_FAIL : Set by controller when calculated CRC value is not equal to appointed CRC fuse word.
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : This field is reserved.
bits : 13 - 15 (3 bit)
access : read-only

WR_UNLOCK : Write 0x3E77 to enable OTP write accesses
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0x3E77 : KEY

Key needed to unlock HW_OCOTP_DATA register.

End of enumeration elements list.


DATA2

OTP Controller Write Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA2 DATA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA2

DATA2 : The program data for third fuse word in one 128 bits OTP.
bits : 0 - 31 (32 bit)
access : read-write


LOCK

Value of OTP Bank0 Word0 (Lock controls)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TESTER BOOT_CFG MEM_TRIM ANALOG OTPMK SRK SJC_RESP RSVD0 USB_ID MAC_ADDR MAU_KEY ROM_PATCH RSVD1 GP1 GP2 RSVD2 CRC_GP1 CRC_GP2

TESTER : Status of shadow register and OTP write lock for tester region
bits : 0 - 1 (2 bit)
access : read-only

BOOT_CFG : Status of shadow register and OTP write lock for BOOT_CFG region
bits : 2 - 3 (2 bit)
access : read-only

MEM_TRIM : Status of shadow register and OTP write lock for MEM_TRIM region
bits : 4 - 5 (2 bit)
access : read-only

ANALOG : Status of shadow register and OTP write lock for analog region
bits : 6 - 7 (2 bit)
access : read-only

OTPMK : Status of shadow register read and write, OTP read and write lock for OTPMK region
bits : 8 - 8 (1 bit)
access : read-only

SRK : Status of shadow register and OTP write lock for SRK region
bits : 9 - 9 (1 bit)
access : read-only

SJC_RESP : Status of shadow register read and write, OTP read and write lock for SJC_RESP region
bits : 10 - 10 (1 bit)
access : read-only

RSVD0 : This field is reserved.
bits : 11 - 11 (1 bit)
access : read-only

USB_ID : Status of shadow register and OTP write lock for USB_ID region
bits : 12 - 13 (2 bit)
access : read-only

MAC_ADDR : Status of shadow register and OTP write lock for MAC_ADDR region
bits : 14 - 15 (2 bit)
access : read-only

MAU_KEY : Status of shadow register read and write, OTP read and write lock for MANUFACTURE_KEY region
bits : 16 - 16 (1 bit)
access : read-only

ROM_PATCH : Status of shadow register and OTP write lock for ROM_PATCH region
bits : 17 - 17 (1 bit)
access : read-only

RSVD1 : This field is reserved.
bits : 18 - 19 (2 bit)
access : read-only

GP1 : Status of shadow register and OTP write lock for GP1 region
bits : 20 - 21 (2 bit)
access : read-only

GP2 : Status of shadow register and OTP write lock for GP2 region
bits : 22 - 23 (2 bit)
access : read-only

RSVD2 : This field is reserved.
bits : 24 - 27 (4 bit)
access : read-only

CRC_GP1 : Status of shadow register write and read, OTP write and read lock for CRC_GP1 region
bits : 28 - 29 (2 bit)
access : read-only

CRC_GP2 : Status of shadow register write and read, OTP write and read lock for CRC_GP2 region
bits : 30 - 31 (2 bit)
access : read-only


TESTER0

Value of OTP Bank0 Word1 (Tester Information)
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TESTER0 TESTER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects value of OTP Bank 0, word 1
bits : 0 - 31 (32 bit)
access : read-write


TESTER1

Value of OTP Bank0 Word2 (Tester Information)
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TESTER1 TESTER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects value of OTP Bank 0, word 2
bits : 0 - 31 (32 bit)
access : read-write


TESTER2

Value of OTP Bank0 Word3 (Tester Information)
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TESTER2 TESTER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects value of OTP Bank 0, word 3
bits : 0 - 31 (32 bit)
access : read-write


TESTER3

Value of OTP Bank1 Word0 (Tester Information)
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TESTER3 TESTER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects value of OTP Bank 1, word 0
bits : 0 - 31 (32 bit)
access : read-write


TESTER4

Value of OTP Bank1 Word1 (Tester Information)
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TESTER4 TESTER4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects value of OTP Bank 1, word 1
bits : 0 - 31 (32 bit)
access : read-write


TESTER5

Value of OTP Bank1 Word2 (Tester Information)
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TESTER5 TESTER5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects value of OTP Bank 1, word 2
bits : 0 - 31 (32 bit)
access : read-write


BOOT_CFG0

Value of OTP Bank1 Word3 (Boot Configuration Information)
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOT_CFG0 BOOT_CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects value of OTP Bank 1, word 3
bits : 0 - 31 (32 bit)
access : read-write


BOOT_CFG1

Value of OTP Bank2 Word0 (Boot Configuration Information)
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOT_CFG1 BOOT_CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects value of OTP bank 2, word 0
bits : 0 - 31 (32 bit)
access : read-write


BOOT_CFG2

Value of OTP Bank2 Word1 (Boot Configuration Information)
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOT_CFG2 BOOT_CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects value of OTP bank 2, word 1
bits : 0 - 31 (32 bit)
access : read-write


BOOT_CFG3

Value of OTP Bank2 Word2 (Boot Configuration Information)
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOT_CFG3 BOOT_CFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects value of OTP bank 2, word 2
bits : 0 - 31 (32 bit)
access : read-write


BOOT_CFG4

Value of OTP Bank2 Word3 (BOOT Configuration Information)
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOT_CFG4 BOOT_CFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects value of OTP bank 2, word 3
bits : 0 - 31 (32 bit)
access : read-write


MEM_TRIM0

Value of OTP Bank3 Word0 (Memory Related Information)
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM_TRIM0 MEM_TRIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects value of OTP bank 3, word 0
bits : 0 - 31 (32 bit)
access : read-write


MEM_TRIM1

Value of OTP Bank3 Word1 (Memory Related Information)
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM_TRIM1 MEM_TRIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects value of OTP bank 3, word 1
bits : 0 - 31 (32 bit)
access : read-write


ANA0

Value of OTP Bank3 Word2 (Analog Information)
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANA0 ANA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects value of OTP bank 3, word 2
bits : 0 - 31 (32 bit)
access : read-write


ANA1

Value of OTP Bank3 Word3 (Analog Info.)
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANA1 ANA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects value of OTP bank 3, word 3
bits : 0 - 31 (32 bit)
access : read-write


DATA3

OTP Controller Write Data Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA3 DATA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA3

DATA3 : The program data for the last fuse word in one 128 bits OTP.
bits : 0 - 31 (32 bit)
access : read-write


OTPMK0

Shadow Register for OTP Bank4 Word0 (OTPMK Key)
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK0 OTPMK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the OTPMK Key word0 (Copy of OTP Bank 4, word 0)
bits : 0 - 31 (32 bit)
access : read-write


OTPMK1

Shadow Register for OTP Bank4 Word1 (OTPMK Key)
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK1 OTPMK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the OTPMK Key word1 (Copy of OTP Bank 4, word 1)
bits : 0 - 31 (32 bit)
access : read-write


OTPMK2

Shadow Register for OTP Bank4 Word2 (OTPMK Key)
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK2 OTPMK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the OTPMK Key word2 (Copy of OTP Bank 4, word 2)
bits : 0 - 31 (32 bit)
access : read-write


OTPMK3

Shadow Register for OTP Bank4 Word3 (OTPMK Key)
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK3 OTPMK3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the OTPMK Key word3 (Copy of OTP Bank 4, word 3)
bits : 0 - 31 (32 bit)
access : read-write


OTPMK4

Shadow Register for OTP Bank5 Word0 (OTPMK Key)
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK4 OTPMK4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the OTPMK Key word4 (Copy of OTP Bank 5, word 0)
bits : 0 - 31 (32 bit)
access : read-write


OTPMK5

Shadow Register for OTP Bank5 Word1 (OTPMK Key)
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK5 OTPMK5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the OTPMK Key word5 (Copy of OTP Bank 5, word 1)
bits : 0 - 31 (32 bit)
access : read-write


OTPMK6

Shadow Register for OTP Bank5 Word2 (OTPMK Key)
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK6 OTPMK6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the OTPMK Key word6 (Copy of OTP Bank 5, word 2)
bits : 0 - 31 (32 bit)
access : read-write


OTPMK7

Shadow Register for OTP Bank5 Word3 (OTPMK Key)
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK7 OTPMK7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the OTPMK Key word7 (Copy of OTP Bank 5, word 3)
bits : 0 - 31 (32 bit)
access : read-write


SRK0

Shadow Register for OTP Bank6 Word0 (SRK Hash)
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK0 SRK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the hash of the Super Root Key word0 (Copy of OTP Bank 6, word 0)
bits : 0 - 31 (32 bit)
access : read-write


SRK1

Shadow Register for OTP Bank6 Word1 (SRK Hash)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK1 SRK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the hash of the Super Root Key word1 (Copy of OTP Bank 6, word 1)
bits : 0 - 31 (32 bit)
access : read-write


SRK2

Shadow Register for OTP Bank6 Word2 (SRK Hash)
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK2 SRK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the hash of the Super Root Key word2 (Copy of OTP Bank 6, word 2)
bits : 0 - 31 (32 bit)
access : read-write


SRK3

Shadow Register for OTP Bank6 Word3 (SRK Hash)
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK3 SRK3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the hash of the Super Root Key word3 (Copy of OTP Bank 6, word 3)
bits : 0 - 31 (32 bit)
access : read-write


SRK4

Shadow Register for OTP Bank7 Word0 (SRK Hash)
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK4 SRK4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the hash of the Super Root Key word4 (Copy of OTP Bank 7, word 0)
bits : 0 - 31 (32 bit)
access : read-write


SRK5

Shadow Register for OTP Bank7 Word1 (SRK Hash)
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK5 SRK5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the hash of the Super Root Key word5 (Copy of OTP Bank 7, word 1)
bits : 0 - 31 (32 bit)
access : read-write


SRK6

Shadow Register for OTP Bank7 Word2 (SRK Hash)
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK6 SRK6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the hash of the Super Root Key word6 (Copy of OTP Bank 7, word 2)
bits : 0 - 31 (32 bit)
access : read-write


SRK7

Shadow Register for OTP Bank7 Word3 (SRK Hash)
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK7 SRK7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the hash of the Super Root Key word7 (Copy of OTP Bank 7, word 3)
bits : 0 - 31 (32 bit)
access : read-write


READ_CTRL

OTP Controller Write Data Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READ_CTRL READ_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_FUSE RSVD0

READ_FUSE : Used to initiate a read to OTP
bits : 0 - 0 (1 bit)
access : read-write

RSVD0 : This field is reserved.
bits : 1 - 31 (31 bit)
access : read-only


SJC_RESP0

Value of OTP Bank8 Word0 (Secure JTAG Response Field)
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SJC_RESP0 SJC_RESP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the SJC_RESP Key word0 (Copy of OTP Bank 8, word 0)
bits : 0 - 31 (32 bit)
access : read-write


SJC_RESP1

Value of OTP Bank8 Word1 (Secure JTAG Response Field)
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SJC_RESP1 SJC_RESP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the SJC_RESP Key word1 (Copy of OTP Bank 8, word 1)
bits : 0 - 31 (32 bit)
access : read-write


USB_ID

Value of OTP Bank8 Word2 (USB ID info)
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB_ID USB_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects the value of OTP Bank 8, word 2.
bits : 0 - 31 (32 bit)
access : read-write


FIELD_RETURN

Value of OTP Bank8 Word3 (Field Return)
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIELD_RETURN FIELD_RETURN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects the value of OTP Bank 8, word 3.
bits : 0 - 31 (32 bit)
access : read-write


MAC_ADDR0

Value of OTP Bank9 Word0 (MAC Address)
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_ADDR0 MAC_ADDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects the value of OTP Bank 9, word 0.
bits : 0 - 31 (32 bit)
access : read-write


MAC_ADDR1

Value of OTP Bank9 Word1 (MAC Address)
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_ADDR1 MAC_ADDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects the value of OTP Bank 9, word 1.
bits : 0 - 31 (32 bit)
access : read-write


MAC_ADDR2

Value of OTP Bank9 Word2 (MAC Address)
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_ADDR2 MAC_ADDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects the value of OTP Bank 9, word 2.
bits : 0 - 31 (32 bit)
access : read-write


SRK_REVOKE

Value of OTP Bank9 Word3 (SRK Revoke)
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK_REVOKE SRK_REVOKE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects the value of OTP Bank 9, word 3.
bits : 0 - 31 (32 bit)
access : read-write


MAU_KEY0

Shadow Register for OTP Bank10 Word0 (MAU Key)
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAU_KEY0 MAU_KEY0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the MAU Key word0 (Copy of OTP Bank 10, word 0)
bits : 0 - 31 (32 bit)
access : read-write


MAU_KEY1

Shadow Register for OTP Bank10 Word1 (MAU Key)
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAU_KEY1 MAU_KEY1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the MAU Key word1 (Copy of OTP Bank 10, word 1)
bits : 0 - 31 (32 bit)
access : read-write


MAU_KEY2

Shadow Register for OTP Bank10 Word2 (MAU Key)
address_offset : 0x6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAU_KEY2 MAU_KEY2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the MAU Key word2 (Copy of OTP Bank 10, word 2)
bits : 0 - 31 (32 bit)
access : read-write


MAU_KEY3

Shadow Register for OTP Bank10 Word3 (MAU Key)
address_offset : 0x6B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAU_KEY3 MAU_KEY3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the MAU Key word3 (Copy of OTP Bank 10, word 3)
bits : 0 - 31 (32 bit)
access : read-write


MAU_KEY4

Shadow Register for OTP Bank11 Word0 (MAU Key)
address_offset : 0x6C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAU_KEY4 MAU_KEY4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the MAU Key word4 (Copy of OTP Bank 11, word 0)
bits : 0 - 31 (32 bit)
access : read-write


MAU_KEY5

Shadow Register for OTP Bank11 Word1 (MAU Key)
address_offset : 0x6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAU_KEY5 MAU_KEY5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the MAU Key word5 (Copy of OTP Bank 11, word 1)
bits : 0 - 31 (32 bit)
access : read-write


MAU_KEY6

Shadow Register for OTP Bank11 Word2 (MAU Key)
address_offset : 0x6E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAU_KEY6 MAU_KEY6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the MAU Key word6 (Copy of OTP Bank 11, word 2)
bits : 0 - 31 (32 bit)
access : read-write


MAU_KEY7

Shadow Register for OTP Bank11 Word3 (MAU Key)
address_offset : 0x6F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAU_KEY7 MAU_KEY7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : Shadow register for the MAU Key word7 (Copy of OTP Bank 11, word 3)
bits : 0 - 31 (32 bit)
access : read-write


READ_FUSE_DATA0

OTP Controller Read Data Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READ_FUSE_DATA0 READ_FUSE_DATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA0

DATA0 : The first fuse word data read from one OTP.
bits : 0 - 31 (32 bit)
access : read-write


GP10

Value of OTP Bank14 Word0
address_offset : 0x780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP10 GP10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects the value of OTP Bank 14, word 0.
bits : 0 - 31 (32 bit)
access : read-write


GP11

Value of OTP Bank14 Word1
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP11 GP11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects the value of OTP Bank 14, word 1.
bits : 0 - 31 (32 bit)
access : read-write


GP20

Value of OTP Bank14 Word2
address_offset : 0x7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP20 GP20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects the value of OTP Bank 14, word 2.
bits : 0 - 31 (32 bit)
access : read-write


GP21

Value of OTP Bank14 Word3
address_offset : 0x7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP21 GP21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects the value of OTP Bank 14, word 3.
bits : 0 - 31 (32 bit)
access : read-write


CRC_GP10

Value of OTP Bank15 Word0 (CRC Key)
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC_GP10 CRC_GP10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects the value of OTP Bank 15, word 0.
bits : 0 - 31 (32 bit)
access : read-write


CRC_GP11

Value of OTP Bank15 Word1 (CRC Key)
address_offset : 0x7D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC_GP11 CRC_GP11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects the value of OTP Bank 15, word 1.
bits : 0 - 31 (32 bit)
access : read-write


CRC_GP20

Value of OTP Bank15 Word2 (CRC Key)
address_offset : 0x7E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC_GP20 CRC_GP20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects the value of OTP Bank 15, word 2.
bits : 0 - 31 (32 bit)
access : read-write


CRC_GP21

Value of OTP Bank15 Word3 (CRC Key)
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC_GP21 CRC_GP21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : It reflects the value of OTP Bank 15, word 3.
bits : 0 - 31 (32 bit)
access : read-write


CTRL_CLR

OTP Controller Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_CLR CTRL_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RSVD0 BUSY ERROR RELOAD_SHADOWS CRC_TEST CRC_FAIL RSVD1 WR_UNLOCK

ADDR : OTP write and read access address register
bits : 0 - 3 (4 bit)
access : read-write

RSVD0 : This field is reserved.
bits : 4 - 7 (4 bit)
access : read-only

BUSY : OTP controller status bit
bits : 8 - 8 (1 bit)
access : read-only

ERROR : Set by the controller when an access to a locked region (OTP or shadow register) is requested
bits : 9 - 9 (1 bit)
access : read-write

RELOAD_SHADOWS : Set to force re-loading all the shadow registers (HW / SW capability and LOCK)
bits : 10 - 10 (1 bit)
access : read-write

CRC_TEST : Set to calculate CRC32 according to start address and end address in CRC_ADDR register
bits : 11 - 11 (1 bit)
access : read-write

CRC_FAIL : Set by controller when calculated CRC value is not equal to appointed CRC fuse word.
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : This field is reserved.
bits : 13 - 15 (3 bit)
access : read-only

WR_UNLOCK : Write 0x3E77 to enable OTP write accesses
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0x3E77 : KEY

Key needed to unlock HW_OCOTP_DATA register.

End of enumeration elements list.


READ_FUSE_DATA1

OTP Controller Read Data Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READ_FUSE_DATA1 READ_FUSE_DATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA1

DATA1 : The second fuse word data read from one OTP.
bits : 0 - 31 (32 bit)
access : read-write


READ_FUSE_DATA2

OTP Controller Read Data Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READ_FUSE_DATA2 READ_FUSE_DATA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA2

DATA2 : The third fuse word data read from one OTP.
bits : 0 - 31 (32 bit)
access : read-write


READ_FUSE_DATA3

OTP Controller Read Data Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READ_FUSE_DATA3 READ_FUSE_DATA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA3

DATA3 : The last fuse word data read from one OTP.
bits : 0 - 31 (32 bit)
access : read-write


SW_STICKY

Sticky bit Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_STICKY SW_STICKY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 SRK_REVOKE_LOCK FIELD_RETURN_LOCK RSVD1

RSVD0 : This field is reserved.
bits : 0 - 0 (1 bit)
access : read-only

SRK_REVOKE_LOCK : Shadow register write and OTP write lock for SRK_REVOKE region
bits : 1 - 1 (1 bit)
access : read-write

FIELD_RETURN_LOCK : Shadow register write and OTP write lock for FIELD_RETURN region
bits : 2 - 2 (1 bit)
access : read-write

RSVD1 : This field is reserved.
bits : 3 - 31 (29 bit)
access : read-only


CTRL_TOG

OTP Controller Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_TOG CTRL_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RSVD0 BUSY ERROR RELOAD_SHADOWS CRC_TEST CRC_FAIL RSVD1 WR_UNLOCK

ADDR : OTP write and read access address register
bits : 0 - 3 (4 bit)
access : read-write

RSVD0 : This field is reserved.
bits : 4 - 7 (4 bit)
access : read-only

BUSY : OTP controller status bit
bits : 8 - 8 (1 bit)
access : read-only

ERROR : Set by the controller when an access to a locked region (OTP or shadow register) is requested
bits : 9 - 9 (1 bit)
access : read-write

RELOAD_SHADOWS : Set to force re-loading all the shadow registers (HW / SW capability and LOCK)
bits : 10 - 10 (1 bit)
access : read-write

CRC_TEST : Set to calculate CRC32 according to start address and end address in CRC_ADDR register
bits : 11 - 11 (1 bit)
access : read-write

CRC_FAIL : Set by controller when calculated CRC value is not equal to appointed CRC fuse word.
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : This field is reserved.
bits : 13 - 15 (3 bit)
access : read-only

WR_UNLOCK : Write 0x3E77 to enable OTP write accesses
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0x3E77 : KEY

Key needed to unlock HW_OCOTP_DATA register.

End of enumeration elements list.


SCS

Software Controllable Signals Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCS SCS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAB_JDE SPARE LOCK

HAB_JDE : HAB JTAG Debug Enable.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : HAB_JDE_0

JTAG debugging is not enabled by the HAB (it can be enabled by other mechanisms).

0x1 : HAB_JDE_1

JTAG debugging is enabled by the HAB (though this signal may be gated off).

End of enumeration elements list.

SPARE : Unallocated read / write bits of implementation for specific software use.
bits : 1 - 30 (30 bit)
access : read-write

LOCK : When set, all of the bits in this register are locked and cannot be changed during SW programming
bits : 31 - 31 (1 bit)
access : read-write


SCS_SET

Software Controllable Signals Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCS_SET SCS_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAB_JDE SPARE LOCK

HAB_JDE : HAB JTAG Debug Enable.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : HAB_JDE_0

JTAG debugging is not enabled by the HAB (it can be enabled by other mechanisms).

0x1 : HAB_JDE_1

JTAG debugging is enabled by the HAB (though this signal may be gated off).

End of enumeration elements list.

SPARE : Unallocated read / write bits of implementation for specific software use.
bits : 1 - 30 (30 bit)
access : read-write

LOCK : When set, all of the bits in this register are locked and cannot be changed during SW programming
bits : 31 - 31 (1 bit)
access : read-write


SCS_CLR

Software Controllable Signals Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCS_CLR SCS_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAB_JDE SPARE LOCK

HAB_JDE : HAB JTAG Debug Enable.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : HAB_JDE_0

JTAG debugging is not enabled by the HAB (it can be enabled by other mechanisms).

0x1 : HAB_JDE_1

JTAG debugging is enabled by the HAB (though this signal may be gated off).

End of enumeration elements list.

SPARE : Unallocated read / write bits of implementation for specific software use.
bits : 1 - 30 (30 bit)
access : read-write

LOCK : When set, all of the bits in this register are locked and cannot be changed during SW programming
bits : 31 - 31 (1 bit)
access : read-write


SCS_TOG

Software Controllable Signals Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCS_TOG SCS_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAB_JDE SPARE LOCK

HAB_JDE : HAB JTAG Debug Enable.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : HAB_JDE_0

JTAG debugging is not enabled by the HAB (it can be enabled by other mechanisms).

0x1 : HAB_JDE_1

JTAG debugging is enabled by the HAB (though this signal may be gated off).

End of enumeration elements list.

SPARE : Unallocated read / write bits of implementation for specific software use.
bits : 1 - 30 (30 bit)
access : read-write

LOCK : When set, all of the bits in this register are locked and cannot be changed during SW programming
bits : 31 - 31 (1 bit)
access : read-write


CRC_ADDR

OTP Controller CRC test address
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC_ADDR CRC_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_START_ADDR DATA_END_ADDR CRC_ADDR RSVD0

DATA_START_ADDR : Start address of fuse word location is for CRC calculation.
bits : 0 - 7 (8 bit)
access : read-write

DATA_END_ADDR : End address of fuse word location is for CRC calculation.
bits : 8 - 15 (8 bit)
access : read-write

CRC_ADDR : Address of 32-bit CRC result is for comparing.
bits : 16 - 17 (2 bit)
access : read-write

RSVD0 : This field is reserved.
bits : 18 - 31 (14 bit)
access : read-only


CRC_VALUE

OTP Controller CRC Value Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC_VALUE CRC_VALUE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : The CRC32 value is based on CRC_ADDR.
bits : 0 - 31 (32 bit)
access : read-write


VERSION

OTP Controller Version Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STEP MINOR MAJOR

STEP : Fixed read-only values reflect the stepping of the RTL version.
bits : 0 - 15 (16 bit)
access : read-only

MINOR : Fixed read-only values reflect the MINOR field of the RTL version.
bits : 16 - 23 (8 bit)
access : read-only

MAJOR : Fixed read-only values reflect the MAJOR field of the RTL version.
bits : 24 - 31 (8 bit)
access : read-only



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