Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xB40 byte (0x0)
mem_usage : registers
protection : not protected
Version Information
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NDID : Number of Domains
bits : 0 - 3 (4 bit)
access : read-only
NMSTR : Number of Masters
bits : 4 - 11 (8 bit)
access : read-only
NPER : Number of Peripherals
bits : 12 - 19 (8 bit)
access : read-only
NRGN : Number of Memory Regions
bits : 20 - 27 (8 bit)
access : read-only
Memory Region Start Address
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x10014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x10088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x100F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x100FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Memory Region Control
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Master Domain Assignment
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x105D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x10960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x109D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x10A50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x10ABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x10AC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x10FA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x11330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x113AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x11428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x11498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x114A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x1198C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x11D10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x11D90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x11E10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x11E84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x11E90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x12380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x12700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x12784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x12808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x12880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x1288C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x12D84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x13100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x13188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x13210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x1328C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x13298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x13798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x13B10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x13B9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x13C28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x13CA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x13CB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x1418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x141BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x14530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x145C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x14650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x146D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x146E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Master Domain Assignment
address_offset : 0x1490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x14BF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x14F60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x14FF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x15088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x15110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x1511C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x15634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x159A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x15A38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x15AD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x15B5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x15B68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x16088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x163F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x1648C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x16528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x165B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x165C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x16AEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x16B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x16E50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x16EF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x16F90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x17024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x17030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x17560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x178C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x17964 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x17A08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x17AA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x17AAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x17FE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x1810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x181C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Peripheral Domain Access Permissions
address_offset : 0x1828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Control
address_offset : 0x1828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x1834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Memory Region Start Address
address_offset : 0x18340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x183E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x18490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x1852C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x18538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x18A78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x18DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x18DD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x18E7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x18F28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x18FC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x18FD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x1951C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x19870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x19920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x199D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x19A74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x19A80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x19FD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x1A320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x1A3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x1A488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x1A530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x1A53C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x1AA94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x1ADE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x1AE98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x1AF50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x1AFFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x1B008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Master Domain Assignment
address_offset : 0x1B08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x1B568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x1B8B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x1B96C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x1BA28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x1BAD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x1BAE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x1C04C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x1C390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Peripheral Domain Access Permissions
address_offset : 0x1C3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region End Address
address_offset : 0x1C450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x1C510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x1C5C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x1C5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x1CB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x1CE80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x1CF44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x1D008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x1D0C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x1D0CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Master Domain Assignment
address_offset : 0x1D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x1D644 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x1D980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x1DA48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x1DB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x1DBCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x1DBD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x1E158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x1E490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x1E55C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x1E628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x1E6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x1E6F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x1EC7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x1EFB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x1F080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x1F150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x1F214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x1F220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Master Domain Assignment
address_offset : 0x1F6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x1F7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x1FAE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x1FBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x1FC88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x1FD50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x1FD5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x202F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x2030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x2040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x2050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x2054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x2060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x2089C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x20E48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x213F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x219AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x21A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x21F64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x22520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x22AE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x230A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x2366C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x23C38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x23E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Status
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 3 (4 bit)
access : read-write
PDS : Power Domain Status
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : PDS_0
Power Down Domain is OFF
0x1 : PDS_1
Power Down Domain is ON
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x24208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x2470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x247DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x2620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Interrupt and Control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCI_EN : Restoration Complete Interrupt
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RCI_EN_0
Interrupt Disabled
0x1 : RCI_EN_1
Interrupt Enabled
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x2860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Master Domain Assignment
address_offset : 0x2864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region End Address
address_offset : 0x2874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x2888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x2890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x289C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Master Domain Assignment
address_offset : 0x2AAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Interrupt Status
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : Interrupt Status
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : INT_0
No Interrupt Pending
0x1 : INT_1
Interrupt Pending
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x2CB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x2CF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x2F48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x30A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x30B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x30D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x30DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x30E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Master Domain Assignment
address_offset : 0x319C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x33F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x3508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x3650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x38B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x38F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x390C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x3928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x3938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x3944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Master Domain Assignment
address_offset : 0x3B14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x3D6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x3D7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x4150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x4170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x4190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x41A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x41B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x45E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x49C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x49E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x4A08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x4A20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x4A2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x4E64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x5240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x5268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x5290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x52AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x52B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x56F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x5AD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x5AFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x5B28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x5B48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x5B54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x5F9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x6370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x63A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x63D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x63F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x6400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x6850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x6C20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x6C54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x6C88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x6CB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x6CBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x7114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x74E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x7518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x7550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x757C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x7588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x79E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x7DB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x7DEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x7E28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x7E58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x7E64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x82CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x8690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x86D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x8710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x8744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x8750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x8BC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x8F80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x8FC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x9008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x9040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x904C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x94C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0x9880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0x98C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0x9910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0x994C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0x9958 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0x9DD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0xA190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0xA1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0xA228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0xA268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0xA274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0xA6FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0xAAB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0xAB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0xAB50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0xAB94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0xABA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0xB030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0xB3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0xB434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0xB488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0xB4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0xB4DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0xB974 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0xBD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0xBD78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0xBDD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0xBE1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0xBE28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0xC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Master Domain Assignment
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0xC2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0xC670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0xC6CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0xC728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0xC778 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0xC784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0xCC2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0xCFD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0xD030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0xD090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0xD0E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0xD0F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0xD5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0xD940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0xD9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0xDA08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0xDA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0xDA6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0xDF24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0xE2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0xE328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0xE390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Master Domain Assignment
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain ID
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DID_0
Master assigned to Processing Domain 0
0x1 : DID_1
Master assigned to Processing Domain 1
0x2 : DID_2
Master assigned to Processing Domain 2
0x3 : DID_3
Master assigned to Processing Domain 3
End of enumeration elements list.
LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0xE3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0xE3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0xE8B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0xEC50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0xECBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0xED28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0xED88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0xED94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0xF25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0xF5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region End Address
address_offset : 0xF660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADR : Upper bound for memory region
bits : 7 - 31 (25 bit)
access : read-write
Memory Region Control
address_offset : 0xF6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access to Region
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
Processing Domain 0 does not have Write access to the memory region
0x1 : D0W_1
Processing Domain 0 has Write access to the memory region
End of enumeration elements list.
D0R : Domain 0 Read Access to Region
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
Processing Domain 0 does not have Read access to the memory region
0x1 : D0R_1
Processing Domain 0 has Read access to the memory region
End of enumeration elements list.
D1W : Domain 1 Write Access to Region
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
Processing Domain 1 does not have Write access to the memory region
0x1 : D1W_1
Processing Domain 1 has Write access to the memory region
End of enumeration elements list.
D1R : Domain 1 Read Access to Region
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
Processing Domain 1 does not have Read access to the memory region
0x1 : D1R_1
Processing Domain 1 has Read access to the memory region
End of enumeration elements list.
D2W : Domain 2 Write Access to Region
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
Processing Domain 2 does not have Write access to the memory region
0x1 : D2W_1
Processing Domain 2 has Write access to the memory region
End of enumeration elements list.
D2R : Domain 2 Read Access to Region
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
Processing Domain 2 does not have Read access to the memory region
0x1 : D2R_1
Processing Domain 2 has Read access to the memory region
End of enumeration elements list.
D3W : Domain 3 Write Access to Region
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
Processing Domain 3 does not have Write access to the memory region
0x1 : D3W_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
D3R : Domain 3 Read Access to Region
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
Processing Domain 3 does not have Read access to the memory region
0x1 : D3R_1
Processing Domain 3 has Read access to the memory region
End of enumeration elements list.
ENA : Region Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : ENA_0
Memory region is not defined or restricted.
0x1 : ENA_1
Memory boundaries, domain permissions and controls are in effect.
End of enumeration elements list.
LCK : Region Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
No Lock. All fields in this register may be modified.
0x1 : LCK_1
Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
End of enumeration elements list.
Peripheral Domain Access Permissions
address_offset : 0xF734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Violation Status
address_offset : 0xF740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDID : Violating Domain ID
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : VDID_0
Processing Domain 0
0x1 : VDID_1
Processing Domain 1
0x2 : VDID_2
Processing Domain 2
0x3 : VDID_3
Processing Domain 3
End of enumeration elements list.
AD : Access Denied
bits : 4 - 4 (1 bit)
access : read-write
VADR : Violating Address
bits : 5 - 31 (27 bit)
access : read-only
Peripheral Domain Access Permissions
address_offset : 0xFC10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0W : Domain 0 Write Access
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : D0W_0
No Write Access
0x1 : D0W_1
Write Access Allowed
End of enumeration elements list.
D0R : Domain 0 Read Access
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : D0R_0
No Read Access
0x1 : D0R_1
Read Access Allowed
End of enumeration elements list.
D1W : Domain 1 Write Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : D1W_0
No Write Access
0x1 : D1W_1
Write Access Allowed
End of enumeration elements list.
D1R : Domain 1 Read Access
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : D1R_0
No Read Access
0x1 : D1R_1
Read Access Allowed
End of enumeration elements list.
D2W : Domain 2 Write Access
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : D2W_0
No Write Access
0x1 : D2W_1
Write Access Allowed
End of enumeration elements list.
D2R : Domain 2 Read Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : D2R_0
No Read Access
0x1 : D2R_1
Read Access Allowed
End of enumeration elements list.
D3W : Domain 3 Write Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : D3W_0
No Write Access
0x1 : D3W_1
Write Access Allowed
End of enumeration elements list.
D3R : Domain 3 Read Access
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : D3R_0
No Read Access
0x1 : D3R_1
Read Access Allowed
End of enumeration elements list.
SREQ : Semaphore Required
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SREQ_0
Semaphores have no effect
0x1 : SREQ_1
Semaphores are enforced
End of enumeration elements list.
LCK : Peripheral Permissions Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : LCK_0
Not Locked
0x1 : LCK_1
Locked
End of enumeration elements list.
Memory Region Start Address
address_offset : 0xFFA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Start address for memory region
bits : 7 - 31 (25 bit)
access : read-write
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