Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x78 byte (0x0)
mem_usage : registers
protection : not protected
SIM Port1 Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAPD1 : SIM card Auto Power Down Port 1
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SAPD1_0
Auto power down Port 1 disabled (default)
0x1 : SAPD1_1
Auto power down Port 1 enabled
End of enumeration elements list.
SVEN1 : SIM card Vcc Enable Port 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SVEN1_0
SIM card Voltage Port 1 disabled (default)
0x1 : SVEN1_1
SIM card Voltage Port 1 enabled
End of enumeration elements list.
STEN1 : SIM card Transmit Enable Port 1
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : STEN1_0
Port1 Transmit Data is forced to zero (default)
0x1 : STEN1_1
Port 1 Transmit Data controlled by SIM module
End of enumeration elements list.
SRST1 : SIM card Reset
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SRST1_0
SIM Card reset Port1 inactive (default)
0x1 : SRST1_1
SIM Card reset Port1 active
End of enumeration elements list.
SCEN1 : SIM card Clock Enable Port 1
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SCEN1_0
SIM Card Clock Disabled Port1
0x1 : SCEN1_1
SIM Card Clock Enabled Port1
End of enumeration elements list.
SCSP1 : SIM Card Clock Stop Polarity Port1
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SCSP1_0
Clock is logic 0 when stopped by SCEN1
0x1 : SCSP1_1
Clock is logic 1 when stopped by SCEN1
End of enumeration elements list.
VOLT3_1 : External one wire interface for SIM Card port1
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : VOLT3_1_0
Port1 uses both rcv and xmt pins
0x1 : VOLT3_1_1
Port1 XMT pin bidirectional. Port1 RCV PIN unused
End of enumeration elements list.
SFPD1 : Auto Power Down port1
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
0 : SFPD1_0
No effect
0x1 : SFPD1_1
Start Auto Power down
End of enumeration elements list.
SIM Receive Buffer Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RCV : Receive buffer. Read from the next location in the receive buffer.
bits : 0 - 7 (8 bit)
access : read-only
PE : Parity Error flag
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : PE_0
Byte contains no parity error (default)
0x1 : PE_1
Byte contains a parity error
End of enumeration elements list.
FE : Frame Error flag
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : FE_0
Byte contains no framing error (default)
0x1 : FE_1
Byte contains a framing error
End of enumeration elements list.
CWT : CWT flag
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : CWT_0
Byte was on time
0x1 : CWT_1
Byte was late
End of enumeration elements list.
SIM Port0 Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAPD0 : SIM card Auto Power Down Port 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SAPD0_0
Auto power down Port 0 disabled (default)
0x1 : SAPD0_1
Auto power down Port 0 enabled
End of enumeration elements list.
SVEN0 : SIM card VCC Enable Port 0
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SVEN0_0
SIM card Voltage Port 0 disabled (default)
0x1 : SVEN0_1
SIM card Voltage Port 0 enabled
End of enumeration elements list.
STEN0 : SIM card Transmit Enable Port 0
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : STEN0_0
Port0 Transmit Data is forced to zero (default)
0x1 : STEN0_1
Port 0 Transmit Data controlled by SIM module
End of enumeration elements list.
SRST0 : SIM card Reset
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SRST0_0
SIM Card reset Port0 inactive (default)
0x1 : SRST0_1
SIM Card reset Port0 active
End of enumeration elements list.
SCEN0 : SIM card Clock Enable Port 0
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SCEN0_0
SIM Card Clock Disabled Port 0
0x1 : SCEN0_1
SIM Card Clock Enabled Port 0
End of enumeration elements list.
SCSP0 : SIM Card Clock Stop Polarity port0
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SCSP0_0
Clock is logic 0 when stopped by scen0
0x1 : SCSP0_1
Clock is logic 1 when stopped by scen0
End of enumeration elements list.
VOLT3_0 : External one wire interface for SIM Card port0
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x1 : VOLT3_0_1
Port0 XMT pin bidirectional. Port0 rcv pin unused
End of enumeration elements list.
SFPD0 : Auto Power Down port0
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
0 : SFPD0_0
No effect
0x1 : SFPD0_1
Start Auto Power down
End of enumeration elements list.
SIM Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICM : Initial Character Mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ICM_0
Initial Character Mode disabled
0x1 : ICM_1
Initial Character Mode enabled (default)
End of enumeration elements list.
ANACK : Automatic NACK Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ANACK_0
NACK generation on errors disabled
0x1 : ANACK_1
NACK generation on errors enabled (default)
End of enumeration elements list.
ONACK : Overrun NACK Enable. Enables overrun NACK generation.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : ONACK_0
NACK generation on overrun is disabled (default)
0x1 : ONACK_1
NACK generation on overrun is enabled
End of enumeration elements list.
Sample12 : Sample12
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Sample12_0
divide by 8(default)
0x1 : Sample12_1
divide by 12
End of enumeration elements list.
baud_sel : SIM Baud Rate Select
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : baud_sel_0
31 (512/1 Fi/Di)
0x1 : baud_sel_1
32 (512/2 Fi/Di)
0x2 : baud_sel_2
16 (512/4 Fi/Di)
0x3 : baud_sel_3
8 (512/8 Fi/Di)
0x4 : baud_sel_4
4 (512/16 Fi/Di)
0x5 : baud_sel_5
2 (512/32 Fi/Di)
0x6 : baud_sel_6
1 (512/64 Fi/Di)
0x7 : baud_sel_7
DIVISOR Reg
End of enumeration elements list.
gpcnt_clk_sel : General Purpose Counter Clock Select
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
0 : gpcnt_clk_sel_0
Disabled / Reset
0x1 : gpcnt_clk_sel_1
Card Clock
0x2 : gpcnt_clk_sel_2
Receive Clock
0x3 : gpcnt_clk_sel_3
ETU Clock (transmit clock)
End of enumeration elements list.
CWTEN : Character Wait Time Counter Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : CWTEN_0
Character Wait time Counter off (default)
0x1 : CWTEN_1
Character Wait time counter on
End of enumeration elements list.
LRCEN : LRC Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LRCEN_0
8-bit Linear Redundancy Checking disabled (default)
0x1 : LRCEN_1
8-bit Linear Redundancy Checking enabled
End of enumeration elements list.
CRCEN : CRC Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : CRCEN_0
16-bit Cyclic Redundancy Checking disabled (default)
0x1 : CRCEN_1
16-bit Cyclic Redundancy Checking enabled
End of enumeration elements list.
xmt_crc_lrc : Transmit CRC or LRC
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : xmt_crc_lrc_0
No Redundancy check info transmitted (default)
0x1 : xmt_crc_lrc_1
Transmit LRC or CRC info when FIFO empties (whichever is enabled)
End of enumeration elements list.
BWTEN : Block wait time enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : BWTEN_0
Disable BWT, BGT
0x1 : BWTEN_1
Enable BWT, BGT
End of enumeration elements list.
SIM Clock Prescaler Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_PRESCALER : Clock prescaler divisor register
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : CLK_PRESCALER_0
~0x02 ipg_perclk/ 2
0x3 : CLK_PRESCALER_3
ipg_perclk / 3
0x4 : CLK_PRESCALER_4
ipg_perclk / 4
0x5 : CLK_PRESCALER_5
ipg_perclk / 5
0x6 : CLK_PRESCALER_6
ipg_perclk / 6
0xFD : CLK_PRESCALER_253
ipg_perclk / 253
0xFE : CLK_PRESCALER_254
ipg_perclk / 254
0xFF : CLK_PRESCALER_255
ipg_perclk / 255
End of enumeration elements list.
SIM Receive Threshold Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDT : Receive Data Threshold
bits : 0 - 8 (9 bit)
access : read-write
RTH : Receive Nack Threshold
bits : 9 - 12 (4 bit)
access : read-write
SIM Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCV_EN : SIM Receiver Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RCV_EN_0
SIM Receiver disabled (default)
0x1 : RCV_EN_1
SIM Receiver enabled
End of enumeration elements list.
XMT_EN : SIM Transmit Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : XMT_EN_0
SIM Transmitter disabled (default)
0x1 : XMT_EN_1
SIM Transmitter enabled
End of enumeration elements list.
RXDMA_EN : Receiver DMA Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : RXDMA_EN_0
SIM Receiver DMA request disabled.
0x1 : RXDMA_EN_1
SIM Receiver DMA request enabled.
End of enumeration elements list.
TXDMA_EN : Transmitter DMA Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TXDMA_EN_0
SIM Transmitter DMA requests disabled.
0x1 : TXDMA_EN_1
SIM Transmitter DMA requests enabled.
End of enumeration elements list.
NACK_DD_EN : NACK delay detection enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NACK_DD_EN_0
Disable the delay detection function.
0x1 : NACK_DD_EN_1
Enable the delay detection function.
End of enumeration elements list.
ESTOP_EN : Enforce reception early stop enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ESTOP_EN_0
Disable the enforce reception early stop function.
0x1 : ESTOP_EN_1
Enable the enforce reception early stop function.
End of enumeration elements list.
ESTOP_EXE : Enforce reception early stop execution
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : ESTOP_EXE_0
Enforce reception early stop function will be executed without NACK.
0x1 : ESTOP_EXE_1
Enforce reception early stop function will be executed at all times.
End of enumeration elements list.
RXCL : Reception data latch disable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : RXCL_0
Enable the synchronization operation.
0x1 : RXCL_1
Disable the synchronization operation.
End of enumeration elements list.
SIM Transmit Status Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTE : Transmit NACK Threshold Error
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : XTE_0
Transmit NACK threshold has not been reached (default)
0x1 : XTE_1
Transmit NACK threshold reached; transmitter frozen
End of enumeration elements list.
TFE : Transmit FIFO Empty
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TFE_0
Transmit FIFO is not empty
0x1 : TFE_1
Transmit FIFO is empty (default)
End of enumeration elements list.
ETC : Early Transmit Complete
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ETC_0
Transmit pending or in progress
0x1 : ETC_1
Transmit complete (default)
End of enumeration elements list.
TC : Transmit Complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : TC_0
Transmit pending or in progress
0x1 : TC_1
Transmit complete (default)
End of enumeration elements list.
TFO : Transmit FIFO Overfill Error
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : TFO_0
No transmit FIFO overfill error has occurred (default).
0x1 : TFO_1
A Transmit FIFO overfill error has occurred.
End of enumeration elements list.
TDTF : Transmit Data Threshold Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : TDTF_0
Number of bytes in FIFO is greater than tdt[3:0], or bit has been cleared.
0x1 : TDTF_1
Number of bytes in FIFO is less than or equal to tdt[3:0] (default)
End of enumeration elements list.
GPCNT : General purpose Counter Flag
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : GPCNT_0
GPCNT time not reached, or bit has been cleared. (default).
0x1 : GPCNT_1
General Purpose counter has reached the GPCNT value.
End of enumeration elements list.
SIM Receive Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OEF : Overrun Error Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : OEF_0
No overrun error has occurred (default).
0x1 : OEF_1
A byte was received when the received FIFO was already full.
End of enumeration elements list.
RFE : Receive FIFO Empty
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RFE_0
Receive FIFO is not empty
0x1 : RFE_1
Receive FIFO is empty (default)
End of enumeration elements list.
RFD : Receive FIFO has unread Data
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : RFD_0
There are no unread bytes in the receive FIFO (default).
0x1 : RFD_1
There is at least one unread byte in the receiver FIFO.
End of enumeration elements list.
RDRF : Receive Data Register Full
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : RDRF_0
Number of unread bytes in receive buffer < value set by RDT[8:0] (default), or bit has been cleared.
0x1 : RDRF_1
Number of unread bytes in receive buffer >= value set by RDT[8:0].
End of enumeration elements list.
LRCOK : Linear Redundancy Check Okay flag
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : LRCOK_0
Current LRC value does not match remainder.
0x1 : LRCOK_1
Current calculated LRC value matches the expected result (that is, zero).
End of enumeration elements list.
CRCOK : Cyclic Redundancy Check Okay flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : CRCOK_0
Current CRC value does not match remainder.
0x1 : CRCOK_1
Current calculated CRC value matches the expected result.
End of enumeration elements list.
CWT : Character Wait Time Counter Flag
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CWT_0
No CWT violation has occurred (default).
0x1 : CWT_1
Time between two consecutive characters exceeded the value in CHAR_WAIT.
End of enumeration elements list.
RTE : Receive NACK threshold error flag
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : RTE_0
Number of NACKs generated by the receiver is less than the value programmed in RTH[3:0]
0x1 : RTE_1
Number of NACKs generated by the receiver is equal to the value programmed in RTH[3:0]
End of enumeration elements list.
BWT : Block wait time error flag
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : BWT_0
Block wait time not exceeded.
0x1 : BWT_1
Block wait time was exceeded.
End of enumeration elements list.
BGT : Block guard time error flag
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : BGT_0
Block guard time was sufficient.
0x1 : BGT_1
Block guard time was too small.
End of enumeration elements list.
SIM Interrupt Mask Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RIM : Receive Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RIM_0
RDRF interrupt enabled
0x1 : RIM_1
RDRF interrupt masked (default)
End of enumeration elements list.
TCIM : Transmit Complete Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TCIM_0
TC interrupt enabled
0x1 : TCIM_1
TC interrupt masked (default)
End of enumeration elements list.
OIM : Overrun Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : OIM_0
OEF interrupt enabled
0x1 : OIM_1
OEF interrupt masked (default)
End of enumeration elements list.
ETCIM : Early Transmit Complete Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : ETCIM_0
ETC interrupt enabled
0x1 : ETCIM_1
ETC interrupt masked (default)
End of enumeration elements list.
TFEIM : Transmit FIFO Empty Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : TFEIM_0
TFE interrupt enabled
0x1 : TFEIM_1
TFE interrupt masked (default)
End of enumeration elements list.
XTM : Transmit Threshold Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : XTM_0
XTE interrupt enabled
0x1 : XTM_1
XTE interrupt masked (default)
End of enumeration elements list.
TFOM : Transmit FIFO Overfill Error Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : TFOM_0
TFO interrupt enabled
0x1 : TFOM_1
TFO interrupt masked (default)
End of enumeration elements list.
TDTFM : Transmit Data Threshold Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : TDTFM_0
TDTF interrupt enabled
0x1 : TDTFM_1
TDTF interrupt masked (default)
End of enumeration elements list.
GPCNTM : General Purpose Counter Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : GPCNTM_0
GPCNT interrupt enabled
0x1 : GPCNTM_1
GPCNT interrupt masked (default)
End of enumeration elements list.
CWTM : Character Wait Time Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : CWTM_0
CWT interrupt enabled
0x1 : CWTM_1
CWT interrupt masked (default)
End of enumeration elements list.
RTM : Receive Nack threshold interrupt mask
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : RTM_0
RTE interrupt enabled
0x1 : RTM_1
RTE interrupt masked (default)
End of enumeration elements list.
BWTM : Block wait time interrupt mask
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : BWTM_0
BWT interrupt enabled
0x1 : BWTM_1
BWT interrupt masked (default)
End of enumeration elements list.
BGTM : Block guard time interrupt mask
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : BGTM_0
BGT interrupt enabled
0x1 : BGTM_1
BGT interrupt masked (default)
End of enumeration elements list.
RFEM : Receive fifo empty interrupt mask
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : RFEM_0
RFE interrupt enabled
0x1 : RFEM_1
RFE interrupt masked (default)
End of enumeration elements list.
SIM Port0 Detect Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDIM0 : SIM Detect Interrupt Mask Port 0. Interrupt mask for the SDI0 interrupt flag.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SDIM0_0
sdi0 enabled
0x1 : SDIM0_1
sdi0 masked (default)
End of enumeration elements list.
SDI0 : SIM Detect Interrupt flag Port 0
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SDI0_0
No insertion or removal of SIM card detected on Port 0 (default)
0x1 : SDI0_1
Insertion or removal of SIM card detected on Port 0
End of enumeration elements list.
SPDP0 : SIMPD0 input pin status
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : SPDP0_0
SIMPD0 pin is logic low
0x1 : SPDP0_1
SIMPD0 pin is logic high
End of enumeration elements list.
SPDS0 : SIM Presence Detect Select Port 0
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SPDS0_0
Falling edge of SIMPD0 Input (default)
0x1 : SPDS0_1
Rising edge of SIMPD0 Input
End of enumeration elements list.
SIM Setup Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AMODE : Alternate SIM Card Mode enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : AMODE_0
Alternate Port Disabled (default)
0x1 : AMODE_1
Alternate Port Enabled
End of enumeration elements list.
SPS : SIM card Port Select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SPS_0
Port 0 Enabled (default)
0x1 : SPS_1
Port 1 Enabled
End of enumeration elements list.
SIM Data Format Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC : Inverse Convention
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : IC_0
Direction convention transfers enabled (default).
0x1 : IC_1
Inverse convention transfers enabled.
End of enumeration elements list.
SIM Transmit Threshold Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDT : Transmit Data Threshold
bits : 0 - 3 (4 bit)
access : read-write
XTH : XTH[3:0] Transmit NACK Threshold
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : XTH_0
XTE will never be set; retransmission after NACK reception is disabled.
0x1 : XTH_1
XTE will be set after 1 nack is received; 0 retransmissions occurs.
0x2 : XTH_2
XTE will be set after 2 nacks are received; at most 1 retransmission occurs.
0x3 : XTH_3
XTE will be set after 3 nacks are received; at most 2 retransmissions occurs.
0xF : XTH_15
XTE will be set after 15 nacks are received; at most 14 retransmissions occurs.
End of enumeration elements list.
SIM Transmit Guard Control Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GETU : Transmit Guard ETUs
bits : 0 - 7 (8 bit)
access : read-write
RCVR11 : Receiver use 11 ETUs
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : RCVR11_0
Receiver configured for 12 ETU operation (default)
0x1 : RCVR11_1
Receiver configured for 11 ETU operation
End of enumeration elements list.
SIM Open Drain Configuration Control Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OD_P0 : Open Drain control for Port 0. Used to control whether the XMT data line on port 0 is open-drain.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : OD_P0_0
XMT pin on port 0 is push-pull (default).
0x1 : OD_P0_1
XMT pin on port 0 is open-drain.
End of enumeration elements list.
OD_P1 : Open Drain control for Port 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : OD_P1_0
XMT pin on port 1 is push-pull (default).
0x1 : OD_P1_1
XMT pin on port 1 is open-drain.
End of enumeration elements list.
SIM Reset Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLUSH_RCV : Flush Receiver
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FLUSH_RCV_0
SIM Receiver normal operation (default).
0x1 : FLUSH_RCV_1
SIM Receiver held in Reset.
End of enumeration elements list.
FLUSH_XMT : Flush Transmitter
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FLUSH_XMT_0
SIM Transmitter normal operation (default).
0x1 : FLUSH_XMT_1
SIM Transmitter held in Reset.
End of enumeration elements list.
SOFT_RST : Software Reset
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
0 : SOFT_RST_0
SIM Normal operation (default).
0x1 : SOFT_RST_1
SIM held in Reset.
End of enumeration elements list.
KILL_CLOCK : Kill SIM Clock
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : KILL_CLOCK_0
SIM input clock enabled (default).
0x1 : KILL_CLOCK_1
SIM input clock disabled.
End of enumeration elements list.
DOZE : DOZE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DOZE_0
DOZE instruction has no effect on SIM module (default).
0x1 : DOZE_1
DOZE instruction will cause SIM module to gate SIM clocks when the transmit FIFO is empty.
End of enumeration elements list.
STOP : STOP
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : STOP_0
STOP instruction shuts down all SIM clocks (default).
0x1 : STOP_1
STOP instruction shuts down all clocks except for the BAUD_CLK (clock provided to SIM Card).
End of enumeration elements list.
SIM Character Wait Time Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CWT : Character Wait Time
bits : 0 - 15 (16 bit)
access : read-write
SIM General Purpose Counter Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPCNT : General Purpose Counter
bits : 0 - 15 (16 bit)
access : read-write
SIM Divisor Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVISOR : DIVISOR Register
bits : 0 - 7 (8 bit)
access : read-write
SIM Block Wait Time Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BWT : BWT Register 16 LSB
bits : 0 - 15 (16 bit)
access : read-write
SIM Block Guard Time Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BGT : BGT Register
bits : 0 - 15 (16 bit)
access : read-write
SIM Block Wait Time Register HIGH
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BWT_H : BWT Register 16 MSB
bits : 0 - 15 (16 bit)
access : read-write
SIM Transmit FIFO Status Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
XMT_RPTR : These bits indicate the transmit FIFO Read Pointer.
bits : 0 - 3 (4 bit)
access : read-only
XMT_WPTR : These bits indicate the transmit FIFO Write Pointer.
bits : 4 - 7 (4 bit)
access : read-only
XMT_CNT : These bits indicate the number of Bytes in the transmit FIFO
bits : 8 - 11 (4 bit)
access : read-only
SIM Receive FIFO Counter Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RCV_CNT : These bits indicate the number of Byte can be written into the receive FIFO
bits : 0 - 8 (9 bit)
access : read-only
SIM Receive FIFO Write Pointer Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RCV_WPTR : These bits indicate the receive FIFO Write pointer.
bits : 0 - 8 (9 bit)
access : read-only
SIM Receive FIFO Read Pointer Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RCV_RPTR : These bits indicate the receiver FIFO read pointer.
bits : 0 - 8 (9 bit)
access : read-only
SIM Port 1 Detect Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDIM1 : SIM Detect Interrupt Mask Port 1. Interrupt mask for the sdi1 interrupt flag.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SDIM1_0
SDI1 enabled
0x1 : SDIM1_1
SDI1 masked (default)
End of enumeration elements list.
SDI1 : SIM Detect Interrupt Flag Port 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SDI1_0
No insertion or removal of SIM card detected on Port 1(default)
0x1 : SDI1_1
Insertion or removal of SIM card detected on Port 1
End of enumeration elements list.
SPDP1 : SIMPD1 input pin status
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : SPDP1_0
SIMPD1 pin is logic low
0x1 : SPDP1_1
SIMPD1 pin is logic high
End of enumeration elements list.
SPDS1 : SIM Presence Detect Select Port 1
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SPDS1_0
Falling edge of SIMPD1 Input (default)
0x1 : SPDS1_1
Rising edge of SIMPD1 Input
End of enumeration elements list.
SIM Transmit Buffer Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XMT : Transmit Buffer. Write to the next available location in the transmit buffer.
bits : 0 - 7 (8 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.