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IOMUXC_LPSR_GPR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x5C byte (0x0)
mem_usage : registers
protection : not protected

Registers

IOMUXC_LPSR_GPR0

IOMUXC_LPSR_GPR4

IOMUXC_LPSR_GPR5

IOMUXC_LPSR_GPR6

IOMUXC_LPSR_GPR7

IOMUXC_LPSR_GPR8

IOMUXC_LPSR_GPR9

IOMUXC_LPSR_GPR10

IOMUXC_LPSR_GPR11

IOMUXC_LPSR_GPR12

IOMUXC_LPSR_GPR13

IOMUXC_LPSR_GPR14

IOMUXC_LPSR_GPR15

IOMUXC_LPSR_GPR1

IOMUXC_LPSR_GPR16

IOMUXC_LPSR_GPR17

IOMUXC_LPSR_GPR18

IOMUXC_LPSR_GPR19

IOMUXC_LPSR_GPR20

IOMUXC_LPSR_GPR21

IOMUXC_LPSR_GPR22

IOMUXC_LPSR_GPR2

IOMUXC_LPSR_GPR3


IOMUXC_LPSR_GPR0

IOMUXC_LPSR General Purpose Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR0 IOMUXC_LPSR_GPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP

GP : Common bits can be R/W freely
bits : 0 - 31 (32 bit)
access : read-write


IOMUXC_LPSR_GPR4

IOMUXC_LPSR General Purpose Register 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR4 IOMUXC_LPSR_GPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP RO

GP : Common bits can be R/W freely
bits : 0 - 15 (16 bit)
access : read-write

RO : Read only bits, always 16'h0
bits : 16 - 31 (16 bit)
access : read-write


IOMUXC_LPSR_GPR5

IOMUXC_LPSR General Purpose Register 5
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR5 IOMUXC_LPSR_GPR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP

GP : Common bits can be R/W freely
bits : 0 - 31 (32 bit)
access : read-write


IOMUXC_LPSR_GPR6

IOMUXC_LPSR General Purpose Register 6
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR6 IOMUXC_LPSR_GPR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP

GP : Common bits can be R/W freely
bits : 0 - 31 (32 bit)
access : read-write


IOMUXC_LPSR_GPR7

IOMUXC_LPSR General Purpose Register 7
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR7 IOMUXC_LPSR_GPR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP

GP : Common bits can be R/W freely
bits : 0 - 31 (32 bit)
access : read-write


IOMUXC_LPSR_GPR8

IOMUXC_LPSR General Purpose Register 8
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR8 IOMUXC_LPSR_GPR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP

GP : Common bits can be R/W freely
bits : 0 - 31 (32 bit)
access : read-write


IOMUXC_LPSR_GPR9

IOMUXC_LPSR General Purpose Register 9
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR9 IOMUXC_LPSR_GPR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STICKY

STICKY : Each bit is sticky. Once it's written to 1'b1, it cannot be written back to 1'b0.
bits : 0 - 31 (32 bit)
access : read-write


IOMUXC_LPSR_GPR10

IOMUXC_LPSR General Purpose Register 10
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR10 IOMUXC_LPSR_GPR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK STICKY

LOCK : These are lock type bits
bits : 0 - 15 (16 bit)
access : read-write

STICKY : Bits [31:16] are lock bits for [15:0]
bits : 16 - 31 (16 bit)
access : read-write


IOMUXC_LPSR_GPR11

IOMUXC_LPSR General Purpose Register 11
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR11 IOMUXC_LPSR_GPR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK STICKY

LOCK : These are lock type bits
bits : 0 - 15 (16 bit)
access : read-write

STICKY : Bits [31:16] are lock bits for [15:0]
bits : 16 - 31 (16 bit)
access : read-write


IOMUXC_LPSR_GPR12

IOMUXC_LPSR General Purpose Register 12
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR12 IOMUXC_LPSR_GPR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP

GP : Common bits can be R/W freely
bits : 0 - 31 (32 bit)
access : read-write


IOMUXC_LPSR_GPR13

IOMUXC_LPSR General Purpose Register 13
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR13 IOMUXC_LPSR_GPR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP RO

GP : Common bits can be R/W freely
bits : 0 - 15 (16 bit)
access : read-write

RO : Read only bits, always 16'h0
bits : 16 - 31 (16 bit)
access : read-write


IOMUXC_LPSR_GPR14

IOMUXC_LPSR General Purpose Register 14
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR14 IOMUXC_LPSR_GPR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP

GP : Common bits can be R/W freely
bits : 0 - 31 (32 bit)
access : read-write


IOMUXC_LPSR_GPR15

IOMUXC_LPSR General Purpose Register 15
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR15 IOMUXC_LPSR_GPR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP

GP : Common bits can be R/W freely
bits : 0 - 31 (32 bit)
access : read-write


IOMUXC_LPSR_GPR1

IOMUXC_LPSR General Purpose Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR1 IOMUXC_LPSR_GPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP

GP : Common bits can be R/W freely
bits : 0 - 31 (32 bit)
access : read-write


IOMUXC_LPSR_GPR16

IOMUXC_LPSR General Purpose Register 16
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR16 IOMUXC_LPSR_GPR16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP

GP : Common bits can be R/W freely
bits : 0 - 31 (32 bit)
access : read-write


IOMUXC_LPSR_GPR17

IOMUXC_LPSR General Purpose Register 17
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR17 IOMUXC_LPSR_GPR17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP

GP : Common bits can be R/W freely
bits : 0 - 31 (32 bit)
access : read-write


IOMUXC_LPSR_GPR18

IOMUXC_LPSR General Purpose Register 18
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR18 IOMUXC_LPSR_GPR18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP

GP : Common bits can be R/W freely
bits : 0 - 31 (32 bit)
access : read-write


IOMUXC_LPSR_GPR19

IOMUXC_LPSR General Purpose Register 19
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR19 IOMUXC_LPSR_GPR19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP

GP : Common bits can be R/W freely
bits : 0 - 31 (32 bit)
access : read-write


IOMUXC_LPSR_GPR20

IOMUXC_LPSR General Purpose Register 20
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR20 IOMUXC_LPSR_GPR20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO1_IO08_DSE GPIO1_IO08_SRE GPIO1_IO08_HYS GPIO1_IO08_PE GPIO1_IO08_PS GPIO1_IO08_MUX_CTL GPIO1_IO09_DSE GPIO1_IO09_SRE GPIO1_IO09_HYS GPIO1_IO09_PE GPIO1_IO09_PS GPIO1_IO09_MUX_CTL GPIO1_IO10_DSE GPIO1_IO10_SRE GPIO1_IO10_HYS GPIO1_IO10_PE GPIO1_IO10_PS GPIO1_IO10_MUX_CTL GPIO1_IO11_DSE GPIO1_IO11_SRE GPIO1_IO11_HYS GPIO1_IO11_PE GPIO1_IO11_PS GPIO1_IO11_MUX_CTL

GPIO1_IO08_DSE : Drive Strength Field Select one out of next values for pad: GPIO1_IO08
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : GPIO1_IO08_DSE_0

DSE_0_X1 - X1

0x1 : GPIO1_IO08_DSE_1

DSE_1_X1 - X2

0x2 : GPIO1_IO08_DSE_2

DSE_2_X1 - X4

0x3 : GPIO1_IO08_DSE_3

DSE_3_X1 - X6

End of enumeration elements list.

GPIO1_IO08_SRE : Slew Rate Field Select one out of next values for pad: GPIO1_IO08
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO08_SRE_0

SRE_0_Fast_Slew_Rate - Fast Slew Rate

0x1 : GPIO1_IO08_SRE_1

SRE_1_Slow_Slew_Rate - Slow Slew Rate

End of enumeration elements list.

GPIO1_IO08_HYS : Hyst. Enable Field Select one out of next values for pad: GPIO1_IO08
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO08_HYS_0

HYS_0_Hysteresis_Disabled - Hysteresis Disabled

0x1 : GPIO1_IO08_HYS_1

HYS_1_Hysteresis_Enabled - Hysteresis Enable

End of enumeration elements list.

GPIO1_IO08_PE : Pull Enable Field Select one out of next values for pad: GPIO1_IO08
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO08_PE_0

PE_0_Pull_Disabled - Pull Disabled

0x1 : GPIO1_IO08_PE_1

PE_1_Pull_Enabled - Pull Enabled

End of enumeration elements list.

GPIO1_IO08_PS : Pull Select Field Select one out of next values for pad: GPIO1_IO08
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

0 : GPIO1_IO08_PS_0

PS_0_100K_PD - 100K PD

0x1 : GPIO1_IO08_PS_1

PS_1_5K_PU - 5K PU

0x2 : GPIO1_IO08_PS_2

PS_2_47K_PU - 47K PU

0x3 : GPIO1_IO08_PS_3

PS_3_100K_PU - 100K PU

End of enumeration elements list.

GPIO1_IO08_MUX_CTL : Mux control for PAD
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO08_MUX_CTL_0

Pad control from SOC IOMUX

0x1 : GPIO1_IO08_MUX_CTL_1

Pad control from LPSR GPR

End of enumeration elements list.

GPIO1_IO09_DSE : Drive Strength Field Select one out of next values for pad: GPIO1_IO09
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : GPIO1_IO09_DSE_0

DSE_0_X1 - X1

0x1 : GPIO1_IO09_DSE_1

DSE_1_X1 - X2

0x2 : GPIO1_IO09_DSE_2

DSE_2_X1 - X4

0x3 : GPIO1_IO09_DSE_3

DSE_3_X1 - X6

End of enumeration elements list.

GPIO1_IO09_SRE : Slew Rate Field Select one out of next values for pad: GPIO1_IO09
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO09_SRE_0

SRE_0_Fast_Slew_Rate - Fast Slew Rate

0x1 : GPIO1_IO09_SRE_1

SRE_1_Slow_Slew_Rate - Slow Slew Rate

End of enumeration elements list.

GPIO1_IO09_HYS : Hyst. Enable Field Select one out of next values for pad: GPIO1_IO09
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO09_HYS_0

HYS_0_Hysteresis_Disabled - Hysteresis Disabled

0x1 : GPIO1_IO09_HYS_1

HYS_1_Hysteresis_Enabled - Hysteresis Enable

End of enumeration elements list.

GPIO1_IO09_PE : Pull Enable Field Select one out of next values for pad: GPIO1_IO09
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO09_PE_0

PE_0_Pull_Disabled - Pull Disabled

0x1 : GPIO1_IO09_PE_1

PE_1_Pull_Enabled - Pull Enabled

End of enumeration elements list.

GPIO1_IO09_PS : Pull Select Field Select one out of next values for pad: GPIO1_IO09
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

0 : GPIO1_IO09_PS_0

PS_0_100K_PD - 100K PD

0x1 : GPIO1_IO09_PS_1

PS_1_5K_PU - 5K PU

0x2 : GPIO1_IO09_PS_2

PS_2_47K_PU - 47K PU

0x3 : GPIO1_IO09_PS_3

PS_3_100K_PU - 100K PU

End of enumeration elements list.

GPIO1_IO09_MUX_CTL : Mux control for PAD
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO09_MUX_CTL_0

Pad control from SOC IOMUX

0x1 : GPIO1_IO09_MUX_CTL_1

Pad control from LPSR GPR

End of enumeration elements list.

GPIO1_IO10_DSE : Drive Strength Field Select one out of next values for pad: GPIO1_IO10
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : GPIO1_IO10_DSE_0

DSE_0_X1 - X1

0x1 : GPIO1_IO10_DSE_1

DSE_1_X1 - X2

0x2 : GPIO1_IO10_DSE_2

DSE_2_X1 - X4

0x3 : GPIO1_IO10_DSE_3

DSE_3_X1 - X6

End of enumeration elements list.

GPIO1_IO10_SRE : Slew Rate Field Select one out of next values for pad: GPIO1_IO10
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO10_SRE_0

SRE_0_Fast_Slew_Rate - Fast Slew Rate

0x1 : GPIO1_IO10_SRE_1

SRE_1_Slow_Slew_Rate - Slow Slew Rate

End of enumeration elements list.

GPIO1_IO10_HYS : Hyst. Enable Field Select one out of next values for pad: GPIO1_IO10
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO10_HYS_0

HYS_0_Hysteresis_Disabled - Hysteresis Disabled

0x1 : GPIO1_IO10_HYS_1

HYS_1_Hysteresis_Enabled - Hysteresis Enable

End of enumeration elements list.

GPIO1_IO10_PE : Pull Enable Field Select one out of next values for pad: GPIO1_IO10
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO10_PE_0

PE_0_Pull_Disabled - Pull Disabled

0x1 : GPIO1_IO10_PE_1

PE_1_Pull_Enabled - Pull Enabled

End of enumeration elements list.

GPIO1_IO10_PS : Pull Select Field Select one out of next values for pad: GPIO1_IO10
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

0 : GPIO1_IO10_PS_0

PS_0_100K_PD - 100K PD

0x1 : GPIO1_IO10_PS_1

PS_1_5K_PU - 5K PU

0x2 : GPIO1_IO10_PS_2

PS_2_47K_PU - 47K PU

0x3 : GPIO1_IO10_PS_3

PS_3_100K_PU - 100K PU

End of enumeration elements list.

GPIO1_IO10_MUX_CTL : Mux control for PAD
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO10_MUX_CTL_0

Pad control from SOC IOMUX

0x1 : GPIO1_IO10_MUX_CTL_1

Pad control from LPSR GPR

End of enumeration elements list.

GPIO1_IO11_DSE : Drive Strength Field Select one out of next values for pad: GPIO1_IO11
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : GPIO1_IO11_DSE_0

DSE_0_X1 - X1

0x1 : GPIO1_IO11_DSE_1

DSE_1_X1 - X2

0x2 : GPIO1_IO11_DSE_2

DSE_2_X1 - X4

0x3 : GPIO1_IO11_DSE_3

DSE_3_X1 - X6

End of enumeration elements list.

GPIO1_IO11_SRE : Slew Rate Field Select one out of next values for pad: GPIO1_IO11
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO11_SRE_0

SRE_0_Fast_Slew_Rate - Fast Slew Rate

0x1 : GPIO1_IO11_SRE_1

SRE_1_Slow_Slew_Rate - Slow Slew Rate

End of enumeration elements list.

GPIO1_IO11_HYS : Hyst. Enable Field Select one out of next values for pad: GPIO1_IO11
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO11_HYS_0

HYS_0_Hysteresis_Disabled - Hysteresis Disabled

0x1 : GPIO1_IO11_HYS_1

HYS_1_Hysteresis_Enabled - Hysteresis Enable

End of enumeration elements list.

GPIO1_IO11_PE : Pull Enable Field Select one out of next values for pad: GPIO1_IO11
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO11_PE_0

PE_0_Pull_Disabled - Pull Disabled

0x1 : GPIO1_IO11_PE_1

PE_1_Pull_Enabled - Pull Enabled

End of enumeration elements list.

GPIO1_IO11_PS : Pull Select Field Select one out of next values for pad: GPIO1_IO11
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0 : GPIO1_IO11_PS_0

PS_0_100K_PD - 100K PD

0x1 : GPIO1_IO11_PS_1

PS_1_5K_PU - 5K PU

0x2 : GPIO1_IO11_PS_2

PS_2_47K_PU - 47K PU

0x3 : GPIO1_IO11_PS_3

PS_3_100K_PU - 100K PU

End of enumeration elements list.

GPIO1_IO11_MUX_CTL : Mux control for PAD
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO11_MUX_CTL_0

Pad control from SOC IOMUX

0x1 : GPIO1_IO11_MUX_CTL_1

Pad control from LPSR GPR

End of enumeration elements list.


IOMUXC_LPSR_GPR21

IOMUXC_LPSR General Purpose Register 21
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR21 IOMUXC_LPSR_GPR21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO1_IO12_DSE GPIO1_IO12_SRE GPIO1_IO12_HYS GPIO1_IO12_PE GPIO1_IO12_PS GPIO1_IO12_MUX_CTL GPIO1_IO13_DSE GPIO1_IO13_SRE GPIO1_IO13_HYS GPIO1_IO13_PE GPIO1_IO13_PS GPIO1_IO13_MUX_CTL GPIO1_IO14_DSE GPIO1_IO14_SRE GPIO1_IO14_HYS GPIO1_IO14_PE GPIO1_IO14_PS GPIO1_IO14_MUX_CTL GPIO1_IO15_DSE GPIO1_IO15_SRE GPIO1_IO15_HYS GPIO1_IO15_PE GPIO1_IO15_PS GPIO1_IO15_MUX_CTL

GPIO1_IO12_DSE : Drive Strength Field Select one out of next values for pad: GPIO1_IO12
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : GPIO1_IO12_DSE_0

DSE_0_X1 - X1

0x1 : GPIO1_IO12_DSE_1

DSE_1_X1 - X2

0x2 : GPIO1_IO12_DSE_2

DSE_2_X1 - X4

0x3 : GPIO1_IO12_DSE_3

DSE_3_X1 - X6

End of enumeration elements list.

GPIO1_IO12_SRE : Slew Rate Field Select one out of next values for pad: GPIO1_IO12
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO12_SRE_0

SRE_0_Fast_Slew_Rate - Fast Slew Rate

0x1 : GPIO1_IO12_SRE_1

SRE_1_Slow_Slew_Rate - Slow Slew Rate

End of enumeration elements list.

GPIO1_IO12_HYS : Hyst. Enable Field Select one out of next values for pad: GPIO1_IO12
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO12_HYS_0

HYS_0_Hysteresis_Disabled - Hysteresis Disabled

0x1 : GPIO1_IO12_HYS_1

HYS_1_Hysteresis_Enabled - Hysteresis Enable

End of enumeration elements list.

GPIO1_IO12_PE : Pull Enable Field Select one out of next values for pad: GPIO1_IO12
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO12_PE_0

PE_0_Pull_Disabled - Pull Disabled

0x1 : GPIO1_IO12_PE_1

PE_1_Pull_Enabled - Pull Enabled

End of enumeration elements list.

GPIO1_IO12_PS : Pull Select Field Select one out of next values for pad: GPIO1_IO12
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

0 : GPIO1_IO12_PS_0

PS_0_100K_PD - 100K PD

0x1 : GPIO1_IO12_PS_1

PS_1_5K_PU - 5K PU

0x2 : GPIO1_IO12_PS_2

PS_2_47K_PU - 47K PU

0x3 : GPIO1_IO12_PS_3

PS_3_100K_PU - 100K PU

End of enumeration elements list.

GPIO1_IO12_MUX_CTL : Mux control for PAD
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO12_MUX_CTL_0

Pad control from SOC IOMUX

0x1 : GPIO1_IO12_MUX_CTL_1

Pad control from LPSR GPR

End of enumeration elements list.

GPIO1_IO13_DSE : Drive Strength Field Select one out of next values for pad: GPIO1_IO13
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : GPIO1_IO13_DSE_0

DSE_0_X1 - X1

0x1 : GPIO1_IO13_DSE_1

DSE_1_X1 - X2

0x2 : GPIO1_IO13_DSE_2

DSE_2_X1 - X4

0x3 : GPIO1_IO13_DSE_3

DSE_3_X1 - X6

End of enumeration elements list.

GPIO1_IO13_SRE : Slew Rate Field Select one out of next values for pad: GPIO1_IO13
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO13_SRE_0

SRE_0_Fast_Slew_Rate - Fast Slew Rate

0x1 : GPIO1_IO13_SRE_1

SRE_1_Slow_Slew_Rate - Slow Slew Rate

End of enumeration elements list.

GPIO1_IO13_HYS : Hyst. Enable Field Select one out of next values for pad: GPIO1_IO13
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO13_HYS_0

HYS_0_Hysteresis_Disabled - Hysteresis Disabled

0x1 : GPIO1_IO13_HYS_1

HYS_1_Hysteresis_Enabled - Hysteresis Enable

End of enumeration elements list.

GPIO1_IO13_PE : Pull Enable Field Select one out of next values for pad: GPIO1_IO13
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO13_PE_0

PE_0_Pull_Disabled - Pull Disabled

0x1 : GPIO1_IO13_PE_1

PE_1_Pull_Enabled - Pull Enabled

End of enumeration elements list.

GPIO1_IO13_PS : Pull Select Field Select one out of next values for pad: GPIO1_IO13
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

0 : GPIO1_IO13_PS_0

PS_0_100K_PD - 100K PD

0x1 : GPIO1_IO13_PS_1

PS_1_5K_PU - 5K PU

0x2 : GPIO1_IO13_PS_2

PS_2_47K_PU - 47K PU

0x3 : GPIO1_IO13_PS_3

PS_3_100K_PU - 100K PU

End of enumeration elements list.

GPIO1_IO13_MUX_CTL : Mux control for PAD
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO13_MUX_CTL_0

Pad control from SOC IOMUX

0x1 : GPIO1_IO13_MUX_CTL_1

Pad control from LPSR GPR

End of enumeration elements list.

GPIO1_IO14_DSE : Drive Strength Field Select one out of next values for pad: GPIO1_IO14
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : GPIO1_IO14_DSE_0

DSE_0_X1 - X1

0x1 : GPIO1_IO14_DSE_1

DSE_1_X1 - X2

0x2 : GPIO1_IO14_DSE_2

DSE_2_X1 - X4

0x3 : GPIO1_IO14_DSE_3

DSE_3_X1 - X6

End of enumeration elements list.

GPIO1_IO14_SRE : Slew Rate Field Select one out of next values for pad: GPIO1_IO14
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO14_SRE_0

SRE_0_Fast_Slew_Rate - Fast Slew Rate

0x1 : GPIO1_IO14_SRE_1

SRE_1_Slow_Slew_Rate - Slow Slew Rate

End of enumeration elements list.

GPIO1_IO14_HYS : Hyst. Enable Field Select one out of next values for pad: GPIO1_IO14
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO14_HYS_0

HYS_0_Hysteresis_Disabled - Hysteresis Disabled

0x1 : GPIO1_IO14_HYS_1

HYS_1_Hysteresis_Enabled - Hysteresis Enable

End of enumeration elements list.

GPIO1_IO14_PE : Pull Enable Field Select one out of next values for pad: GPIO1_IO14
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO14_PE_0

PE_0_Pull_Disabled - Pull Disabled

0x1 : GPIO1_IO14_PE_1

PE_1_Pull_Enabled - Pull Enabled

End of enumeration elements list.

GPIO1_IO14_PS : Pull Select Field Select one out of next values for pad: GPIO1_IO14
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

0 : GPIO1_IO14_PS_0

PS_0_100K_PD - 100K PD

0x1 : GPIO1_IO14_PS_1

PS_1_5K_PU - 5K PU

0x2 : GPIO1_IO14_PS_2

PS_2_47K_PU - 47K PU

0x3 : GPIO1_IO14_PS_3

PS_3_100K_PU - 100K PU

End of enumeration elements list.

GPIO1_IO14_MUX_CTL : Mux control for PAD
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO14_MUX_CTL_0

Pad control from SOC IOMUX

0x1 : GPIO1_IO14_MUX_CTL_1

Pad control from LPSR GPR

End of enumeration elements list.

GPIO1_IO15_DSE : Drive Strength Field Select one out of next values for pad: GPIO1_IO15
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : GPIO1_IO15_DSE_0

DSE_0_X1 - X1

0x1 : GPIO1_IO15_DSE_1

DSE_1_X1 - X2

0x2 : GPIO1_IO15_DSE_2

DSE_2_X1 - X4

0x3 : GPIO1_IO15_DSE_3

DSE_3_X1 - X6

End of enumeration elements list.

GPIO1_IO15_SRE : Slew Rate Field Select one out of next values for pad: GPIO1_IO15
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO15_SRE_0

SRE_0_Fast_Slew_Rate - Fast Slew Rate

0x1 : GPIO1_IO15_SRE_1

SRE_1_Slow_Slew_Rate - Slow Slew Rate

End of enumeration elements list.

GPIO1_IO15_HYS : Hyst. Enable Field Select one out of next values for pad: GPIO1_IO15
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO15_HYS_0

HYS_0_Hysteresis_Disabled - Hysteresis Disabled

0x1 : GPIO1_IO15_HYS_1

HYS_1_Hysteresis_Enabled - Hysteresis Enable

End of enumeration elements list.

GPIO1_IO15_PE : Pull Enable Field Select one out of next values for pad: GPIO1_IO15
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO15_PE_0

PE_0_Pull_Disabled - Pull Disabled

0x1 : GPIO1_IO15_PE_1

PE_1_Pull_Enabled - Pull Enabled

End of enumeration elements list.

GPIO1_IO15_PS : Pull Select Field Select one out of next values for pad: GPIO1_IO15
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0 : GPIO1_IO15_PS_0

PS_0_100K_PD - 100K PD

0x1 : GPIO1_IO15_PS_1

PS_1_5K_PU - 5K PU

0x2 : GPIO1_IO15_PS_2

PS_2_47K_PU - 47K PU

0x3 : GPIO1_IO15_PS_3

PS_3_100K_PU - 100K PU

End of enumeration elements list.

GPIO1_IO15_MUX_CTL : Mux control for PAD
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : GPIO1_IO15_MUX_CTL_0

Pad control from SOC IOMUX

0x1 : GPIO1_IO15_MUX_CTL_1

Pad control from LPSR GPR

End of enumeration elements list.


IOMUXC_LPSR_GPR22

IOMUXC_LPSR General Purpose Register 22
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR22 IOMUXC_LPSR_GPR22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP RO

GP : Common bits can be R/W freely
bits : 0 - 15 (16 bit)
access : read-write

RO : Read only bits, always 16'h0
bits : 16 - 31 (16 bit)
access : read-write


IOMUXC_LPSR_GPR2

IOMUXC_LPSR General Purpose Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR2 IOMUXC_LPSR_GPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP

GP : Common bits can be R/W freely
bits : 0 - 31 (32 bit)
access : read-write


IOMUXC_LPSR_GPR3

IOMUXC_LPSR General Purpose Register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOMUXC_LPSR_GPR3 IOMUXC_LPSR_GPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP RO

GP : Common bits can be R/W freely
bits : 0 - 15 (16 bit)
access : read-write

RO : Read only bits, always 16'h0
bits : 16 - 31 (16 bit)
access : read-write



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