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address_offset : 0x0 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection : not protected
Anadig 24M Oscillator Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL_24M_PWD : This field powers down the 24M crystal oscillator if set true.
bits : 0 - 0 (1 bit)
access : read-write
XTAL_24M_EN : This field controls the clock gate at the output of the oscillator. 1 = enabled
bits : 1 - 1 (1 bit)
access : read-write
OSC_XTALOK : Status bit which signals that the output of the 24MHz crystal oscillator is stable.
bits : 2 - 2 (1 bit)
access : read-only
OSC_XTALOK_EN : Enable the xtalok detection circuitry.
bits : 3 - 3 (1 bit)
access : read-write
CLKGATE_CTRL : This bit allows disabling the clock gate (always un-gated) for the xtal 24MHz clock that clocks the digital logic in the analog block
bits : 4 - 4 (1 bit)
access : read-write
CLKGATE_DELAY : This field specifies the delay between powering up the xtal 24MHz clock and release the clock to the digital logic inside the analog block
bits : 5 - 7 (3 bit)
access : read-write
RCOSC_CG_OVERRIDE : For debug purposes only
bits : 8 - 8 (1 bit)
access : read-write
XTALOSC_PWRUP_DELAY : Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use
bits : 9 - 10 (2 bit)
access : read-write
XTALOSC_PWRUP_STAT : Status of the 24MHz xtal oscillator. 0 - not stable; 1 - Stable and ready to use.
bits : 11 - 11 (1 bit)
access : read-only
OSC_SEL : Select the source for the 24MHz clock. 0 - xtal osc.; 1 - RC osc.
bits : 12 - 12 (1 bit)
access : read-write
RC_OSC_EN : RC osc. enable control. 0- turn off the RC osc. 24MHz clock; 1- turn on the RC osc. clock.
bits : 13 - 13 (1 bit)
access : read-write
XTAL_MISC : Misc control bits for 24m xtal osc
bits : 15 - 30 (16 bit)
access : read-write
Anadig 24MHz RC Osc. config0 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNE_START : Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.
bits : 0 - 0 (1 bit)
access : read-write
TUNE_ENABLE : Enables the tuning logic to calculate new RC tuning values
bits : 1 - 1 (1 bit)
access : read-write
TUNE_BYPASS : Bypasses any calculated RC tuning value and uses the programmed register value.
bits : 2 - 2 (1 bit)
access : read-write
TUNE_INVERT : Invert the stepping of the calculated RC tuning value.
bits : 3 - 3 (1 bit)
access : read-write
RC_OSC_PROG : RC osc. tuning values.
bits : 4 - 11 (8 bit)
access : read-write
HYST_PLUS : Positive hysteresis value
bits : 12 - 15 (4 bit)
access : read-write
HYST_MINUS : Negative hysteresis value
bits : 16 - 19 (4 bit)
access : read-write
RC_OSC_PROG_CUR : The current tuning value in use.
bits : 24 - 31 (8 bit)
access : read-write
Anadig 24MHz RC Osc. config0 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNE_START : Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.
bits : 0 - 0 (1 bit)
access : read-write
TUNE_ENABLE : Enables the tuning logic to calculate new RC tuning values
bits : 1 - 1 (1 bit)
access : read-write
TUNE_BYPASS : Bypasses any calculated RC tuning value and uses the programmed register value.
bits : 2 - 2 (1 bit)
access : read-write
TUNE_INVERT : Invert the stepping of the calculated RC tuning value.
bits : 3 - 3 (1 bit)
access : read-write
RC_OSC_PROG : RC osc. tuning values.
bits : 4 - 11 (8 bit)
access : read-write
HYST_PLUS : Positive hysteresis value
bits : 12 - 15 (4 bit)
access : read-write
HYST_MINUS : Negative hysteresis value
bits : 16 - 19 (4 bit)
access : read-write
RC_OSC_PROG_CUR : The current tuning value in use.
bits : 24 - 31 (8 bit)
access : read-write
Anadig 24MHz RC Osc. config0 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNE_START : Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.
bits : 0 - 0 (1 bit)
access : read-write
TUNE_ENABLE : Enables the tuning logic to calculate new RC tuning values
bits : 1 - 1 (1 bit)
access : read-write
TUNE_BYPASS : Bypasses any calculated RC tuning value and uses the programmed register value.
bits : 2 - 2 (1 bit)
access : read-write
TUNE_INVERT : Invert the stepping of the calculated RC tuning value.
bits : 3 - 3 (1 bit)
access : read-write
RC_OSC_PROG : RC osc. tuning values.
bits : 4 - 11 (8 bit)
access : read-write
HYST_PLUS : Positive hysteresis value
bits : 12 - 15 (4 bit)
access : read-write
HYST_MINUS : Negative hysteresis value
bits : 16 - 19 (4 bit)
access : read-write
RC_OSC_PROG_CUR : The current tuning value in use.
bits : 24 - 31 (8 bit)
access : read-write
Anadig 24MHz RC Osc. config0 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNE_START : Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.
bits : 0 - 0 (1 bit)
access : read-write
TUNE_ENABLE : Enables the tuning logic to calculate new RC tuning values
bits : 1 - 1 (1 bit)
access : read-write
TUNE_BYPASS : Bypasses any calculated RC tuning value and uses the programmed register value.
bits : 2 - 2 (1 bit)
access : read-write
TUNE_INVERT : Invert the stepping of the calculated RC tuning value.
bits : 3 - 3 (1 bit)
access : read-write
RC_OSC_PROG : RC osc. tuning values.
bits : 4 - 11 (8 bit)
access : read-write
HYST_PLUS : Positive hysteresis value
bits : 12 - 15 (4 bit)
access : read-write
HYST_MINUS : Negative hysteresis value
bits : 16 - 19 (4 bit)
access : read-write
RC_OSC_PROG_CUR : The current tuning value in use.
bits : 24 - 31 (8 bit)
access : read-write
Anadig 24MHz RC Osc. config1 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_RC_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write
COUNT_RC_CUR : The current tuning value in use.
bits : 20 - 31 (12 bit)
access : read-write
Anadig 24MHz RC Osc. config1 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_RC_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write
COUNT_RC_CUR : The current tuning value in use.
bits : 20 - 31 (12 bit)
access : read-write
Anadig 24MHz RC Osc. config1 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_RC_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write
COUNT_RC_CUR : The current tuning value in use.
bits : 20 - 31 (12 bit)
access : read-write
Anadig 24MHz RC Osc. config1 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_RC_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write
COUNT_RC_CUR : The current tuning value in use.
bits : 20 - 31 (12 bit)
access : read-write
Anadig 24MHz RC Osc. config2 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_1M_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write
ENABLE_1M : Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
bits : 16 - 16 (1 bit)
access : read-write
MUX_1M : Mux the corrected or uncorrected 1MHz clock to the output. 0 - .
bits : 17 - 17 (1 bit)
access : read-write
CLK_1M_ERR_FL : Flag indicates that the count_1m count wasn't reached within 1 32KHz period
bits : 31 - 31 (1 bit)
access : read-write
Anadig 24MHz RC Osc. config2 Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_1M_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write
ENABLE_1M : Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
bits : 16 - 16 (1 bit)
access : read-write
MUX_1M : Mux the corrected or uncorrected 1MHz clock to the output. 0 - .
bits : 17 - 17 (1 bit)
access : read-write
CLK_1M_ERR_FL : Flag indicates that the count_1m count wasn't reached within 1 32KHz period
bits : 31 - 31 (1 bit)
access : read-write
Anadig 24MHz RC Osc. config2 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_1M_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write
ENABLE_1M : Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
bits : 16 - 16 (1 bit)
access : read-write
MUX_1M : Mux the corrected or uncorrected 1MHz clock to the output. 0 - .
bits : 17 - 17 (1 bit)
access : read-write
CLK_1M_ERR_FL : Flag indicates that the count_1m count wasn't reached within 1 32KHz period
bits : 31 - 31 (1 bit)
access : read-write
Anadig 24MHz RC Osc. config2 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_1M_TRG : The target count used to tune the RC OSC frequency
bits : 0 - 11 (12 bit)
access : read-write
ENABLE_1M : Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
bits : 16 - 16 (1 bit)
access : read-write
MUX_1M : Mux the corrected or uncorrected 1MHz clock to the output. 0 - .
bits : 17 - 17 (1 bit)
access : read-write
CLK_1M_ERR_FL : Flag indicates that the count_1m count wasn't reached within 1 32KHz period
bits : 31 - 31 (1 bit)
access : read-write
Anadig 24M Oscillator Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL_24M_PWD : This field powers down the 24M crystal oscillator if set true.
bits : 0 - 0 (1 bit)
access : read-write
XTAL_24M_EN : This field controls the clock gate at the output of the oscillator. 1 = enabled
bits : 1 - 1 (1 bit)
access : read-write
OSC_XTALOK : Status bit which signals that the output of the 24MHz crystal oscillator is stable.
bits : 2 - 2 (1 bit)
access : read-only
OSC_XTALOK_EN : Enable the xtalok detection circuitry.
bits : 3 - 3 (1 bit)
access : read-write
CLKGATE_CTRL : This bit allows disabling the clock gate (always un-gated) for the xtal 24MHz clock that clocks the digital logic in the analog block
bits : 4 - 4 (1 bit)
access : read-write
CLKGATE_DELAY : This field specifies the delay between powering up the xtal 24MHz clock and release the clock to the digital logic inside the analog block
bits : 5 - 7 (3 bit)
access : read-write
RCOSC_CG_OVERRIDE : For debug purposes only
bits : 8 - 8 (1 bit)
access : read-write
XTALOSC_PWRUP_DELAY : Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use
bits : 9 - 10 (2 bit)
access : read-write
XTALOSC_PWRUP_STAT : Status of the 24MHz xtal oscillator. 0 - not stable; 1 - Stable and ready to use.
bits : 11 - 11 (1 bit)
access : read-only
OSC_SEL : Select the source for the 24MHz clock. 0 - xtal osc.; 1 - RC osc.
bits : 12 - 12 (1 bit)
access : read-write
RC_OSC_EN : RC osc. enable control. 0- turn off the RC osc. 24MHz clock; 1- turn on the RC osc. clock.
bits : 13 - 13 (1 bit)
access : read-write
XTAL_MISC : Misc control bits for 24m xtal osc
bits : 15 - 30 (16 bit)
access : read-write
32K Oscillator Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RTC_XTAL_SOURCE : This field indicates which chip source is being used for the rtc clock
bits : 0 - 0 (1 bit)
access : read-only
32K Oscillator Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RTC_XTAL_SOURCE : This field indicates which chip source is being used for the rtc clock
bits : 0 - 0 (1 bit)
access : read-only
32K Oscillator Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RTC_XTAL_SOURCE : This field indicates which chip source is being used for the rtc clock
bits : 0 - 0 (1 bit)
access : read-only
32K Oscillator Control Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RTC_XTAL_SOURCE : This field indicates which chip source is being used for the rtc clock
bits : 0 - 0 (1 bit)
access : read-only
Anadig 24M Oscillator Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL_24M_PWD : This field powers down the 24M crystal oscillator if set true.
bits : 0 - 0 (1 bit)
access : read-write
XTAL_24M_EN : This field controls the clock gate at the output of the oscillator. 1 = enabled
bits : 1 - 1 (1 bit)
access : read-write
OSC_XTALOK : Status bit which signals that the output of the 24MHz crystal oscillator is stable.
bits : 2 - 2 (1 bit)
access : read-only
OSC_XTALOK_EN : Enable the xtalok detection circuitry.
bits : 3 - 3 (1 bit)
access : read-write
CLKGATE_CTRL : This bit allows disabling the clock gate (always un-gated) for the xtal 24MHz clock that clocks the digital logic in the analog block
bits : 4 - 4 (1 bit)
access : read-write
CLKGATE_DELAY : This field specifies the delay between powering up the xtal 24MHz clock and release the clock to the digital logic inside the analog block
bits : 5 - 7 (3 bit)
access : read-write
RCOSC_CG_OVERRIDE : For debug purposes only
bits : 8 - 8 (1 bit)
access : read-write
XTALOSC_PWRUP_DELAY : Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use
bits : 9 - 10 (2 bit)
access : read-write
XTALOSC_PWRUP_STAT : Status of the 24MHz xtal oscillator. 0 - not stable; 1 - Stable and ready to use.
bits : 11 - 11 (1 bit)
access : read-only
OSC_SEL : Select the source for the 24MHz clock. 0 - xtal osc.; 1 - RC osc.
bits : 12 - 12 (1 bit)
access : read-write
RC_OSC_EN : RC osc. enable control. 0- turn off the RC osc. 24MHz clock; 1- turn on the RC osc. clock.
bits : 13 - 13 (1 bit)
access : read-write
XTAL_MISC : Misc control bits for 24m xtal osc
bits : 15 - 30 (16 bit)
access : read-write
Anadig 24M Oscillator Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL_24M_PWD : This field powers down the 24M crystal oscillator if set true.
bits : 0 - 0 (1 bit)
access : read-write
XTAL_24M_EN : This field controls the clock gate at the output of the oscillator. 1 = enabled
bits : 1 - 1 (1 bit)
access : read-write
OSC_XTALOK : Status bit which signals that the output of the 24MHz crystal oscillator is stable.
bits : 2 - 2 (1 bit)
access : read-only
OSC_XTALOK_EN : Enable the xtalok detection circuitry.
bits : 3 - 3 (1 bit)
access : read-write
CLKGATE_CTRL : This bit allows disabling the clock gate (always un-gated) for the xtal 24MHz clock that clocks the digital logic in the analog block
bits : 4 - 4 (1 bit)
access : read-write
CLKGATE_DELAY : This field specifies the delay between powering up the xtal 24MHz clock and release the clock to the digital logic inside the analog block
bits : 5 - 7 (3 bit)
access : read-write
RCOSC_CG_OVERRIDE : For debug purposes only
bits : 8 - 8 (1 bit)
access : read-write
XTALOSC_PWRUP_DELAY : Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use
bits : 9 - 10 (2 bit)
access : read-write
XTALOSC_PWRUP_STAT : Status of the 24MHz xtal oscillator. 0 - not stable; 1 - Stable and ready to use.
bits : 11 - 11 (1 bit)
access : read-only
OSC_SEL : Select the source for the 24MHz clock. 0 - xtal osc.; 1 - RC osc.
bits : 12 - 12 (1 bit)
access : read-write
RC_OSC_EN : RC osc. enable control. 0- turn off the RC osc. 24MHz clock; 1- turn on the RC osc. clock.
bits : 13 - 13 (1 bit)
access : read-write
XTAL_MISC : Misc control bits for 24m xtal osc
bits : 15 - 30 (16 bit)
access : read-write
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