Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
USB OTG Control 1 Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVER_CUR_DIS : Disable Overcurrent Detection
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : OVER_CUR_DIS_0
Enables overcurrent detection
0x1 : OVER_CUR_DIS_1
Disables overcurrent detection
End of enumeration elements list.
OVER_CUR_POL : Polarity of Overcurrent The polarity of OTGn/OTG2 port overcurrent event
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : OVER_CUR_POL_0
High active (high on this signal represents an overcurrent condition)
0x1 : OVER_CUR_POL_1
Low active (low on this signal represents an overcurrent condition)
End of enumeration elements list.
PWR_POL : Power Polarity This bit should be set according to PMIC Power Pin polarity.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : PWR_POL_0
PMIC Power Pin is Low active.
0x1 : PWR_POL_1
PMIC Power Pin is High active.
End of enumeration elements list.
WIE : Wake-up Interrupt Enable This bit enables or disables the OTGn wake-up interrupt
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : WIE_0
Interrupt Disabled
0x1 : WIE_1
Interrupt Enabled
End of enumeration elements list.
WKUP_SW_EN : Software Wake-up Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : WKUP_SW_EN_0
Disable
0x1 : WKUP_SW_EN_1
Enable
End of enumeration elements list.
WKUP_SW : Software Wake-up
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : WKUP_SW_0
Inactive
0x1 : WKUP_SW_1
Force wake-up
End of enumeration elements list.
WKUP_ID_EN : Wake-up on ID change enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : WKUP_ID_EN_0
Disable
0x1 : WKUP_ID_EN_1
Enable
End of enumeration elements list.
WKUP_VBUS_EN : Wake-up on VBUS change enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : WKUP_VBUS_EN_0
Disable
0x1 : WKUP_VBUS_EN_1
Enable
End of enumeration elements list.
ULPI_PHY_CLK_EN : ULPI PHY clock enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : ULPI_PHY_CLK_EN_0
Disable
0x1 : ULPI_PHY_CLK_EN_1
Enable
End of enumeration elements list.
WKUP_DPDM_EN : Wake-up on DPDM change enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : WKUP_DPDM_EN_0
DPDM changes wake-up to be disabled only when VBUS is 0.
0x1 : WKUP_DPDM_EN_1
(Default) DPDM changes wake-up to be enabled, it is for device only.
End of enumeration elements list.
WIR : Wake-up Interrupt Request This bit indicates that a wake-up interrupt request is received on the OTGn port
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : WIR_0
No wake-up interrupt request received
0x1 : WIR_1
Wake-up Interrupt Request received
End of enumeration elements list.
USB Host HSIC Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSIC_CLK_ON : Force Host HSIC module 480M clock on, even when in Host is in suspend mode.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : HSIC_CLK_ON_0
Inactive
0x1 : HSIC_CLK_ON_1
Active
End of enumeration elements list.
HSIC_EN : Host HSIC enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : HSIC_EN_0
Disabled
0x1 : HSIC_EN_1
Enabled
End of enumeration elements list.
CLK_VLD : Indicating whether Host HSIC clock is valid.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x1 : CLK_VLD_1
Valid
End of enumeration elements list.
USB OTG Control 2 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBUS_SOURCE_SEL : VBUS source select when detect VBUS wakeup event, it is for UTMI PHY only (UH core has no such feature)
bits : 0 - 1 (2 bit)
access : read-write
AUTURESUME_EN : Auto Resume Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : AUTURESUME_EN_0
Default
End of enumeration elements list.
LOWSPEED_EN : Set if AUTURESUME_EN is set and works on low speed.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : LOWSPEED_EN_0
Default
End of enumeration elements list.
UTMI_CLK_VLD : Indicate whether the UTMI clock to the USB PHY is valid. Write 1 to clear
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UTMI_CLK_VLD_0
Default
End of enumeration elements list.
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