\n
address_offset : 0x0 Bytes (0x0)
size : 0x12C byte (0x0)
mem_usage : registers
protection : not protected
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQSn SW PAD Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUE : Pull Up/Down or Keeper Selection Field
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper_Selected
Keeper Selected
0x1 : PUE_1_Pull_Up_Down_Selected
Pull Up/Down Selected
End of enumeration elements list.
PKE : Pull Up/Pull Down/Keeper Enable Field
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PKE_0_Pull_Up_Down_and_Keeper_Disabled
Pull Up/Down and Keeper Disabled
0x1 : PKE_1_Pull_Up_Down_or_Keeper_Enabled
Pull Up/Down or Keeper Enabled
End of enumeration elements list.
PUS : Pull Up/Down Resistance Select Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PUS_0_100_kOhm_Pull_Down
100 kOhm Pull Down
0x1 : PUS_1_47_Kohm_Pull_Up
47 Kohm Pull Up
0x2 : PUS_2_100_kOhm_Pull_Up
100 kOhm Pull Up
0x3 : PUS_3_22_kOhm_Pull_Up
22 kOhm Pull Up
End of enumeration elements list.
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
CRPOINT_TRIM : Crosspoint Adjustment Field
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : CRPOINT_TRIM_0_No_adjustment
No adjustment
0x1 : CRPOINT_TRIM_1__70_mV
-70 mV
0x2 : CRPOINT_TRIM_2__70_mV
+70 mV
0x3 : CRPOINT_TRIM_3__140_mV
+140 mV
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_right_shrink
right shrink
0x2 : DCYCLE_TRIM_2_left_shrink
left shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
SW_PAD_CTL_GRP_PUS SW GRP Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUS : Pull Up/Down Resistance Select Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PUS_0_100_kOhm_Pull_Down
100 kOhm Pull Down
0x1 : PUS_1_47_Kohm_Pull_Up
47 Kohm Pull Up
0x2 : PUS_2_100_kOhm_Pull_Up
100 kOhm Pull Up
0x3 : PUS_3_22_kOhm_Pull_Up
22 kOhm Pull Up
End of enumeration elements list.
SW_PAD_CTL_GRP_DS_ADDR SW GRP Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_GRP_DS_CTRL SW GRP Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
SW_PAD_CTL_GRP_DS_DAT0 SW GRP Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
SW_PAD_CTL_GRP_DS_DAT1 SW GRP Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
SW_PAD_CTL_GRP_DS_DAT2 SW GRP Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
SW_PAD_CTL_GRP_DS_DAT3 SW GRP Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
SW_PAD_CTL_GRP_HYS SW GRP Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQMn SW PAD Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_GRP_INSEL_DAT SW GRP Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
SW_PAD_CTL_GRP_INSEL_DQS SW GRP Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
SW_PAD_CTL_GRP_DDRTYPE SW GRP Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DDR_SELECT : DDR Select Field
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0 : DDR_SELECT_0_DDR3_MODE
DDR3 mode
0x2 : DDR_SELECT_2_LPDDR2_LPDDR3
LPDDR2/LPDDR3 modes
0x3 : DDR_SELECT_3
DDR_SELECT_3_HSIC_USB mode
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_n SW PAD Control Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQSn SW PAD Control Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUE : Pull Up/Down or Keeper Selection Field
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper_Selected
Keeper Selected
0x1 : PUE_1_Pull_Up_Down_Selected
Pull Up/Down Selected
End of enumeration elements list.
PKE : Pull Up/Pull Down/Keeper Enable Field
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PKE_0_Pull_Up_Down_and_Keeper_Disabled
Pull Up/Down and Keeper Disabled
0x1 : PKE_1_Pull_Up_Down_or_Keeper_Enabled
Pull Up/Down or Keeper Enabled
End of enumeration elements list.
PUS : Pull Up/Down Resistance Select Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PUS_0_100_kOhm_Pull_Down
100 kOhm Pull Down
0x1 : PUS_1_47_Kohm_Pull_Up
47 Kohm Pull Up
0x2 : PUS_2_100_kOhm_Pull_Up
100 kOhm Pull Up
0x3 : PUS_3_22_kOhm_Pull_Up
22 kOhm Pull Up
End of enumeration elements list.
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
CRPOINT_TRIM : Crosspoint Adjustment Field
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : CRPOINT_TRIM_0_No_adjustment
No adjustment
0x1 : CRPOINT_TRIM_1__70_mV
-70 mV
0x2 : CRPOINT_TRIM_2__70_mV
+70 mV
0x3 : CRPOINT_TRIM_3__140_mV
+140 mV
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_right_shrink
right shrink
0x2 : DCYCLE_TRIM_2_left_shrink
left shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_CKEn SW PAD Control Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUE : Pull Up/Down or Keeper Selection Field
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper_Selected
Keeper Selected
0x1 : PUE_1_Pull_Up_Down_Selected
Pull Up/Down Selected
End of enumeration elements list.
PKE : Pull Up/Pull Down/Keeper Enable Field
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PKE_0_Pull_Up_Down_and_Keeper_Disabled
Pull Up/Down and Keeper Disabled
0x1 : PKE_1_Pull_Up_Down_or_Keeper_Enabled
Pull Up/Down or Keeper Enabled
End of enumeration elements list.
PUS : Pull Up/Down Resistance Select Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PUS_0_100_kOhm_Pull_Down
100 kOhm Pull Down
0x1 : PUS_1_47_Kohm_Pull_Up
47 Kohm Pull Up
0x2 : PUS_2_100_kOhm_Pull_Up
100 kOhm Pull Up
0x3 : PUS_3_22_kOhm_Pull_Up
22 kOhm Pull Up
End of enumeration elements list.
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQMn SW PAD Control Register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_ZQn SW PAD Control Register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DDR_SELECT : DDR Select Field
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0 : DDR_SELECT_0_DDR3_MODE
DDR3 mode
0x2 : DDR_SELECT_2_LPDDR2_LPDDR3
LPDDR2/LPDDR3 modes
0x3 : DDR_SELECT_3
DDR_SELECT_3_HSIC_USB mode
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_n SW PAD Control Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQSn SW PAD Control Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUE : Pull Up/Down or Keeper Selection Field
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper_Selected
Keeper Selected
0x1 : PUE_1_Pull_Up_Down_Selected
Pull Up/Down Selected
End of enumeration elements list.
PKE : Pull Up/Pull Down/Keeper Enable Field
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PKE_0_Pull_Up_Down_and_Keeper_Disabled
Pull Up/Down and Keeper Disabled
0x1 : PKE_1_Pull_Up_Down_or_Keeper_Enabled
Pull Up/Down or Keeper Enabled
End of enumeration elements list.
PUS : Pull Up/Down Resistance Select Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PUS_0_100_kOhm_Pull_Down
100 kOhm Pull Down
0x1 : PUS_1_47_Kohm_Pull_Up
47 Kohm Pull Up
0x2 : PUS_2_100_kOhm_Pull_Up
100 kOhm Pull Up
0x3 : PUS_3_22_kOhm_Pull_Up
22 kOhm Pull Up
End of enumeration elements list.
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
CRPOINT_TRIM : Crosspoint Adjustment Field
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : CRPOINT_TRIM_0_No_adjustment
No adjustment
0x1 : CRPOINT_TRIM_1__70_mV
-70 mV
0x2 : CRPOINT_TRIM_2__70_mV
+70 mV
0x3 : CRPOINT_TRIM_3__140_mV
+140 mV
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_right_shrink
right shrink
0x2 : DCYCLE_TRIM_2_left_shrink
left shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQMn SW PAD Control Register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_CKEn SW PAD Control Register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUE : Pull Up/Down or Keeper Selection Field
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper_Selected
Keeper Selected
0x1 : PUE_1_Pull_Up_Down_Selected
Pull Up/Down Selected
End of enumeration elements list.
PKE : Pull Up/Pull Down/Keeper Enable Field
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PKE_0_Pull_Up_Down_and_Keeper_Disabled
Pull Up/Down and Keeper Disabled
0x1 : PKE_1_Pull_Up_Down_or_Keeper_Enabled
Pull Up/Down or Keeper Enabled
End of enumeration elements list.
PUS : Pull Up/Down Resistance Select Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PUS_0_100_kOhm_Pull_Down
100 kOhm Pull Down
0x1 : PUS_1_47_Kohm_Pull_Up
47 Kohm Pull Up
0x2 : PUS_2_100_kOhm_Pull_Up
100 kOhm Pull Up
0x3 : PUS_3_22_kOhm_Pull_Up
22 kOhm Pull Up
End of enumeration elements list.
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_n SW PAD Control Register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQSn SW PAD Control Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUE : Pull Up/Down or Keeper Selection Field
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper_Selected
Keeper Selected
0x1 : PUE_1_Pull_Up_Down_Selected
Pull Up/Down Selected
End of enumeration elements list.
PKE : Pull Up/Pull Down/Keeper Enable Field
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PKE_0_Pull_Up_Down_and_Keeper_Disabled
Pull Up/Down and Keeper Disabled
0x1 : PKE_1_Pull_Up_Down_or_Keeper_Enabled
Pull Up/Down or Keeper Enabled
End of enumeration elements list.
PUS : Pull Up/Down Resistance Select Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PUS_0_100_kOhm_Pull_Down
100 kOhm Pull Down
0x1 : PUS_1_47_Kohm_Pull_Up
47 Kohm Pull Up
0x2 : PUS_2_100_kOhm_Pull_Up
100 kOhm Pull Up
0x3 : PUS_3_22_kOhm_Pull_Up
22 kOhm Pull Up
End of enumeration elements list.
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
CRPOINT_TRIM : Crosspoint Adjustment Field
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : CRPOINT_TRIM_0_No_adjustment
No adjustment
0x1 : CRPOINT_TRIM_1__70_mV
-70 mV
0x2 : CRPOINT_TRIM_2__70_mV
+70 mV
0x3 : CRPOINT_TRIM_3__140_mV
+140 mV
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_right_shrink
right shrink
0x2 : DCYCLE_TRIM_2_left_shrink
left shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_ZQn SW PAD Control Register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DDR_SELECT : DDR Select Field
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0 : DDR_SELECT_0_DDR3_MODE
DDR3 mode
0x2 : DDR_SELECT_2_LPDDR2_LPDDR3
LPDDR2/LPDDR3 modes
0x3 : DDR_SELECT_3
DDR_SELECT_3_HSIC_USB mode
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQMn SW PAD Control Register
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_n SW PAD Control Register
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_n SW PAD Control Register
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_n SW PAD Control Register
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_n SW PAD Control Register
address_offset : 0x554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_n SW PAD Control Register
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x6CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_n SW PAD Control Register
address_offset : 0x6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_n SW PAD Control Register
address_offset : 0x794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_n SW PAD Control Register
address_offset : 0x85C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_n SW PAD Control Register
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_CLK0 SW PAD Control Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUE : Pull Up/Down or Keeper Selection Field
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper_Selected
Keeper Selected
0x1 : PUE_1_Pull_Up_Down_Selected
Pull Up/Down Selected
End of enumeration elements list.
PKE : Pull Up/Pull Down/Keeper Enable Field
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PKE_0_Pull_Up_Down_and_Keeper_Disabled
Pull Up/Down and Keeper Disabled
0x1 : PKE_1_Pull_Up_Down_or_Keeper_Enabled
Pull Up/Down or Keeper Enabled
End of enumeration elements list.
PUS : Pull Up/Down Resistance Select Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PUS_0_100_kOhm_Pull_Down
100 kOhm Pull Down
0x1 : PUS_1_47_Kohm_Pull_Up
47 Kohm Pull Up
0x2 : PUS_2_100_kOhm_Pull_Up
100 kOhm Pull Up
0x3 : PUS_3_22_kOhm_Pull_Up
22 kOhm Pull Up
End of enumeration elements list.
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
CRPOINT_TRIM : Crosspoint Adjustment Field
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : CRPOINT_TRIM_0_No_adjustment
No adjustment
0x1 : CRPOINT_TRIM_1__70_mV
-70 mV
0x2 : CRPOINT_TRIM_2__70_mV
+70 mV
0x3 : CRPOINT_TRIM_3__140_mV
+140 mV
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_right_shrink
right shrink
0x2 : DCYCLE_TRIM_2_left_shrink
left shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
SW_PAD_CTL_PAD_DDR_ODT SW PAD Control Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUE : Pull Up/Down or Keeper Selection Field
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper_Selected
Keeper Selected
0x1 : PUE_1_Pull_Up_Down_Selected
Pull Up/Down Selected
End of enumeration elements list.
PKE : Pull Up/Pull Down/Keeper Enable Field
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PKE_0_Pull_Up_Down_and_Keeper_Disabled
Pull Up/Down and Keeper Disabled
0x1 : PKE_1_Pull_Up_Down_or_Keeper_Enabled
Pull Up/Down or Keeper Enabled
End of enumeration elements list.
PUS : Pull Up/Down Resistance Select Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PUS_0_100_kOhm_Pull_Down
100 kOhm Pull Down
0x1 : PUS_1_47_Kohm_Pull_Up
47 Kohm Pull Up
0x2 : PUS_2_100_kOhm_Pull_Up
100 kOhm Pull Up
0x3 : PUS_3_22_kOhm_Pull_Up
22 kOhm Pull Up
End of enumeration elements list.
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_INPUT : DDR/CMOS Input Select Field
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DDR_INPUT_0_CMOS_input_type
CMOS input type
0x1 : DDR_INPUT_1_Differential_input_mode
Differential input mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_HSIC_DATA SW PAD Control Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUE : Pull Up/Down or Keeper Selection Field
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper_Selected
Keeper Selected
0x1 : PUE_1_Pull_Up_Down_Selected
Pull Up/Down Selected
End of enumeration elements list.
PUS : Pull Up/Down Resistance Select Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PUS_0_100_kOhm_Pull_Down
100 kOhm Pull Down
0x1 : PUS_1_47_Kohm_Pull_Up
47 Kohm Pull Up
0x2 : PUS_2_100_kOhm_Pull_Up
100 kOhm Pull Up
0x3 : PUS_3_22_kOhm_Pull_Up
22 kOhm Pull Up
End of enumeration elements list.
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_SELECT : DDR Select Field
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0 : DDR_SELECT_0_DDR3_MODE
DDR3 mode
0x2 : DDR_SELECT_2_LPDDR2_LPDDR3
LPDDR2/LPDDR3 modes
0x3 : DDR_SELECT_3
DDR_SELECT_3_HSIC_USB mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_PAD_HSIC_STROBE SW PAD Control Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUE : Pull Up/Down or Keeper Selection Field
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper_Selected
Keeper Selected
0x1 : PUE_1_Pull_Up_Down_Selected
Pull Up/Down Selected
End of enumeration elements list.
PUS : Pull Up/Down Resistance Select Field
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PUS_0_100_kOhm_Pull_Down
100 kOhm Pull Down
0x1 : PUS_1_47_Kohm_Pull_Up
47 Kohm Pull Up
0x2 : PUS_2_100_kOhm_Pull_Up
100 kOhm Pull Up
0x3 : PUS_3_22_kOhm_Pull_Up
22 kOhm Pull Up
End of enumeration elements list.
DSE : Output Drive Strength Select Field
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : DSE_0_Driver_Disabled
Driver Disabled
0x1 : DSE_1_240_Ohm
240 Ohm
0x2 : DSE_2_240_Ohm_2___120_Ohm
240/2=120 Ohm
0x3 : DSE_3_240_3__80_Ohm
240/3=80 Ohm
0x4 : DSE_4_240_4___60_Ohm
240/4=60 Ohm
0x5 : DSE_5_240_5___48_Ohm
240/5=48 Ohm
0x6 : DSE_6_240_6___40_Ohm
240/6=40 Ohm
0x7 : DSE_7_240_7___34_Ohm
240/7=34 Ohm
End of enumeration elements list.
HYS : Input Hysteresis Field
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : HYS_0_CMOS_input
CMOS input
0x1 : HYS_1_Schmitt_trigger_input
Schmitt trigger input
End of enumeration elements list.
DCYCLE_TRIM : Duty Cycle Control Field
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DCYCLE_TRIM_0_no_pulse_shrink
no pulse shrink
0x1 : DCYCLE_TRIM_1_left_shrink
left shrink
0x2 : DCYCLE_TRIM_2_right_shrink
right shrink
0x3 : DCYCLE_TRIM_3_right_shrink
right shrink
End of enumeration elements list.
DDR_TRIM : Output Driver Delay Trim Field
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DDR_TRIM_0_0pS
0pS
0x1 : DDR_TRIM_1_50pS
50pS
0x2 : DDR_TRIM_2_100pS
100pS
0x3 : DDR_TRIM_3_150pS
150pS
End of enumeration elements list.
DDR_SELECT : DDR Select Field
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0 : DDR_SELECT_0_DDR3_MODE
DDR3 mode
0x2 : DDR_SELECT_2_LPDDR2_LPDDR3
LPDDR2/LPDDR3 modes
0x3 : DDR_SELECT_3
DDR_SELECT_3_HSIC_USB mode
End of enumeration elements list.
DDR_ODT : On Die Termination Select Field
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : DDR_ODT_0_No_Termination
No Termination
0x1 : DDR_ODT_1_120_Ohm
120 Ohm
0x2 : DDR_ODT_2_60_Ohm
60 Ohm
0x3 : DDR_ODT_3_40_Ohm
40 Ohm
0x4 : DDR_ODT_4_30_Ohm
30 Ohm
0x5 : DDR_ODT_5_24_Ohm
24 Ohm
0x6 : DDR_ODT_6_20_Ohm
20 Ohm
0x7 : DDR_ODT_7_17_Ohm
17 Ohm
End of enumeration elements list.
SW_PAD_CTL_GRP_PUE SW GRP Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUE : Pull Up/Down or Keeper Selection Field
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper_Selected
Keeper Selected
0x1 : PUE_1_Pull_Up_Down_Selected
Pull Up/Down Selected
End of enumeration elements list.
SW_PAD_CTL_GRP_PUE_DAT SW GRP Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUE : Pull Up/Down or Keeper Selection Field
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PUE_0_Keeper_Selected
Keeper Selected
0x1 : PUE_1_Pull_Up_Down_Selected
Pull Up/Down Selected
End of enumeration elements list.
SW_PAD_CTL_GRP_PKE SW GRP Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKE : Pull Up/Pull Down/Keeper Enable Field
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PKE_0_Pull_Up_Down_and_Keeper_Disabled
Pull Up/Down and Keeper Disabled
0x1 : PKE_1_Pull_Up_Down_or_Keeper_Enabled
Pull Up/Down or Keeper Enabled
End of enumeration elements list.
SW_PAD_CTL_GRP_PKE_DAT SW GRP Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKE : Pull Up/Pull Down/Keeper Enable Field
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PKE_0_Pull_Up_Down_and_Keeper_Disabled
Pull Up/Down and Keeper Disabled
0x1 : PKE_1_Pull_Up_Down_or_Keeper_Enabled
Pull Up/Down or Keeper Enabled
End of enumeration elements list.
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