\n

GPIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PDOR

PDIR

PDDR

PSOR

BDACP0[0]

BDACP0[1]

PCOR

BDACP0[2]

BDACP0[3]

PTOR


PDOR

Port Data Output Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDOR PDOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDO

PDO : Port Data Output
bits : 0 - 31 (32 bit)
access : read-write


PDIR

Port Data Input Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDIR PDIR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDI

PDI : Port Data Input
bits : 0 - 31 (32 bit)
access : read-only


PDDR

Port Data Direction Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDDR PDDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDD

PDD : Port Data Direction
bits : 0 - 31 (32 bit)
access : read-write


PSOR

Port Set Output Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSOR PSOR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTSO

PTSO : Port Set Output
bits : 0 - 31 (32 bit)
access : write-only


BDACP0[0]

Port Byte Domain Access Control Register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDACP0[0] BDACP0[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0ACP D1ACP D2ACP D3ACP D4ACP D5ACP D6ACP D7ACP LK2 VLD

D0ACP : Domain Access Control Policy
bits : 0 - 2 (3 bit)
access : read-write

D1ACP : Domain Access Control Policy
bits : 3 - 5 (3 bit)
access : read-write

D2ACP : Domain Access Control Policy
bits : 6 - 8 (3 bit)
access : read-write

D3ACP : Domain Access Control Policy
bits : 9 - 11 (3 bit)
access : read-write

D4ACP : Domain Access Control Policy
bits : 12 - 14 (3 bit)
access : read-write

D5ACP : Domain Access Control Policy
bits : 15 - 17 (3 bit)
access : read-write

D6ACP : Domain Access Control Policy
bits : 18 - 20 (3 bit)
access : read-write

D7ACP : Domain Access Control Policy
bits : 21 - 23 (3 bit)
access : read-write

LK2 : LK2
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0 : LK2_0

Entire DxACP can be written.

0x1 : LK2_1

Entire DxACP can be written.

0x2 : LK2_2

Domain x can only update the DxACP field; no other D*ACP fields can be written.

0x3 : LK2_3

DxACP is locked (read-only) until the next reset.

End of enumeration elements list.

VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : VLD_0

The DxACP assignment is invalid.

0x1 : VLD_1

The DxACP assignment is valid.

End of enumeration elements list.


BDACP0[1]

Port Byte Domain Access Control Register 0
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDACP0[1] BDACP0[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0ACP D1ACP D2ACP D3ACP D4ACP D5ACP D6ACP D7ACP LK2 VLD

D0ACP : Domain Access Control Policy
bits : 0 - 2 (3 bit)
access : read-write

D1ACP : Domain Access Control Policy
bits : 3 - 5 (3 bit)
access : read-write

D2ACP : Domain Access Control Policy
bits : 6 - 8 (3 bit)
access : read-write

D3ACP : Domain Access Control Policy
bits : 9 - 11 (3 bit)
access : read-write

D4ACP : Domain Access Control Policy
bits : 12 - 14 (3 bit)
access : read-write

D5ACP : Domain Access Control Policy
bits : 15 - 17 (3 bit)
access : read-write

D6ACP : Domain Access Control Policy
bits : 18 - 20 (3 bit)
access : read-write

D7ACP : Domain Access Control Policy
bits : 21 - 23 (3 bit)
access : read-write

LK2 : LK2
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0 : LK2_0

Entire DxACP can be written.

0x1 : LK2_1

Entire DxACP can be written.

0x2 : LK2_2

Domain x can only update the DxACP field; no other D*ACP fields can be written.

0x3 : LK2_3

DxACP is locked (read-only) until the next reset.

End of enumeration elements list.

VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : VLD_0

The DxACP assignment is invalid.

0x1 : VLD_1

The DxACP assignment is valid.

End of enumeration elements list.


PCOR

Port Clear Output Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PCOR PCOR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTCO

PTCO : Port Clear Output
bits : 0 - 31 (32 bit)
access : write-only


BDACP0[2]

Port Byte Domain Access Control Register 0
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDACP0[2] BDACP0[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0ACP D1ACP D2ACP D3ACP D4ACP D5ACP D6ACP D7ACP LK2 VLD

D0ACP : Domain Access Control Policy
bits : 0 - 2 (3 bit)
access : read-write

D1ACP : Domain Access Control Policy
bits : 3 - 5 (3 bit)
access : read-write

D2ACP : Domain Access Control Policy
bits : 6 - 8 (3 bit)
access : read-write

D3ACP : Domain Access Control Policy
bits : 9 - 11 (3 bit)
access : read-write

D4ACP : Domain Access Control Policy
bits : 12 - 14 (3 bit)
access : read-write

D5ACP : Domain Access Control Policy
bits : 15 - 17 (3 bit)
access : read-write

D6ACP : Domain Access Control Policy
bits : 18 - 20 (3 bit)
access : read-write

D7ACP : Domain Access Control Policy
bits : 21 - 23 (3 bit)
access : read-write

LK2 : LK2
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0 : LK2_0

Entire DxACP can be written.

0x1 : LK2_1

Entire DxACP can be written.

0x2 : LK2_2

Domain x can only update the DxACP field; no other D*ACP fields can be written.

0x3 : LK2_3

DxACP is locked (read-only) until the next reset.

End of enumeration elements list.

VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : VLD_0

The DxACP assignment is invalid.

0x1 : VLD_1

The DxACP assignment is valid.

End of enumeration elements list.


BDACP0[3]

Port Byte Domain Access Control Register 0
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDACP0[3] BDACP0[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0ACP D1ACP D2ACP D3ACP D4ACP D5ACP D6ACP D7ACP LK2 VLD

D0ACP : Domain Access Control Policy
bits : 0 - 2 (3 bit)
access : read-write

D1ACP : Domain Access Control Policy
bits : 3 - 5 (3 bit)
access : read-write

D2ACP : Domain Access Control Policy
bits : 6 - 8 (3 bit)
access : read-write

D3ACP : Domain Access Control Policy
bits : 9 - 11 (3 bit)
access : read-write

D4ACP : Domain Access Control Policy
bits : 12 - 14 (3 bit)
access : read-write

D5ACP : Domain Access Control Policy
bits : 15 - 17 (3 bit)
access : read-write

D6ACP : Domain Access Control Policy
bits : 18 - 20 (3 bit)
access : read-write

D7ACP : Domain Access Control Policy
bits : 21 - 23 (3 bit)
access : read-write

LK2 : LK2
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0 : LK2_0

Entire DxACP can be written.

0x1 : LK2_1

Entire DxACP can be written.

0x2 : LK2_2

Domain x can only update the DxACP field; no other D*ACP fields can be written.

0x3 : LK2_3

DxACP is locked (read-only) until the next reset.

End of enumeration elements list.

VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : VLD_0

The DxACP assignment is invalid.

0x1 : VLD_1

The DxACP assignment is valid.

End of enumeration elements list.


PTOR

Port Toggle Output Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PTOR PTOR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTTO

PTTO : Port Toggle Output
bits : 0 - 31 (32 bit)
access : write-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.