\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
Port Data Output Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDO : Port Data Output
bits : 0 - 31 (32 bit)
access : read-write
Port Data Input Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDI : Port Data Input
bits : 0 - 31 (32 bit)
access : read-only
Port Data Direction Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDD : Port Data Direction
bits : 0 - 31 (32 bit)
access : read-write
Port Set Output Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PTSO : Port Set Output
bits : 0 - 31 (32 bit)
access : write-only
Port Byte Domain Access Control Register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain Access Control Policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain Access Control Policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain Access Control Policy
bits : 6 - 8 (3 bit)
access : read-write
D3ACP : Domain Access Control Policy
bits : 9 - 11 (3 bit)
access : read-write
D4ACP : Domain Access Control Policy
bits : 12 - 14 (3 bit)
access : read-write
D5ACP : Domain Access Control Policy
bits : 15 - 17 (3 bit)
access : read-write
D6ACP : Domain Access Control Policy
bits : 18 - 20 (3 bit)
access : read-write
D7ACP : Domain Access Control Policy
bits : 21 - 23 (3 bit)
access : read-write
LK2 : LK2
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire DxACP can be written.
0x1 : LK2_1
Entire DxACP can be written.
0x2 : LK2_2
Domain x can only update the DxACP field; no other D*ACP fields can be written.
0x3 : LK2_3
DxACP is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The DxACP assignment is invalid.
0x1 : VLD_1
The DxACP assignment is valid.
End of enumeration elements list.
Port Byte Domain Access Control Register 0
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain Access Control Policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain Access Control Policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain Access Control Policy
bits : 6 - 8 (3 bit)
access : read-write
D3ACP : Domain Access Control Policy
bits : 9 - 11 (3 bit)
access : read-write
D4ACP : Domain Access Control Policy
bits : 12 - 14 (3 bit)
access : read-write
D5ACP : Domain Access Control Policy
bits : 15 - 17 (3 bit)
access : read-write
D6ACP : Domain Access Control Policy
bits : 18 - 20 (3 bit)
access : read-write
D7ACP : Domain Access Control Policy
bits : 21 - 23 (3 bit)
access : read-write
LK2 : LK2
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire DxACP can be written.
0x1 : LK2_1
Entire DxACP can be written.
0x2 : LK2_2
Domain x can only update the DxACP field; no other D*ACP fields can be written.
0x3 : LK2_3
DxACP is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The DxACP assignment is invalid.
0x1 : VLD_1
The DxACP assignment is valid.
End of enumeration elements list.
Port Clear Output Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PTCO : Port Clear Output
bits : 0 - 31 (32 bit)
access : write-only
Port Byte Domain Access Control Register 0
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain Access Control Policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain Access Control Policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain Access Control Policy
bits : 6 - 8 (3 bit)
access : read-write
D3ACP : Domain Access Control Policy
bits : 9 - 11 (3 bit)
access : read-write
D4ACP : Domain Access Control Policy
bits : 12 - 14 (3 bit)
access : read-write
D5ACP : Domain Access Control Policy
bits : 15 - 17 (3 bit)
access : read-write
D6ACP : Domain Access Control Policy
bits : 18 - 20 (3 bit)
access : read-write
D7ACP : Domain Access Control Policy
bits : 21 - 23 (3 bit)
access : read-write
LK2 : LK2
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire DxACP can be written.
0x1 : LK2_1
Entire DxACP can be written.
0x2 : LK2_2
Domain x can only update the DxACP field; no other D*ACP fields can be written.
0x3 : LK2_3
DxACP is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The DxACP assignment is invalid.
0x1 : VLD_1
The DxACP assignment is valid.
End of enumeration elements list.
Port Byte Domain Access Control Register 0
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain Access Control Policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain Access Control Policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain Access Control Policy
bits : 6 - 8 (3 bit)
access : read-write
D3ACP : Domain Access Control Policy
bits : 9 - 11 (3 bit)
access : read-write
D4ACP : Domain Access Control Policy
bits : 12 - 14 (3 bit)
access : read-write
D5ACP : Domain Access Control Policy
bits : 15 - 17 (3 bit)
access : read-write
D6ACP : Domain Access Control Policy
bits : 18 - 20 (3 bit)
access : read-write
D7ACP : Domain Access Control Policy
bits : 21 - 23 (3 bit)
access : read-write
LK2 : LK2
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire DxACP can be written.
0x1 : LK2_1
Entire DxACP can be written.
0x2 : LK2_2
Domain x can only update the DxACP field; no other D*ACP fields can be written.
0x3 : LK2_3
DxACP is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The DxACP assignment is invalid.
0x1 : VLD_1
The DxACP assignment is valid.
End of enumeration elements list.
Port Toggle Output Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PTTO : Port Toggle Output
bits : 0 - 31 (32 bit)
access : write-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.