\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C4 byte (0x0)
mem_usage : registers
protection : not protected
PCC PCTLB Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC ADC0 Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC CMP0 Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC CMP1 Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC DAC0 Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : PCD_0
Divide by 1.
0x1 : PCD_1
Divide by 2.
0x2 : PCD_2
Divide by 3.
0x3 : PCD_3
Divide by 4.
0x4 : PCD_4
Divide by 5.
0x5 : PCD_5
Divide by 6.
0x6 : PCD_6
Divide by 7.
0x7 : PCD_7
Divide by 8.
End of enumeration elements list.
FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FRAC_0
Fractional value is 0.
0x1 : FRAC_1
Fractional value is 1.
End of enumeration elements list.
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC DAC1 Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : PCD_0
Divide by 1.
0x1 : PCD_1
Divide by 2.
0x2 : PCD_2
Divide by 3.
0x3 : PCD_3
Divide by 4.
0x4 : PCD_4
Divide by 5.
0x5 : PCD_5
Divide by 6.
0x6 : PCD_6
Divide by 7.
0x7 : PCD_7
Divide by 8.
End of enumeration elements list.
FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FRAC_0
Fractional value is 0.
0x1 : FRAC_1
Fractional value is 1.
End of enumeration elements list.
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC SNVS Register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC DMA0 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC RGPIO2P0 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC XRDC Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC SEMA42_0 Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC DMA_MUX0 Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC MU_A Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC WDOG0 Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : PCD_0
Divide by 1.
0x1 : PCD_1
Divide by 2.
0x2 : PCD_2
Divide by 3.
0x3 : PCD_3
Divide by 4.
0x4 : PCD_4
Divide by 5.
0x5 : PCD_5
Divide by 6.
0x6 : PCD_6
Divide by 7.
0x7 : PCD_7
Divide by 8.
End of enumeration elements list.
FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FRAC_0
Fractional value is 0.
0x1 : FRAC_1
Fractional value is 1.
End of enumeration elements list.
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC CRC Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LTC Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC TRNG Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPIT0 Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPTIMER0 Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPTIMER1 Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC TPM0 Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC TPM1 Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC FLEXIO0 Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPI2C0 Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPI2C1 Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPI2C2 Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPI2C3 Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC SAI0 Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCD : Peripheral Clock Divider Select
bits : 0 - 15 (16 bit)
access : read-write
FRAC : Peripheral Clock Divider Fraction
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : FRAC_0
Fractional value is 0.
0x1 : FRAC_1
Fractional value is 1.
End of enumeration elements list.
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPSPI0 Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPSPI1 Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPUART0 Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPUART1 Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC PCTLA Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
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