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LTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x7F4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MD

DS

CTX_[13]

ICVS

CTX_[0]

COM

CTX_[1]

CTL

CW

KEY_[0]

CTX_[2]

STA

ESTA

VID1

VID2

CHAVID

CTX_[3]

AADSZ

KEY_[1]

CTX_[4]

CTX_[5]

FIFOSTA

IFIFO

OFIFO

KS

KEY_[2]

CTX_[6]

CTX_[7]

KEY_[3]

CTX_[8]

CTX_[9]

CTX_[10]

CTX_[11]

CTX_[12]


MD

Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MD MD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENC ICV_TEST AS AAI ALG

ENC : Encrypt/Decrypt.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DECRYPT

Decrypt.

0x1 : ENCRYPT

Encrypt.

End of enumeration elements list.

ICV_TEST : ICV Checking / Test AES fault detection.
bits : 1 - 1 (1 bit)
access : read-write

AS : Algorithm State
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0 : UPDATE

Update

0x1 : INITIALIZE

Initialize

0x2 : FINALIZE

Finalize

0x3 : INITFINAL

Initialize/Finalize

End of enumeration elements list.

AAI : Additional Algorithm information
bits : 4 - 12 (9 bit)
access : read-write

ALG : Algorithm
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0x10 : AES

AES

End of enumeration elements list.


DS

Data Size Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DS DS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DS

DS : Data Size
bits : 0 - 11 (12 bit)
access : read-write


CTX_[13]

Context Register
address_offset : 0x106C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTX_[13] CTX_[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write


ICVS

ICV Size Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICVS ICVS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICVS

ICVS : ICV Size, in Bytes
bits : 0 - 4 (5 bit)
access : read-write


CTX_[0]

Context Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTX_[0] CTX_[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write


COM

Command Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COM COM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALL AES

ALL : Reset All Internal Logic
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

0 : NO_RESET

Do Not Reset

0x1 : RESET_ALL

Reset all CHAs in use by this CCB.

End of enumeration elements list.

AES : Reset AESA
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

0 : NO_RESET

Do Not Reset

0x1 : RESET_AESA

Reset AES Accelerator

End of enumeration elements list.


CTX_[1]

Context Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTX_[1] CTX_[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write


CTL

Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM IFE IFR OFE OFR IFS OFS KIS KOS CIS COS KDF KAL

IM : Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : INT_NOT_MASKED

Interrupt not masked.

0x1 : INT_MASKED

Interrupt masked

End of enumeration elements list.

IFE : Input FIFO DMA Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : IFE_DISABLED

DMA Request and Done signals disabled for the Input FIFO.

0x1 : IFE_ENABLED

DMA Request and Done signals enabled for the Input FIFO.

End of enumeration elements list.

IFR : Input FIFO DMA Request Size
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : IFR_1

DMA request size is 1 entry.

0x1 : IFR_4

DMA request size is 4 entries.

End of enumeration elements list.

OFE : Output FIFO DMA Enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : OFE_DISABLED

DMA Request and Done signals disabled for the Output FIFO.

0x1 : OFE_ENABLED

DMA Request and Done signals enabled for the Output FIFO.

End of enumeration elements list.

OFR : Output FIFO DMA Request Size
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : OFR_1

DMA request size is 1 entry.

0x1 : OFR_4

DMA request size is 4 entries.

End of enumeration elements list.

IFS : Input FIFO Byte Swap
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : IFS_NO_SWAP

Do Not Byte Swap Data.

0x1 : IFS_SWAP

Byte Swap Data.

End of enumeration elements list.

OFS : Output FIFO Byte Swap
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : OFS_NO_SWAP

Do Not Byte Swap Data.

0x1 : OFS_SWAP

Byte Swap Data.

End of enumeration elements list.

KIS : Key Register Input Byte Swap
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : KIS_NO_SWAP

Do Not Byte Swap Data.

0x1 : KIS_SWAP

Byte Swap Data.

End of enumeration elements list.

KOS : Key Register Output Byte Swap
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : KOS_NO_SWAP

Do Not Byte Swap Data.

0x1 : KOS_SWAP

Byte Swap Data.

End of enumeration elements list.

CIS : Context Register Input Byte Swap
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : CIS_NO_SWAP

Do Not Byte Swap Data.

0x1 : CIS_SWAP

Byte Swap Data.

End of enumeration elements list.

COS : Context Register Output Byte Swap
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : COS_NO_SWAP

Do Not Byte Swap Data.

0x1 : COS_SWAP

Byte Swap Data.

End of enumeration elements list.

KDF : Key Derivation Function
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : KDF_DISABLE

Key Derivation Function Disabled.

0x1 : KDF_ENABLE

Key Derivation Function Enabled.

End of enumeration elements list.

KAL : Key Register Access Lock
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : KAL_READABLE

Key Register is readable.

0x1 : KAL_NOT_READABLE

Key Register is not readable.

End of enumeration elements list.


CW

Clear Written Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CW CW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM CDS CICV CCR CKR COF CIF

CM : Clear the Mode Register
bits : 0 - 0 (1 bit)
access : write-only

CDS : Clear the Data Size Register
bits : 2 - 2 (1 bit)
access : write-only

CICV : Clear the ICV Size Register
bits : 3 - 3 (1 bit)
access : write-only

CCR : Clear the Context Register
bits : 5 - 5 (1 bit)
access : write-only

CKR : Clear the Key Register
bits : 6 - 6 (1 bit)
access : write-only

COF : Clear Output FIFO
bits : 30 - 30 (1 bit)
access : write-only

CIF : Clear Input FIFO
bits : 31 - 31 (1 bit)
access : write-only


KEY_[0]

Key Registers
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEY_[0] KEY_[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : KEY
bits : 0 - 31 (32 bit)
access : read-write


CTX_[2]

Context Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTX_[2] CTX_[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write


STA

Status Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STA STA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AB DI EI

AB : AESA Busy
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : AESA_IDLE

AESA Idle

0x1 : AESA_BUSY

AESA Busy.

End of enumeration elements list.

DI : Done Interrupt
bits : 16 - 16 (1 bit)
access : read-write

EI : Error Interrupt
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

0 : NOT_ERROR_INT

Not Error.

0x1 : ERROR_INT

Error Interrupt.

End of enumeration elements list.


ESTA

Error Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ESTA ESTA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRID1 CL1

ERRID1 : Error ID 1
bits : 0 - 3 (4 bit)
access : read-only

Enumeration:

0x1 : MODE_ERROR

Mode Error

0x2 : DATA_SIZE_ERROR

Data Size Error

0x3 : KEY_SIZE_ERROR

Key Size Error

0x6 : DATA_OUT_OF_SEQ_ERROR

Data Arrived out of Sequence Error

0xA : ICV_CHECK_FAIL

ICV Check Failed

0xB : INTERNAL_HARD_FAIL

Internal Hardware Failure

0xC : CCM_AAD_SIZE_ERROR

CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and AAD povided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.)

0xF : INVALID_ENGINE_SEL_ERROR

Invalid Crypto Engine Selected

End of enumeration elements list.

CL1 : algorithms
bits : 8 - 11 (4 bit)
access : read-only

Enumeration:

0 : GEN_ERROR

General Error

0x1 : AES_ERROR

AES

End of enumeration elements list.


VID1

Version ID Register
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VID1 VID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIN_REV MAJ_REV IP_ID

MIN_REV : Minor revision number.
bits : 0 - 7 (8 bit)
access : read-only

MAJ_REV : Major revision number.
bits : 8 - 15 (8 bit)
access : read-only

IP_ID : ID(0x0034).
bits : 16 - 31 (16 bit)
access : read-only


VID2

Version ID 2 Register
address_offset : 0x4F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VID2 VID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECO_REV ARCH_ERA

ECO_REV : ECO revision number.
bits : 0 - 7 (8 bit)
access : read-only

ARCH_ERA : Architectural ERA.
bits : 8 - 15 (8 bit)
access : read-only


CHAVID

CHA Version ID Register
address_offset : 0x4F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHAVID CHAVID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AESREV AESVID

AESREV : AES Revision Number
bits : 0 - 3 (4 bit)
access : read-only

AESVID : AES Version ID
bits : 4 - 7 (4 bit)
access : read-only


CTX_[3]

Context Register
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTX_[3] CTX_[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write


AADSZ

AAD Size Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AADSZ AADSZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AADSZ AL

AADSZ : AAD size in Bytes, mod 16
bits : 0 - 3 (4 bit)
access : read-write

AL : AAD Last
bits : 31 - 31 (1 bit)
access : read-write


KEY_[1]

Key Registers
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEY_[1] KEY_[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : KEY
bits : 0 - 31 (32 bit)
access : read-write


CTX_[4]

Context Register
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTX_[4] CTX_[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write


CTX_[5]

Context Register
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTX_[5] CTX_[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write


FIFOSTA

FIFO Status Register
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFOSTA FIFOSTA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFL IFF OFL OFF

IFL : Input FIFO Level
bits : 0 - 6 (7 bit)
access : read-only

IFF : Input FIFO Full
bits : 15 - 15 (1 bit)
access : read-only

OFL : Output FIFO Level
bits : 16 - 22 (7 bit)
access : read-only

OFF : Output FIFO Full
bits : 31 - 31 (1 bit)
access : read-only


IFIFO

Input Data FIFO
address_offset : 0x7E0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFIFO IFIFO write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFIFO

IFIFO : IFIFO
bits : 0 - 31 (32 bit)
access : write-only


OFIFO

Output Data FIFO
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OFIFO OFIFO read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFIFO

OFIFO : Output FIFO
bits : 0 - 31 (32 bit)
access : read-only


KS

Key Size Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KS KS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KS

KS : Key Size
bits : 0 - 4 (5 bit)
access : write-only


KEY_[2]

Key Registers
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEY_[2] KEY_[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : KEY
bits : 0 - 31 (32 bit)
access : read-write


CTX_[6]

Context Register
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTX_[6] CTX_[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write


CTX_[7]

Context Register
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTX_[7] CTX_[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write


KEY_[3]

Key Registers
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEY_[3] KEY_[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : KEY
bits : 0 - 31 (32 bit)
access : read-write


CTX_[8]

Context Register
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTX_[8] CTX_[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write


CTX_[9]

Context Register
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTX_[9] CTX_[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write


CTX_[10]

Context Register
address_offset : 0xCDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTX_[10] CTX_[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write


CTX_[11]

Context Register
address_offset : 0xE08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTX_[11] CTX_[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write


CTX_[12]

Context Register
address_offset : 0xF38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTX_[12] CTX_[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write



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