\n
address_offset : 0x0 Bytes (0x0)
size : 0x5C byte (0x0)
mem_usage : registers
protection : not protected
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-TVAL
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CVAL
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-TCTRL
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-TVAL
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CVAL
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-TCTRL
Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEATURE : Feature Number
bits : 0 - 15 (16 bit)
access : read-only
MINOR : Minor Version Number
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Major Version Number
bits : 24 - 31 (8 bit)
access : read-only
Module Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIE0 : Channel 0 Timer Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TIE0_0
Disabled
0x1 : TIE0_1
Enabled
End of enumeration elements list.
TIE1 : Channel 1 Timer Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TIE1_0
Disabled
0x1 : TIE1_1
Enabled
End of enumeration elements list.
TIE2 : Channel 2 Timer Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : TIE2_0
Disabled
0x1 : TIE2_1
Enabled
End of enumeration elements list.
TIE3 : Channel 3 Timer Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TIE3_0
Disabled
0x1 : TIE3_1
Enabled
End of enumeration elements list.
Set Timer Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET_T_EN_0 : Set Timer 0 Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SET_T_EN_0_0
No effect
0x1 : SET_T_EN_0_1
Enables Timer Channel 0
End of enumeration elements list.
SET_T_EN_1 : Set Timer 1 Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SET_T_EN_1_0
No Effect
0x1 : SET_T_EN_1_1
Enables Timer Channel 1
End of enumeration elements list.
SET_T_EN_2 : Set Timer 2 Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SET_T_EN_2_0
No Effect
0x1 : SET_T_EN_2_1
Enables Timer Channel 2
End of enumeration elements list.
SET_T_EN_3 : Set Timer 3 Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SET_T_EN_3_0
No effect
0x1 : SET_T_EN_3_1
Enables Timer Channel 3
End of enumeration elements list.
Clear Timer Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR_T_EN_0 : Clear Timer 0 Enable
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
0 : CLR_T_EN_0_0
No action
0x1 : CLR_T_EN_0_1
Clear the Timer Enable bit (TCTRL0[T_EN]) for Timer Channel 0
End of enumeration elements list.
CLR_T_EN_1 : Clear Timer 1 Enable
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
0 : CLR_T_EN_1_0
No Action
0x1 : CLR_T_EN_1_1
Clear the Timer Enable bit (TCTRL1[T_EN]) for Timer Channel 1
End of enumeration elements list.
CLR_T_EN_2 : Clear Timer 2 Enable
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
0 : CLR_T_EN_2_0
No Action
0x1 : CLR_T_EN_2_1
Clear the Timer Enable bit (TCTRL2[T_EN]) for Timer Channel 2
End of enumeration elements list.
CLR_T_EN_3 : Clear Timer 3 Enable
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
0 : CLR_T_EN_3_0
No Action
0x1 : CLR_T_EN_3_1
Clear the Timer Enable bit (TCTRL3[T_EN]) for Timer Channel 3
End of enumeration elements list.
Timer Value Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMR_VAL : Timer Value
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : TMR_VAL_0
Invalid load value in compare mode
0x1 : TMR_VAL_1
Invalid load value in compare mode
0x2 : TMR_VAL_2
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x3 : TMR_VAL_3
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x4 : TMR_VAL_4
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x5 : TMR_VAL_5
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x6 : TMR_VAL_6
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x7 : TMR_VAL_7
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x8 : TMR_VAL_8
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x9 : TMR_VAL_9
In compare mode: the value to be loaded; in capture mode, the value of the timer
End of enumeration elements list.
Current Timer Value
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMR_CUR_VAL : Current Timer Value
bits : 0 - 31 (32 bit)
access : read-only
Timer Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_EN : Timer Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : T_EN_0
Timer Channel is disabled
0x1 : T_EN_1
Timer Channel is enabled
End of enumeration elements list.
CHAIN : Chain Channel
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : CHAIN_0
Channel Chaining is disabled. The channel timer runs independently.
0x1 : CHAIN_1
Channel Chaining is enabled. The timer decrements on the previous channel's timeout.
End of enumeration elements list.
MODE : Timer Operation Mode
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : MODE_0
32-bit Periodic Counter
0x1 : MODE_1
Dual 16-bit Periodic Counter
0x2 : MODE_2
32-bit Trigger Accumulator
0x3 : MODE_3
32-bit Trigger Input Capture
End of enumeration elements list.
TSOT : Timer Start On Trigger
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : TSOT_0
Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI))
0x1 : TSOT_1
Timer starts to decrement when a rising edge on a selected trigger is detected
End of enumeration elements list.
TSOI : Timer Stop On Interrupt
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : TSOI_0
The channel timer does not stop after timeout
0x1 : TSOI_1
The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected.
End of enumeration elements list.
TROT : Timer Reload On Trigger
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : TROT_0
Timer will not reload on the selected trigger
0x1 : TROT_1
Timer will reload on the selected trigger
End of enumeration elements list.
TRG_SRC : Trigger Source
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TRG_SRC_0
Selects external triggers
0x1 : TRG_SRC_1
Selects internal triggers
End of enumeration elements list.
TRG_SEL : Trigger Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TRG_SEL_0
Timer channel 0 - 3 trigger source is selected
0x1 : TRG_SEL_1
Timer channel 0 - 3 trigger source is selected
0x2 : TRG_SEL_2
Timer channel 0 - 3 trigger source is selected
0x3 : TRG_SEL_3
Timer channel 0 - 3 trigger source is selected
End of enumeration elements list.
Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Number of Timer Channels
bits : 0 - 7 (8 bit)
access : read-only
EXT_TRIG : Number of External Trigger Inputs
bits : 8 - 15 (8 bit)
access : read-only
Timer Value Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMR_VAL : Timer Value
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : TMR_VAL_0
Invalid load value in compare mode
0x1 : TMR_VAL_1
Invalid load value in compare mode
0x2 : TMR_VAL_2
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x3 : TMR_VAL_3
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x4 : TMR_VAL_4
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x5 : TMR_VAL_5
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x6 : TMR_VAL_6
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x7 : TMR_VAL_7
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x8 : TMR_VAL_8
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x9 : TMR_VAL_9
In compare mode: the value to be loaded; in capture mode, the value of the timer
End of enumeration elements list.
Current Timer Value
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMR_CUR_VAL : Current Timer Value
bits : 0 - 31 (32 bit)
access : read-only
Timer Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_EN : Timer Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : T_EN_0
Timer Channel is disabled
0x1 : T_EN_1
Timer Channel is enabled
End of enumeration elements list.
CHAIN : Chain Channel
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : CHAIN_0
Channel Chaining is disabled. The channel timer runs independently.
0x1 : CHAIN_1
Channel Chaining is enabled. The timer decrements on the previous channel's timeout.
End of enumeration elements list.
MODE : Timer Operation Mode
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : MODE_0
32-bit Periodic Counter
0x1 : MODE_1
Dual 16-bit Periodic Counter
0x2 : MODE_2
32-bit Trigger Accumulator
0x3 : MODE_3
32-bit Trigger Input Capture
End of enumeration elements list.
TSOT : Timer Start On Trigger
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : TSOT_0
Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI))
0x1 : TSOT_1
Timer starts to decrement when a rising edge on a selected trigger is detected
End of enumeration elements list.
TSOI : Timer Stop On Interrupt
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : TSOI_0
The channel timer does not stop after timeout
0x1 : TSOI_1
The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected.
End of enumeration elements list.
TROT : Timer Reload On Trigger
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : TROT_0
Timer will not reload on the selected trigger
0x1 : TROT_1
Timer will reload on the selected trigger
End of enumeration elements list.
TRG_SRC : Trigger Source
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TRG_SRC_0
Selects external triggers
0x1 : TRG_SRC_1
Selects internal triggers
End of enumeration elements list.
TRG_SEL : Trigger Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TRG_SEL_0
Timer channel 0 - 3 trigger source is selected
0x1 : TRG_SEL_1
Timer channel 0 - 3 trigger source is selected
0x2 : TRG_SEL_2
Timer channel 0 - 3 trigger source is selected
0x3 : TRG_SEL_3
Timer channel 0 - 3 trigger source is selected
End of enumeration elements list.
Module Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M_CEN : Module Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : M_CEN_0
Disable peripheral clock to timers
0x1 : M_CEN_1
Enable peripheral clock to timers
End of enumeration elements list.
SW_RST : Software Reset Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SW_RST_0
Timer channels and registers are not reset
0x1 : SW_RST_1
Reset timer channels and registers
End of enumeration elements list.
DOZE_EN : DOZE Mode Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DOZE_EN_0
Stop timer channels in DOZE mode
0x1 : DOZE_EN_1
Allow timer channels to continue to run in DOZE mode
End of enumeration elements list.
DBG_EN : Debug Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DBG_EN_0
Stop timer channels in Debug mode
0x1 : DBG_EN_1
Allow timer channels to continue to run in Debug mode
End of enumeration elements list.
Timer Value Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMR_VAL : Timer Value
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : TMR_VAL_0
Invalid load value in compare mode
0x1 : TMR_VAL_1
Invalid load value in compare mode
0x2 : TMR_VAL_2
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x3 : TMR_VAL_3
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x4 : TMR_VAL_4
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x5 : TMR_VAL_5
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x6 : TMR_VAL_6
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x7 : TMR_VAL_7
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x8 : TMR_VAL_8
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x9 : TMR_VAL_9
In compare mode: the value to be loaded; in capture mode, the value of the timer
End of enumeration elements list.
Current Timer Value
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMR_CUR_VAL : Current Timer Value
bits : 0 - 31 (32 bit)
access : read-only
Timer Control Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_EN : Timer Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : T_EN_0
Timer Channel is disabled
0x1 : T_EN_1
Timer Channel is enabled
End of enumeration elements list.
CHAIN : Chain Channel
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : CHAIN_0
Channel Chaining is disabled. The channel timer runs independently.
0x1 : CHAIN_1
Channel Chaining is enabled. The timer decrements on the previous channel's timeout.
End of enumeration elements list.
MODE : Timer Operation Mode
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : MODE_0
32-bit Periodic Counter
0x1 : MODE_1
Dual 16-bit Periodic Counter
0x2 : MODE_2
32-bit Trigger Accumulator
0x3 : MODE_3
32-bit Trigger Input Capture
End of enumeration elements list.
TSOT : Timer Start On Trigger
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : TSOT_0
Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI))
0x1 : TSOT_1
Timer starts to decrement when a rising edge on a selected trigger is detected
End of enumeration elements list.
TSOI : Timer Stop On Interrupt
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : TSOI_0
The channel timer does not stop after timeout
0x1 : TSOI_1
The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected.
End of enumeration elements list.
TROT : Timer Reload On Trigger
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : TROT_0
Timer will not reload on the selected trigger
0x1 : TROT_1
Timer will reload on the selected trigger
End of enumeration elements list.
TRG_SRC : Trigger Source
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TRG_SRC_0
Selects external triggers
0x1 : TRG_SRC_1
Selects internal triggers
End of enumeration elements list.
TRG_SEL : Trigger Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TRG_SEL_0
Timer channel 0 - 3 trigger source is selected
0x1 : TRG_SEL_1
Timer channel 0 - 3 trigger source is selected
0x2 : TRG_SEL_2
Timer channel 0 - 3 trigger source is selected
0x3 : TRG_SEL_3
Timer channel 0 - 3 trigger source is selected
End of enumeration elements list.
Module Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIF0 : Channel 0 Timer Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TIF0_0
Timer has not timed out
0x1 : TIF0_1
Timeout has occurred (timer has timed out)
End of enumeration elements list.
TIF1 : Channel 1 Timer Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TIF1_0
Timer has not timed out
0x1 : TIF1_1
Timeout has occurred (timer has timed out)
End of enumeration elements list.
TIF2 : Channel 2 Timer Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : TIF2_0
Timer has not timed out
0x1 : TIF2_1
Timeout has occurred (timer has timed out)
End of enumeration elements list.
TIF3 : Channel 3 Timer Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TIF3_0
Timer has not timed out
0x1 : TIF3_1
Timeout has occurred (timer has timed out)
End of enumeration elements list.
Timer Value Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMR_VAL : Timer Value
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : TMR_VAL_0
Invalid load value in compare mode
0x1 : TMR_VAL_1
Invalid load value in compare mode
0x2 : TMR_VAL_2
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x3 : TMR_VAL_3
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x4 : TMR_VAL_4
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x5 : TMR_VAL_5
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x6 : TMR_VAL_6
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x7 : TMR_VAL_7
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x8 : TMR_VAL_8
In compare mode: the value to be loaded; in capture mode, the value of the timer
0x9 : TMR_VAL_9
In compare mode: the value to be loaded; in capture mode, the value of the timer
End of enumeration elements list.
Current Timer Value
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMR_CUR_VAL : Current Timer Value
bits : 0 - 31 (32 bit)
access : read-only
Timer Control Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_EN : Timer Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : T_EN_0
Timer Channel is disabled
0x1 : T_EN_1
Timer Channel is enabled
End of enumeration elements list.
CHAIN : Chain Channel
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : CHAIN_0
Channel Chaining is disabled. The channel timer runs independently.
0x1 : CHAIN_1
Channel Chaining is enabled. The timer decrements on the previous channel's timeout.
End of enumeration elements list.
MODE : Timer Operation Mode
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : MODE_0
32-bit Periodic Counter
0x1 : MODE_1
Dual 16-bit Periodic Counter
0x2 : MODE_2
32-bit Trigger Accumulator
0x3 : MODE_3
32-bit Trigger Input Capture
End of enumeration elements list.
TSOT : Timer Start On Trigger
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : TSOT_0
Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI))
0x1 : TSOT_1
Timer starts to decrement when a rising edge on a selected trigger is detected
End of enumeration elements list.
TSOI : Timer Stop On Interrupt
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : TSOI_0
The channel timer does not stop after timeout
0x1 : TSOI_1
The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected.
End of enumeration elements list.
TROT : Timer Reload On Trigger
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : TROT_0
Timer will not reload on the selected trigger
0x1 : TROT_1
Timer will reload on the selected trigger
End of enumeration elements list.
TRG_SRC : Trigger Source
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TRG_SRC_0
Selects external triggers
0x1 : TRG_SRC_1
Selects internal triggers
End of enumeration elements list.
TRG_SEL : Trigger Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TRG_SEL_0
Timer channel 0 - 3 trigger source is selected
0x1 : TRG_SEL_1
Timer channel 0 - 3 trigger source is selected
0x2 : TRG_SEL_2
Timer channel 0 - 3 trigger source is selected
0x3 : TRG_SEL_3
Timer channel 0 - 3 trigger source is selected
End of enumeration elements list.
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